SteROI-D: System Design and Mapping for Stereo Depth Inference on Regions of Interest

Andrew Berkovich; Jack Erhardt; Reid Pinkham; Zhengya Zhang; Ziang Li

REVIEW 2 major objections 5 minor 31 references

SteROI-D: System Design and Mapping for Stereo Depth Inference on Regions of Interest

T0 review · 2 major / 5 minor · reviewed 2026-08-07 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read SteROI-D shows that stereo depth estimation for AR/VR can run on a 28nm ASIC at 30 FPS with up to 4.35x less energy than a full-frame baseline by processing only regions of interest and reusing detections across five frames.

desk verdict A credible ROI-based stereo depth ASIC with a genuinely useful mapping methodology, but the 4.35x energy claim rests on an untested 5-frame detection amortization. read the letter →

arxiv 2502.09528 v1 pith:JL2F5YNQ submitted 2025-02-13 cs.CV cs.AR

Jack Erhardt , Ziang Li , Reid Pinkham , Andrew Berkovich , Zhengya Zhang This is my paper · ORCID

classification cs.CVcs.AR

keywords stereodepthestimationregion-of-interestprocessinglow-powerAR/VRhardware-softwareco-designtemporalsparsitymappingmethodologyenergy-efficientacceleratorobjecttracking

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Stereo depth estimation—computing distance from two camera images—is one of the most energy-hungry tasks on augmented and virtual reality headsets, and this paper tries to make it practical on battery-limited devices. It proposes SteROI-D, a full system that runs the depth network only on regions of interest (ROIs) around tracked objects, and reuses one object detection across several frames by relying on a lightweight correlation-filter tracker in between. The paper reports that a 28nm prototype achieves up to a 4.35x reduction in total system energy per inference compared with a baseline ASIC that processes every full frame, while still meeting 30 FPS real-time operation. The key new machinery is a mapping methodology that splits mapping decisions between offline optimization and cheap runtime selection, so a continuous range of ROI sizes can be handled efficiently. If the results hold, ROI-based stereo depth becomes energy-viable for AR/VR, not just a theoretical saving.

What carries the argument

The load-bearing mechanism is Binned Mapping. Because the space of possible ROI sizes is continuous and large, a mapping cannot be stored per size offline nor generated online. The paper divides the ROI size range into a small number of bins, and assigns each bin a precomputed mapping descriptor—a choice of DRAM mode (which activations are streamed or buffered in DRAM), per-layer dataflow assignment, and tile, PE, and SCU shutoff configuration. At runtime the controller only needs to identify the bin and instantiate the low-level mapping. Two architectural features make the binned mappings effective: Special Compute Units (SCUs) that execute non-parameterized stereo operations (vector L1 norm, min, argmin) which vector-matrix multiplier arrays cannot handle efficiently, and multipacket NoC routing that sends a single data packet to multiple destinations, cutting redundant data movement. The binning is what transforms ROI variability from a mapping explosion into a tractable offline-online split.

What would settle it

Run the SteROI-D pipeline on a long stereo sequence with ground-truth object positions, executing detection every five frames and correlation-filter tracking in between, and measure both total energy and depth error on the tracked ROIs against full-frame inference. If the tracker loses the objects often enough to raise depth error above an application threshold, or if holding accuracy requires detection more often than every five frames, the claimed 4.35x energy saving does not hold at that accuracy.

Watch

Extended reading notes

Core claim

On its own terms, the paper claims that ROI and temporal sparsity, used together, reduce the total energy of a stereo depth pipeline by up to 4.35x without dropping below 30 FPS. ROI sparsity means the network computes disparity only inside bounding boxes around objects of interest, which in egocentric datasets are typically orders of magnitude smaller than the full image. Temporal sparsity means the expensive object detector runs only every fifth frame, while correlation-filter tracking on cheaper L1 processors maintains ROI boxes in the other frames. The paper presents a simulation and design-space exploration using HITNet as the depth network, TinyYOLOv3 for detection, and KITTI and EPIC-KITCHENS ROI distributions to show that the savings survive detection and tracking overhead, and that the system's energy scales with ROI size. It also introduces specialized compute units and multipacket NoC routing to handle the non-convolutional operations and data movement that stereo depth networks need.

Load-bearing premise

The energy savings assume object detection can run only every fifth frame and that a correlation-filter tracker keeps the ROI boxes accurately on the objects in between; the paper reports no tracking accuracy or drift measurements, so if detection must run more often or the boxes drift, the 4.35x savings shrink.

Editorial extensions

If this is right

A SteROI-D-class processor can keep real-time 30 FPS stereo depth while cutting per-inference energy by up to 4.35x against a full-frame ASIC baseline.
Energy per inference scales with ROI size: small ROIs are dominated by static power, large ROIs by DRAM I/O, so the mapping must treat them differently.
Two mapping bins capture most of the energy gain; additional bins give diminishing returns, but extra bins can help for high-variance ROI distributions.
A conventional edge platform like the Jetson Orin Nano cannot sustain 30 FPS on the same ROI-based HITNet workload, while SteROI-D is designed to.
The system-level costs that do not scale with ROI—sensor, transmit, tracking, and detection—limit the total savings, which is why detection is run only every fifth frame.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

Beyond the paper's own claims, the Binned Mapping split between offline optimization and runtime bin selection could apply to other variable-size workloads, such as segmentation or object detection, on hierarchical accelerators whenever a mapping descriptor can be expressed compactly.
The 4.35x figure depends on the assumed 5-frame detection cadence and on the tracker holding the ROI on the object; measuring actual tracking drift on long egocentric sequences would tell whether the cadence can be stretched further or must be shortened.
The reported end-point-error degradation for narrow ROIs implies a tunable quality-energy knob: an application can enforce a minimum ROI width and trade depth accuracy for energy, and the bin boundaries could be positioned to honor that minimum.
Because the simulator uses 16-bit operations and 28nm post-layout energy estimates, the balance between static, DRAM, and compute energy would shift on a more advanced process node or with lower-precision arithmetic; the mapping methodology itself is what carries over.

Share X Bluesky LinkedIn Reddit HN

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Read SteROI-D. Short version: it's a real system design paper with one load-bearing assumption that's still unverified.

The genuinely new pieces are Binned Mapping – splitting offline-optimized mapping descriptors across ROI-size intervals so runtime variable ROIs stay cheap – plus the SCUs for non-parameterized stereo ops and the multipacket NoC broadcast. I checked against ANSA, EyeCoD, Argos; those aren't in prior work. The first-of-kind claim for ROI-based stereo depth processing holds up as far as I can tell.

The paper also does credible engineering legwork: the energy numbers come from a multi-part simulator with post-APR TSMC 28nm extraction for PE/SCU/SRAM, cited DRAM/NoC models, and a measured Jetson Orin Nano comparison (400 mJ per 90k crop inference at 30 FPS). The bin-count and ROI-distribution ablations are informative, and the DRAM-mode progression (Fig 7) is a nice way to reduce the mapping space.

The soft spot is the one the stress test flags. Fig 12's caption states the 4.35x assumes 'object detection runs every 5 frames.' Section 3 interleaves object detection with a correlation-filter tracker to keep ROIs valid in between, but there is no experiment measuring tracker accuracy, drift, or how much depth quality degrades when the crop is slightly misplaced. Fig 3 only evaluates static crops. The detection/tracking energy in the stack doesn't scale with ROI size, so the amortization factor of 5 directly sets the headline number. If the detector had to run every 3 frames, the per-inference savings would shrink roughly 40%; every frame, and ROI processing could cost more than the baseline. The paper is not internally inconsistent – it flags the assumption in the caption – but it's an externality-heavy pillar for a central quantitative claim.

Two smaller concerns: the no-ROI baseline is described only as an aggregate number (55.16 mJ, 58.49 FPS), so I can't tell what it contains; and no simulator or final architecture parameters are released, so all numerical claims are single-source.

Who it's for: people building low-power AR/VR depth accelerators and hardware-software co-design mapping frameworks. Worth a serious referee: yes. I'd send it out with the explicit expectation that reviewers either get a tracking sensitivity analysis and a clearer baseline or the claim gets reframed as conditional. If the authors release the simulator and show the tracker doesn't drift, this becomes a solid contribution rather than a plausible one.

Referee Report

2 major / 5 minor

Summary. The paper proposes SteROI-D, a stereo-depth inference system for AR/VR that processes only regions of interest (ROIs) and temporally amortizes expensive object detection with correlation-filter tracking on low-power L1 processors. The L2 accelerator combines vector-matrix-multiplier PEs with special compute units for non-parameterized stereo operations, a multipacket NoC, and a binned offline/online mapping methodology for variable ROI sizes. A multi-part simulator using post-APR TSMC 28nm energy extraction, DRAM/NoC models, and a measured Jetson Orin Nano comparison is used to report up to a 4.35x reduction in total system energy per inference versus a no-ROI baseline ASIC at a 30 FPS constraint. The paper also includes ablations over bin count and ROI distributions.

Significance. If the 4.35x energy claim holds, the paper makes a credible case that ROI-based stereo depth estimation can become energy-viable for battery-limited AR/VR devices. The strengths are the anchoring of the energy model in post-APR TSMC 28nm simulation, the external Jetson Orin Nano comparison with measured power, the systematic binned mapping methodology, and the ablation across ROI distributions and bin counts. The central result is not circular: energy numbers derive from architectural simulation plus cited DRAM/NoC models, not from fitting a constant to a target. The main weakness is that the headline number rests on an unmeasured temporal-sparsity assumption, namely that object detection need only run every 5 frames with a correlation-filter tracker maintaining accurate ROIs in between. The baseline comparison is also under-specified. These issues are fixable but are load-bearing for the central quantitative claim.

major comments (2)

[§3 and Fig. 12] The 4.35x per-inference savings in §6.2 is computed under the explicit assumption in the Fig. 12 caption that object detection runs every 5 frames and the ROI distribution follows KITTI. Section 3 proposes correlation-filter tracking on the L1 processors to keep ROI boxes valid in the intermediate frames, but no experiment in the paper measures tracking accuracy, drift, or the resulting depth-quality degradation over those frames; Fig. 3 evaluates static crops only. If the detector must run every 3 frames rather than every 5, or if tracker drift mislocates crops and degrades ROI depth quality below an application tolerance, the L2 detection overhead in the 12.68 mJ per-inference stack grows and the headline 4.35x ratio shrinks accordingly. This is not an internal inconsistency, but it is the least externally supported load-bearing assumption in the paper.
[§6.2, Fig. 12] The no-ROI baseline comparison is under-specified. Figure 12 reports only aggregate energy for the baseline (55.16 mJ per inference at 58.49 FPS) with no breakdown into compute, SRAM, DRAM, NoC, and static components, and no statement of which processor configuration, DRAM mode, or mapping was used for the baseline. Since the 4.35x ratio is the paper's headline quantitative result, this baseline must be reproducible; as written, a reader cannot determine whether the baseline uses the same L2 fabric with full-frame processing or a different architecture, nor how the 55.16 mJ figure is derived from the simulator.

minor comments (5)

[§4] The word 'heretoafter' in the system-design paragraph is a typo for 'hereafter', and the surrounding sentence should be split for clarity.
[§2.4] The word 'imfeasible' in the final sentence of Section 2.4 is a typo for 'infeasible'.
[Fig. 6 caption] The caption appears to repeat the same text three times; please clarify the intended comparison between MAC counts and stereo-depth-specific operation counts.
[§6] The statement that compiling HITNet per ROI size with ONNX and TensorRT 'provides optimistic estimates' should specify the exact TensorRT precision, batch size, and power measurement methodology beyond 'Jetson Stats', so the reader can assess the degree of optimism.
[Fig. 2 caption and §3] The caption and text refer to KITTI as an 'egocentric dataset', but KITTI is an autonomous-driving dataset from a vehicle-mounted camera; this should be corrected or relabeled as a non-egocentric source.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the energy-savings claim is produced by a forward simulation from explicitly stated architectural and workload assumptions, not by fitting or by definitional recycling.

full rationale

The paper's central quantitative claim (up to 4.35x total-system energy reduction, Section 6.2) is the output of a multi-part energy simulator: post-APR 28nm PE/SCU/SRAM energies, external DRAM models [16,17], NoC energy from prior ANSA work [20], sensor/MIPI/uTSV estimates, a measured Jetson Orin Nano comparison, and L1/detection estimates. The 4.35x is the ratio of the simulated baseline (55.16 mJ/inference) to the simulated SteROI-D design (12.68 mJ/inference) under the explicitly stated assumption in the Fig. 12 caption that object detection runs every 5 frames and that ROIs follow the KITTI distribution. This assumption is load-bearing and unvalidated by a tracking-drift experiment, but it is not circular: the 5-frame cadence is an input to the simulation, not a parameter fitted to reproduce the 4.35x number, and the paper does not present the cadence as a derived prediction. The ROI-to-energy relationship is independently reasoned via MAC counts and simulator component energies rather than defined in terms of the final savings. The only notable self-citation, ANSA [20] for NoC energy and the hierarchical architecture basis, is a normal use of prior work as a component model; it is neither a uniqueness theorem nor an ansatz imported to force the conclusion, so it does not constitute load-bearing circularity. No equation in the paper is shown to be equivalent to its own output by construction.

Assumptions & free parameters 4 free parameters · 5 assumptions · 2 invented entities

The headline 4.35x energy result depends on hand-chosen workload and architecture premises: bin count, 5-frame detection interval, and unreported final processor configuration are free parameters; ROI distribution representativeness, tracker fidelity, and post-APR energy accuracy are unverified axioms; the SCU and multipacket NoC are proposed components without independent silicon evidence.

free parameters (4)

Number of mapping bins = 1 to 8, swept in Fig. 8; exact value for 4.35x result not stated
Divides the ROI size range into intervals, each with an offline-optimized mapping descriptor. The ablation shows diminishing returns beyond 2 bins; it is a design choice, not derived from first principles.
Object detection interval = 5 frames
Fig. 12 assumes full object detection runs every 5 frames with correlation-filter tracking in between. This temporal-sparsity factor directly sets detection energy overhead and is not derived from tracking accuracy constraints.
Processor sub-configuration and SCU/PE counts = not reported for final design
Tile-level shutoff, SCU-to-PE balance, and SRAM allocation are chosen by design-space exploration; the paper does not report the final configuration behind Fig. 12, so the energy result depends on unreleased hand-optimized choices.
Bin boundaries and DRAM mode thresholds = not reported
The Binned Mapping assigns a DRAM mode and dataflow descriptor to each ROI interval; boundaries are optimized offline but not tabulated, making the headline energy result hard to reproduce.

assumptions (5)

domain assumption HITNet and TinyYOLOv3 are representative of AR/VR stereo-depth and object-detection workloads.
Section 6 uses HITNet for depth and TinyYOLOv3 for detection; if real workloads differ in compute and energy mix, the 4.35x may not transfer.
domain assumption Depth degradation on ROI crops is acceptable for downstream AR/VR tasks.
Section 3 measures EPE and 3-pixel error against full-frame outputs but sets no application-level tolerance; the ROI width analysis shows narrow crops degrade substantially.
ad hoc to paper Correlation-filter tracking maintains ROI boxes for 4 intermediate frames without requiring re-detection.
Fig. 12 assumes detection every 5 frames; the paper cites references for tracker efficiency but does not evaluate tracking accuracy or drift on the target datasets.
domain assumption Post-APR TSMC 28nm energy models for PE, SCU, and SRAM plus cited DRAM and NoC models predict realized system energy closely.
Section 6 reports no fabricated silicon or measured prototype; all headline energy numbers are simulator outputs, so modeling error propagates directly into the 4.35x claim.
domain assumption KITTI and EPIC-Kitchens ROI size distributions represent typical AR/VR use.
Figures 2, 9, and 12 optimize and evaluate against these egocentric datasets; other distributions with larger or overlapping ROIs would reduce savings.

invented entities (2)

Special Compute Unit (SCU)
purpose: Accelerate non-parameterized stereo-depth operations (vector difference, L1 norm, min/argmin, warp/aggregate, maxpool) that VMM-based PEs handle inefficiently.
Proposed in Section 4; only simulated energy and latency from post-APR models exist, with no silicon measurement in the paper.
Multipacket NoC routing
purpose: Reduce redundant data movement when one activation is sent to many destination PEs or tiles; DOR guarantees each link carries a packet once.
Introduced in Section 4 as a design mechanism; energy and latency are taken from the NoC model in prior work, not from measured hardware.

how reviews work

0 comments

Cite this review

Pith. "Pith review of SteROI-D: System Design and Mapping for Stereo Depth Inference on Regions of Interest." pith.science (2026). https://pith.science/paper/JL2F5YNQ

@misc{pith2026250209528,
  author       = {Pith},
  title        = {Pith review of: SteROI-D: System Design and Mapping for Stereo Depth Inference on Regions of Interest},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/JL2F5YNQ}},
  note         = {Machine review of arXiv:2502.09528}
}

read the original abstract

Machine learning algorithms have enabled high quality stereo depth estimation to run on Augmented and Virtual Reality (AR/VR) devices. However, high energy consumption across the full image processing stack prevents stereo depth algorithms from running effectively on battery-limited devices. This paper introduces SteROI-D, a full stereo depth system paired with a mapping methodology. SteROI-D exploits Region-of-Interest (ROI) and temporal sparsity at the system level to save energy. SteROI-D's flexible and heterogeneous compute fabric supports diverse ROIs. Importantly, we introduce a systematic mapping methodology to effectively handle dynamic ROIs, thereby maximizing energy savings. Using these techniques, our 28nm prototype SteROI-D design achieves up to 4.35x reduction in total system energy compared to a baseline ASIC.

Figures

Figures reproduced from arXiv: 2502.09528 by the authors.

**Figure 2.** Distribution of ROI sizes across various object track [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗

**Figure 3.** EPE (left) and 3-pixel error (right) for HITNet [ [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗

Figures from the paper (7 more)

**Figure 4.** Figure 4: The design features stereo sensors and a custom accelerator integrated into an SoC, which is a typical design for AR platforms [7]. Furthermore, each sensor is co-packaged with a lightweight L1 processor, based on [23]. These processors are responsible for handling the…

**Figure 4.** Figure 4: SteROI-D system design. Matrix Buffer Shuffle Buffer Vec. Buffer VMM Vector SRAM Matrix SRAM Accum NoC Router NoC Router SRAM 0 SRAM 1 Vec. Buffer Vec. Buffer Diff + L1 norm Accum Min + Argmin v PE PE PE PE Core DRAM I/O Controller NoC Router Tile [PITH_FULL_IMAGE:fig…

**Figure 7.** Figure 7: By successively buffering or streaming large activa [PITH_FULL_IMAGE:figures/full_fig_p004_7.png]

**Figure 6.** Figure 6: Conventional CNN operation counts (e.g. convolu [PITH_FULL_IMAGE:figures/full_fig_p004_6.png]

**Figure 8.** Figure 8: Effect of number of bins. Increasing bin count re [PITH_FULL_IMAGE:figures/full_fig_p005_8.png]

**Figure 11.** Figure 11: The energy consumption is primarily influenced by static [PITH_FULL_IMAGE:figures/full_fig_p006_11.png]

**Figure 10.** Figure 10: Energy consumption of Jetson Orin Nano run [PITH_FULL_IMAGE:figures/full_fig_p006_10.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

31 extracted references · 18 canonical work pages

[1]

[n. d.]. qualcomm.com. https://www.qualcomm.com/content/dam/qcomm- martech/dm-assets/documents/whitepaper_-_driving_the_new_era_of_ immersive_experiences_-_qualcomm.pdf. [Accessed 20-11-2024]

work page 2024
[2]

Bolme, J

David S. Bolme, J. Ross Beveridge, Bruce A. Draper, and Yui Man Lui. 2010. Visual object tracking using adaptive correlation filters. In 2010 IEEE Computer Society Conference on Computer Vision and Pattern Recognition . 2544–2550. https: //doi.org/10.1109/CVPR.2010.5539960 ISSN: 1063-6919

arXiv 2010
[3]

Sungpill Choi, Jinsu Lee, Kyuho Lee, and Hoi-Jun Yoo. 2018. A 9.02mW CNN- stereo-based real-time 3D hand-gesture recognition processor for smart mobile devices. In 2018 IEEE International Solid-State Circuits Conference - (ISSCC) . 220–

work page 2018
[4]

Francesco Conti, Gianna Paulin, Angelo Garofalo, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, and Luca Benini. 2024. Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing. IEEE Journal of Solid-State Circuits 59, 1 (Jan. 2024), 128–142....

work page arXiv 2024
[5]

Dima Damen, Hazel Doughty, Giovanni Maria Farinella, Antonino Furnari, Jian Ma, Evangelos Kazakos, Davide Moltisanti, Jonathan Munro, Toby Perrett, Will Price, and Michael Wray. 2022. Rescaling Egocentric Vision: Collection, Pipeline and Challenges for EPIC-KITCHENS-100. International Journal of Computer Vision (IJCV) 130 (2022), 33–55. https://doi.org/10...

doi:10.1007/s11263-021-01531-2 2022
[6]

Ryoji Eki, Satoshi Yamada, Hiroyuki Ozawa, Hitoshi Kai, Kazuyuki Okuike, Hareesh Gowtham, Hidetomo Nakanishi, Edan Almog, Yoel Livne, Gadi Yuval, Eli Zyss, and Takashi Izawa. 2021. 9.6 A 1/2.3inch 12.3Mpixel with On-Chip 4.97TOPS/W CNN Processor Back-Illuminated Stacked CMOS Image Sensor. In 2021 IEEE International Solid-State Circuits Conference (ISSCC) ...

arXiv 2021
[7]

Jakob Engel, Kiran Somasundaram, Michael Goesele, Albert Sun, Alexander Gamino, Andrew Turner, Arjang Talattof, Arnie Yuan, Bilal Souti, Brighid Mered- ith, Cheng Peng, Chris Sweeney, Cole Wilson, Dan Barnes, Daniel DeTone, David Caruso, Derek Valleroy, Dinesh Ginjupalli, Duncan Frost, Edward Miller, Elias Mueggler, Evgeniy Oleinik, Fan Zhang, Guruprasad ...

arXiv 2023
[8]

Andreas Geiger, Philip Lenz, and Raquel Urtasun. 2012. Are we ready for Au- tonomous Driving? The KITTI Vision Benchmark Suite. In Conference on Com- puter Vision and Pattern Recognition (CVPR)

work page 2012

Show all 31 references

[9]

Jorge Gomez, Saavan Patel, Syed Shakib Sarwar, Ziyun Li, Raffaele Capoccia, Zhao Wang, Reid Pinkham, Andrew Berkovich, Tsung-Hsun Tsai, Barbara De Salvo, and Chiao Liu. 2022. Distributed On-Sensor Compute System for AR/VR Devices: A Semi-Analytical Simulation Framework for Pow...

2022 doi arXiv
[10]

Odrika Iqbal, Saquib Siddiqui, Joshua Martin, Sameeksha Katoch, Andreas Spanias, Daniel Bliss, and Suren Jayasuriya. 2020. Design and FPGA Implementa- tion of an Adaptive video Subsampling Algorithm for Energy-Efficient Single Ob- ject Tracking. , 3065-3069 pages. https://doi....

2020
[11]

Sameh Khamis, Sean Fanello, Christoph Rhemann, Adarsh Kowdle, Julien Valentin, and Shahram Izadi. 2018. StereoNet: Guided Hierarchical Refinement for Real-Time Edge-Aware Depth Prediction. In Proceedings of the European Conference on Computer Vision (ECCV)

2018
[12]

Johannes Kopf, Kevin Matzen, Suhib Alsisan, Ocean Quigley, Francis Ge, Yang- ming Chong, Josh Patterson, Jan-Michael Frahm, Shu Wu, Matthew Yu, Peizhao Zhang, Zijian He, Peter Vajda, Ayush Saraf, and Michael Cohen. 2020. One Shot 3D Photography. arXiv:2008.12298 [cs.CV]

2020 arXiv
[13]

Chiao Liu, Andrew Berkovich, Song Chen, Hans Reyserhove, Syed Shakib Sarwar, and Tsung-Hsun Tsai. 2019. Intelligent Vision Systems – Bringing Human- Machine Interface to AR/VR. In 2019 IEEE International Electron Devices Meeting (IEDM). 10.5.1–10.5.4. https://doi.org/10.1109/I...

2019
[14]

Chiao Liu, Song Chen, Tsung-Hsun Tsai, Barbara de Salvo, and Jorge Gomez
[15]

Moritz Menze and Andreas Geiger. 2015. Object Scene Flow for Autonomous Vehicles. In Conference on Computer Vision and Pattern Recognition (CVPR)

2015
[16]

Micron. [n. d.]. LPDDR5 Memory Data Sheet. https://www.micron.com/products/ dram/lpddr5
[17]

Micron. 2022. LPDDR4/LPDDR4X SDRAM

2022
[18]

Li-Shiuan Peh and Natalie Enright Jerger. 2009. On-Chip Networks (1st ed.). Morgan and Claypool Publishers

2009
[19]

Reid Pinkham, Andrew Berkovich, and Zhengya Zhang. 2021. Near-Sensor Distributed DNN Processing for Augmented and Virtual Reality. IEEE Journal on Emerging and Selected Topics in Circuits and Systems 11, 4 (2021), 663–676. https://doi.org/10.1109/JETCAS.2021.3121259

2021
[20]

Reid Pinkham, Jack Erhardt, Barbara De Salvo, Andrew Berkovich, and Zhengya Zhang. 2023. ANSA: Adaptive Near-Sensor Architecture for Dynamic DNN Processing in Compact Form Factors. , 1256-1269 pages. https://doi.org/10.1109/ TCSI.2022.3228725

2023
[21]

Joseph Redmon and Ali Farhadi. 2018. YOLOv3: An Incremental Improvement. https://arxiv.org/abs/1804.02767v1

2018 arXiv
[22]

Mark Sandler, Andrew Howard, Menglong Zhu, Andrey Zhmoginov, and Liang- Chieh Chen. 2018. MobileNetV2: Inverted Residuals and Linear Bottlenecks. In Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

2018
[23]

Moritz Scherer, Manuel Eggimann, Alfio Di Mauro, Arpan Suravi Prasad, Francesco Conti, Davide Rossi, Jorge Tomás Gómez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, Barbara De Salvo, and Luca Benini. 2023. Siracusa: A Low-Power On-Sensor RISC-V SoC for Extended Reality Visual Proc...

2023
[24]

Min-Woong Seo, Myunglae Chu, Hyun-Yong Jung, Suksan Kim, Jiyoun Song, Daehee Bae, Sanggwon Lee, Junan Lee, Sung-Yong Kim, Jongyeon Lee, Minkyung Kim, Gwi-Deok Lee, Heesung Shim, Changyong Um, Changhwa Kim, In-Gyu Baek, Doowon Kwon, Hongki Kim, Hyuksoon Choi, Jonghyun Go, Jungc...

2022
[25]

Faranak Shamsafar, Samuel Woerz, Rafia Rahim, and Andreas Zell. 2021. Mo- bileStereoNet: Towards Lightweight Deep Networks for Stereo Matching. https: //arxiv.org/abs/2108.09770v1

2021 arXiv
[26]

Vladimir Tankovich, Christian Hane, Yinda Zhang, Adarsh Kowdle, Sean Fanello, and Sofien Bouaziz. 2021. HITNet: Hierarchical Iterative Tile Refinement Network for Real-time Stereo Matching. In Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition (C...

2021
[27]

Haoran You, Cheng Wan, Yang Zhao, Zhongzhi Yu, Yonggan Fu, Jiayi Yuan, Shang Wu, Shunyao Zhang, Yongan Zhang, Chaojian Li, Vivek Boominathan, Ashok Veeraraghavan, Ziyun Li, and Yingyan Lin. 2022. EyeCoD: Eye Tracking System Acceleration via Flatcam-Based Algorithm & Accelerato...

2022
[28]

Junkang Zhu, Wei Tang, Ching-En Lee, Haolei Ye, Eric McCreath, and Zhengya Zhang. 2022. VOTA: A Heterogeneous Multicore Visual Object Tracking Accel- erator Using Correlation Filters. IEEE Journal of Solid-State Circuits 57, 11 (2022), 3490–3502. https://doi.org/10.1109/JSSC.2...

2022
[29]

zjjMaiMai. 2021. TinyHITNet. https://github.com/zjjMaiMai/TinyHITNet

2021
[222]

https://doi.org/10.1109/ISSCC.2018.8310263

2018
[2022]

In 2022 IEEE International Solid-State Circuits Conference (ISSCC), Vol

Augmented Reality - The Next Frontier of Image Sensors and Compute Systems. In 2022 IEEE International Solid-State Circuits Conference (ISSCC), Vol. 65. 426–428. https://doi.org/10.1109/ISSCC42614.2022.9731584

2022

Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.

[1] [1]

[n. d.]. qualcomm.com. https://www.qualcomm.com/content/dam/qcomm- martech/dm-assets/documents/whitepaper_-_driving_the_new_era_of_ immersive_experiences_-_qualcomm.pdf. [Accessed 20-11-2024]

work page 2024

[2] [2]

Bolme, J

David S. Bolme, J. Ross Beveridge, Bruce A. Draper, and Yui Man Lui. 2010. Visual object tracking using adaptive correlation filters. In 2010 IEEE Computer Society Conference on Computer Vision and Pattern Recognition . 2544–2550. https: //doi.org/10.1109/CVPR.2010.5539960 ISSN: 1063-6919

arXiv 2010

[3] [3]

Sungpill Choi, Jinsu Lee, Kyuho Lee, and Hoi-Jun Yoo. 2018. A 9.02mW CNN- stereo-based real-time 3D hand-gesture recognition processor for smart mobile devices. In 2018 IEEE International Solid-State Circuits Conference - (ISSCC) . 220–

work page 2018

[4] [4]

Francesco Conti, Gianna Paulin, Angelo Garofalo, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, and Luca Benini. 2024. Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing. IEEE Journal of Solid-State Circuits 59, 1 (Jan. 2024), 128–142....

work page arXiv 2024

[5] [5]

Dima Damen, Hazel Doughty, Giovanni Maria Farinella, Antonino Furnari, Jian Ma, Evangelos Kazakos, Davide Moltisanti, Jonathan Munro, Toby Perrett, Will Price, and Michael Wray. 2022. Rescaling Egocentric Vision: Collection, Pipeline and Challenges for EPIC-KITCHENS-100. International Journal of Computer Vision (IJCV) 130 (2022), 33–55. https://doi.org/10...

doi:10.1007/s11263-021-01531-2 2022

[6] [6]

Ryoji Eki, Satoshi Yamada, Hiroyuki Ozawa, Hitoshi Kai, Kazuyuki Okuike, Hareesh Gowtham, Hidetomo Nakanishi, Edan Almog, Yoel Livne, Gadi Yuval, Eli Zyss, and Takashi Izawa. 2021. 9.6 A 1/2.3inch 12.3Mpixel with On-Chip 4.97TOPS/W CNN Processor Back-Illuminated Stacked CMOS Image Sensor. In 2021 IEEE International Solid-State Circuits Conference (ISSCC) ...

arXiv 2021

[7] [7]

Jakob Engel, Kiran Somasundaram, Michael Goesele, Albert Sun, Alexander Gamino, Andrew Turner, Arjang Talattof, Arnie Yuan, Bilal Souti, Brighid Mered- ith, Cheng Peng, Chris Sweeney, Cole Wilson, Dan Barnes, Daniel DeTone, David Caruso, Derek Valleroy, Dinesh Ginjupalli, Duncan Frost, Edward Miller, Elias Mueggler, Evgeniy Oleinik, Fan Zhang, Guruprasad ...

arXiv 2023

[8] [8]

Andreas Geiger, Philip Lenz, and Raquel Urtasun. 2012. Are we ready for Au- tonomous Driving? The KITTI Vision Benchmark Suite. In Conference on Com- puter Vision and Pattern Recognition (CVPR)

work page 2012