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SCALE-Sim v3: A modular cycle-accurate systolic accelerator simulator for end-to-end system analysis

T0 review · 3 major / 5 minor · reviewed 2026-08-16 · deepseek-v4-flash

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Pith's one-line read SCALE-Sim v3 argues that modeling DRAM stalls, energy, sparsity, layout, and multi-core changes design conclusions: output-stationary dataflow beats weight-stationary by 30.1% once DRAM stalls are counted.

desk verdict A useful integration of known components into a widely used simulator, but the headline DRAM-stall result is explicitly deferred and the integrated stack is never validated end-to-end. read the letter →

arxiv 2504.15377 v2 pith:OGWEQNX2 submitted 2025-04-21 cs.PF cs.AR

Ritik Raj , Sarbartha Banerjee , Nikhil Chandra , Zishen Wan , Jianming Tong , Ananda Samajdar , Tushar Krishna This is my paper · ORCID
classification cs.PFcs.AR
keywords cycle-accuratesimulationsystolicarraysAIacceleratordesignsparsematrixmultiplicationDRAMmodelingdatalayoutenergyestimationmulti-coreaccelerators
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

SCALE-Sim v3 is a cycle-accurate simulator for systolic-array AI accelerators that adds five capabilities its predecessor lacked: multiple tensor cores, sparse matrix support, detailed DRAM timing, on-chip data-layout and bank-conflict modeling, and energy/power estimation. The paper's central claim is that these additions change design conclusions rather than merely refine them. Compute-only simulation says weight-stationary dataflow is 21% faster than output-stationary on six ResNet18 layers, but once DRAM stalls are included, output-stationary shows 30.1% lower execution cycles. Likewise, for ViT-base a 128x128 array is 6.53x faster than a 32x32 array by latency, yet the 32x32 array is 2.86x more energy-efficient and the 64x64 array wins on energy-delay product. If the integrated model is right, designers can see full-system latency, bandwidth, and power trade-offs that compute-only tools miss.

What carries the argument

The load-bearing mechanism is the integration layer that connects the systolic compute engine to memory, layout, and energy models through cycle-accurate traces and action counts. The compute core generates memory traces and per-access action counts; a DRAM simulator returns round-trip latencies that are replayed through finite request queues to create stalls; a bank-level layout model computes slowdown from concurrent accesses to the same SRAM bank; and an energy estimator converts action counts, such as random versus repeated reads and idle versus gated MACs, into power and energy. Spatio-temporal partitioning extends the predecessor's spatial-partition runtime equations, and the sparse core supports layer-wise and row-wise N:M sparsity with blocked ELLPACK or compressed-row/column storage. These pieces are composed so that the same workload and mapping can be evaluated for latency, bandwidth, and energy in one run.

What would settle it

A concrete check: take the same six ResNet18 layers and the paper's DDR4 configuration, simulate output-stationary and weight-stationary dataflows in the full SCALE-Sim v3 stack, and compare against an RTL model of the array with real DRAM timing; the claim predicts output-stationary has 30.1% fewer execution cycles, so a measured weight-stationary advantage, or an error well beyond the five percent used for component validation, would falsify the integrated-accuracy claim.

Watch

Extended reading notes

Core claim

SCALE-Sim v3 is a modular, cycle-accurate systolic accelerator simulator that extends its predecessor with multi-core spatio-temporal partitioning and hierarchical memory, layer-wise and row-wise N:M sparsity, a cycle-accurate DRAM interface, precise bank-level data-layout modeling, and architecture-level energy modeling. The discovery claim is that including these full-system effects reverses or reshapes conclusions drawn from compute-cycle-only simulation. The paper reports that weight-stationary beats output-stationary by 21% in compute cycles, but output-stationary has 30.1% lower execution cycles when DRAM stalls are factored in; and for ViT-base, a 128x128 array is 6.53x faster than a 32x32 array in latency while the 32x32 array is 2.86x more energy-efficient, with the 64x64 array best on energy-delay product. The paper also shows that sparsity cuts memory needs: a latency-constrained dense core requires 3.00 MB of on-chip memory, whereas a 2:4 sparse core requires 768 kB.

Load-bearing premise

The load-bearing premise is that individually validated components, including systolic compute, DRAM timing, data layout, and energy counts, remain accurate when composed into one simulator, since no experiment validates the complete stack with all five features interacting.

Editorial extensions

If this is right

  • Array-size rankings depend on the metric: a 128x128 array wins on latency, a 32x32 array wins on energy, and a 64x64 array wins on energy-delay product for ViT-base, so single-metric design-space searches can be misleading.
  • Dataflow selection should be memory-aware, because compute-only rankings (weight-stationary 21% faster than output-stationary) can flip once DRAM stalls are included (output-stationary 30.1% lower execution cycles).
  • Sparsity can trade compute for memory capacity: a latency-constrained ResNet-18 design needs 3.00 MB of on-chip memory when dense but only 768 kB with 2:4 sparsity.
  • Memory request-queue depth is a first-order performance knob: average total cycles drop 3.76x going from 32 to 128 entries and a further 38% at 512 entries.
  • Increasing the number of on-chip SRAM banks consistently reduces data-layout slowdown for all three dataflows in the reported workloads.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • I infer that the weight-stationary versus output-stationary reversal is not a universal property but a function of request-queue depth and layer memory intensity; a useful extension would map the crossover point across queue sizes and DRAM technologies.
  • If the integrated accuracy holds, the simulator makes it practical to search the joint space of array shape, bank count, queue depth, and N:M sparsity for Pareto-optimal designs, which the paper demonstrates only for a few isolated comparisons.
  • The layout results suggest a cheap architectural lever: for fixed on-chip bandwidth, adding banks reduces stalls, so designers may prefer wider-but-shallower memories; this follows from the paper's slowdown equations but is not stated as a recommendation.
  • A testable extension is to feed the generated action counts into a power or thermal model, since the counts already distinguish idle, repeated, and random accesses.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper presents SCALE-Sim v3, an extension of the SCALE-Sim v2 systolic-array simulator that adds five features: multi-core simulation with spatio-temporal partitioning and hierarchical memories, layer-wise and row-wise sparse SpMM support, Ramulator-based DRAM and main-memory modeling, on-chip data-layout/bank-conflict modeling, and Accelergy-based energy/power estimation. The authors argue that these additions enable end-to-end system analysis and change accelerator design conclusions: a 128x128 array is 6.53x faster than a 32x32 array for ViT-base on latency, while the smaller array is 2.86x more energy-efficient; the 64x64 array is best on energy-delay product; and including DRAM stalls reverses the WS-vs-OS dataflow ranking for ResNet18 layers, with OS exhibiting 30.1% lower execution cycles. The paper includes component-level validation for sparsity, Accelergy integration, and Ramulator integration, plus comparisons of simulation time and design choices against SCALE-Sim v2.

Significance. If the results hold, SCALE-Sim v3 fills a genuine gap: it is a modular, open-source, cycle-accurate simulator that combines sparsity, multi-core scaling, DRAM, data-layout, and energy modeling in one tool, with a public GitHub repository. Strengths of the paper include the explicit component validations cited (Ramulator against Micron DDR4 RTL, Accelergy against PnR for Eyeriss and a systolic array, sparse-core validation against VEGETA RTL and Ampere 2:4 reports), the low simulation overhead of the individual features, and the clean integration workflow through trace files and action counts. The main risk is that the paper's headline design-changing conclusions, particularly the DRAM-stall reversal and the energy-delay comparisons, currently rest on incomplete reporting and an unvalidated composition of separately validated components.

major comments (3)
  1. [Section V-B, Steps 1-3; Section IX-B] The DRAM-stall workflow is a single non-iterated pass: Step 1 generates a memory trace with cycle timestamps from the no-stall systolic-array simulator; Step 2 feeds that trace to Ramulator to obtain round-trip latencies; Step 3 reruns SCALE-Sim with finite request queues and those latencies. The rerun changes request arrival times and queue occupancy, which changes Ramulator's row-buffer and bank-conflict behavior, which changes the latencies, which changes the stalls. The paper provides no fixed-point iteration, convergence check, or error bound for this approximation, and Section IX-B explicitly states 'We will add an analysis in the revision.' Since WS and OS have different access orders and reuse patterns, the abstract's claim that 'when factoring in DRAM stalls, OS dataflow exhibits 30.1% lower execution cycles compared to WS' is not substantiated as written. Please add the deferred analysis and either justify the single-pass approximation empirically or iterate to a fixed point.
  2. [Table V] Three EdP entries in Table V are off by a factor of 10. For RCNN 32x32, the table reports 159,932 while latency 126,830 times energy 12.61 equals 1,599,326.3; for RCNN 64x64, the table reports 148,161 while 52,243 times 28.36 equals 1,481,611.5; and for ViT-base 32x32, the table reports 490,356.9 while 444,970 times 11.02 equals 4,903,569.4. The text's ViT-base conclusion ('64x64 outperforms both') survives the correction, but the table as printed makes the energy-delay comparisons partly unreadable and the RCNN comparison misleading. Please correct these entries and audit all derived numbers in the paper.
  3. [Section VIII; Section V-B] The validation section validates SCALE-Sim v2, Ramulator, Accelergy, and the sparse cores individually, but no experiment validates the integrated v3 stack with all five features interacting. This is load-bearing because the headline DRAM-stall result depends on composing compute timing, Ramulator latencies, finite request queues, and layout-induced stalls; double-counting or mis-sequencing in this composition could change the reported rankings. Please add an end-to-end validation or a cross-check that exercises the full integrated simulator (e.g., against a full-system RTL/FPGA measurement, or against an analytical model with known answer) to confirm that the composition is accurate.
minor comments (5)
  1. [Section IV-B, Step 2] The sentence 'we assume that the first N rows have non-zero elements and the remaining N−M rows have zero elements' should read 'M−N rows' rather than 'N−M rows.'
  2. [Section I, Limitation 4] The sentence contains grammatical and clarity issues: 'a ignorance of the actual data layout could lead to a magnitude of performance off' should be rewritten (e.g., 'ignoring the actual data layout could lead to a significant performance error').
  3. [Section VII-A, Step 1] The tool name 'Accelergy' is misspelled as 'Accerlegy' in the sentence 'The neural network description remains unchanged across SCALE-Sim v3 and Accerlegy.'
  4. [Figure 15] The x-axis labels 'RCNNResNet50ViT' lack separators, making the figure hard to read; please use distinct tick labels.
  5. [Section IX-B] The sentence 'SCALE-Sim v2 shows a 21% reduction in compute cycles ... using weight-stationary (WS) dataflow compared to output-stationary (OS)' is confusing because the 21% is presumably a SCALE-Sim v3 result obtained with v2-style settings; please clarify which simulator produced each number in this comparison.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: SCALE-Sim v3's findings are modular simulation outputs validated against external RTL/PnR references, not fitted predictions or self-citation chains.

full rationale

The paper's central deliverable is a modular simulator whose claimed results are simulation outputs, not fitted parameters renamed as predictions. The compute-cycle equations (Section III-A, Eqs. 1-3) are analytical extensions of the published SCALE-Sim v2 runtime formula, and the spatio-temporal partitioning results are generated by those equations rather than being defined by them. The energy and EdP findings are produced by Accelergy from SCALE-Sim v3 action counts, with validation reported against PnR results for Eyeriss and a systolic array (Section VIII). The memory and DRAM-stall findings use Ramulator round-trip latencies fed through finite request queues; none of these quantities is defined in terms of the headline WS/OS or array-size rankings. Validation targets are external: Micron DDR4 RTL, Ampere sparse tensor core reports, and Vegeta RTL, so the cited tool validations constitute independent evidence rather than a closed self-citation loop. The only notable caveats are the absence of an end-to-end validation of the full integrated stack and the explicitly deferred analysis in Section IX-B ('We will add an analysis in the revision.'); these are correctness and completeness risks, not circularity, because the deferred claim is not assumed as an input anywhere. The paper's lineage with SCALE-Sim v2, co-authored by some of the same authors, is expected tool inheritance and is not load-bearing as a proof step. Accordingly, no circular step is present and the circularity score is 0.

Assumptions & free parameters 0 free parameters · 5 assumptions · 0 invented entities

No parameters are fitted to data; the central claims are simulator outputs over user-selected configurations. The paper relies on four background assumptions: composition of separately validated components is valid; sparse input simplification; synthetic row-wise sparsity; and the SCALE-Sim v2 cycle formula. No new physical entities are introduced.

assumptions (5)
  • domain assumption Separately validated components compose to a valid full-system simulator without end-to-end validation.
    Section VIII validates SCALE-Sim v2, Accelergy, Ramulator, and sparse cores separately; no integrated validation is reported, yet Section IX presents full-system conclusions.
  • ad hoc to paper Sparse operand matrices are representable by non-zero blocks in the first N rows with remaining rows zero.
    Section IV-B Step 2: 'For simplicity, we assume that the first N rows have non-zero elements and the remaining N-M rows have zero elements'; this simplification affects compute-cycle and storage claims.
  • ad hoc to paper Row-wise sparsity ratios are drawn randomly with N <= M/2 for each row, and blocked ELLPACK is used throughout.
    Section IV-B Step 1-2; the paper does not use real sparsity distributions from trained models, so sparsity case studies are synthetic.
  • domain assumption The cycle formulas for spatial and spatio-temporal partitioning (Equations 1-3) are valid generalizations of the SCALE-Sim v2 runtime model.
    Equation 1 is attributed to [24]; Equations 2 and 3 extend it by substituting temporal partition into the pipeline expression without a proof of cycle-level timing equivalence.
  • domain assumption Accelergy's energy estimates and Ramulator's DRAM timing are accurate for the configured memory technologies and 65nm PnR baseline used in validation.
    Section II-D and Section VIII rely on claimed 95% Accelergy accuracy and cycle-accurate Ramulator vs Micron DDR4; these are external claims.

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Cite this review

Pith. "Pith review of SCALE-Sim v3: A modular cycle-accurate systolic accelerator simulator for end-to-end system analysis." pith.science (2026). https://pith.science/paper/OGWEQNX2

@misc{pith2026250415377,
  author       = {Pith},
  title        = {Pith review of: SCALE-Sim v3: A modular cycle-accurate systolic accelerator simulator for end-to-end system analysis},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/OGWEQNX2}},
  note         = {Machine review of arXiv:2504.15377}
}
read the original abstract

The rapid advancements in AI, scientific computing, and high-performance computing (HPC) have driven the need for versatile and efficient hardware accelerators. Existing tools like SCALE-Sim v2 provide valuable cycle-accurate simulations for systolic-array-based architectures but fall short in supporting key modern features such as sparsity, multi-core scalability, and comprehensive memory analysis. To address these limitations, we present SCALE-Sim v3, a modular, cycle-accurate simulator that extends the capabilities of its predecessor. SCALE-Sim v3 introduces five significant enhancements: multi-core simulation with spatio-temporal partitioning and hierarchical memory structures, support for sparse matrix multiplications (SpMM) with layer-wise and row-wise sparsity, integration with Ramulator for detailed DRAM analysis, precise data layout modeling to minimize memory stalls, and energy and power estimation via Accelergy. These improvements enable deeper end-to-end system analysis for modern AI accelerators, accommodating a wide variety of systems and workloads and providing detailed full-system insights into latency, bandwidth, and power efficiency. A 128x128 array is 6.53x faster than a 32x32 array for ViT-base, using only latency as a metric. However, SCALE-Sim v3 finds that 32x32 is 2.86x more energy-efficient due to better utilization and lower leakage energy. For EdP, 64x64 outperforms both 128x128 and 32x32 for ViT-base. SCALE-Sim v2 shows a 21% reduction in compute cycles for six ResNet18 layers using weight-stationary (WS) dataflow compared to output-stationary (OS). However, when factoring in DRAM stalls, OS dataflow exhibits 30.1% lower execution cycles compared to WS, highlighting the critical role of detailed DRAM analysis.

Figures

Figures reproduced from arXiv: 2504.15377 by the authors.

Figure 1
Figure 1. Overview of SCALE-Sim v3 highlighting the new features over SCALE-Sim v2 marked in red [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Spatial and spatio-temporal partitioning [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 4
Figure 4. Shared Input and Weight L2 SRAMs C. Heterogeneous Tensor Cores We add the support for tensor cores, following the naming convention from Google’s TPU [2] where each TensorCore consists of one or more matrix-multiply units (MXUs) and a vector unit. The vector/SIMD unit is used for general computation such as activations and softmax. Similarly, SIMD unit in Meta’s MTIA [4] handles quantization/de-quantization and nonl… view at source ↗
Figures from the paper (9 more)
Figure 3
Figure 3. Figure 3: Compute cycles v/s memory footprint tradeoff for [PITH_FULL_IMAGE:figures/full_fig_p004_3.png]
Figure 5
Figure 5. Figure 5: Total compute cycles (including memory stalls) vs On [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 7
Figure 7. Figure 7: The memory plot shows the memory storage compar [PITH_FULL_IMAGE:figures/full_fig_p006_7.png]
Figure 8
Figure 8. Figure 8: Compute cycle variation shown for Feed Forward layers [PITH_FULL_IMAGE:figures/full_fig_p006_8.png]
Figure 9
Figure 9. Figure 9: We observe a proportional increase in the memory [PITH_FULL_IMAGE:figures/full_fig_p007_9.png]
Figure 12
Figure 12. Figure 12: Slowdown of different dataflows under different [PITH_FULL_IMAGE:figures/full_fig_p008_12.png]
Figure 11
Figure 11. Figure 11: Overview of data layout modeling in multi-bank on [PITH_FULL_IMAGE:figures/full_fig_p008_11.png]
Figure 14
Figure 14. Figure 14: Translation table for action types in Accelergy with a [PITH_FULL_IMAGE:figures/full_fig_p009_14.png]
Figure 15
Figure 15. Figure 15: Energy consumption under different dataflow types [PITH_FULL_IMAGE:figures/full_fig_p010_15.png]

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Reference graph

Works this paper leans on

86 extracted references · 65 canonical work pages · cited by 2 Pith papers

  1. [1]

    Compute trends across three eras of machine learning,

    J. Sevilla, L. Heim, A. Ho, T. Besiroglu, M. Hobbhahn, and P. Villalobos, “Compute trends across three eras of machine learning,” in 2022 International Joint Conference on Neural Networks (IJCNN) , pp. 1–8, IEEE, 2022

    2022

  2. [2]

    Tpu v4: An optically reconfigurable supercomputer for machine learning with hardware sup- port for embeddings,

    N. Jouppi, G. Kurian, S. Li, P. Ma, R. Nagarajan, L. Nai, N. Patil, S. Subramanian, A. Swing, B. Towles, et al. , “Tpu v4: An optically reconfigurable supercomputer for machine learning with hardware sup- port for embeddings,” in Proceedings of the 50th Annual International Symposium on Computer Architecture (ISCA) , pp. 1–14, 2023

    2023

  3. [3]

    Wafer Scale Engine (WSE-2) Dataset

    Cerebras, “Wafer Scale Engine (WSE-2) Dataset.” https://f. hubspotusercontent30.net/hubfs/8968533/WSE-2%20Datasheet.pdf. 11

    arXiv

  4. [4]

    Mtia: First generation silicon targeting meta’s recommendation systems,

    A. Firoozshahian, J. Coburn, R. Levenstein, R. Nattoji, A. Kamath, O. Wu, G. Grewal, H. Aepala, B. Jakka, B. Dreyer, et al. , “Mtia: First generation silicon targeting meta’s recommendation systems,” in Proceedings of the 50th Annual International Symposium on Computer Architecture, pp. 1–13, 2023

    2023

  5. [5]

    Ai accelerator on ibm telum processor: Industrial product,

    C. Lichtenau, A. Buyuktosunoglu, R. Bertran, P. Figuli, C. Jacobi, N. Papandreou, H. Pozidis, A. Saporito, A. Sica, and E. Tzortzatos, “Ai accelerator on ibm telum processor: Industrial product,” in Proceedings of the 49th Annual International Symposium on Computer Architecture , pp. 1012–1028, 2022

    2022

  6. [6]

    Survey of machine learning accelerators,

    A. Reuther, P. Michaleas, M. Jones, V . Gadepally, S. Samsi, and J. Kepner, “Survey of machine learning accelerators,” in 2020 IEEE high performance extreme computing conference (HPEC) , pp. 1–12, IEEE, 2020

    2020

  7. [7]

    Enabling scientific computing on memristive accelerators,

    B. Feinberg, U. K. R. Vengalam, N. Whitehair, S. Wang, and E. Ipek, “Enabling scientific computing on memristive accelerators,” in 2018 ACM/IEEE 45th Annual International Symposium on Computer Archi- tecture (ISCA), pp. 367–382, IEEE, 2018

    2018

  8. [8]

    Burstz+: Eliminating the communi- cation bottleneck of scientific computing accelerators via accelerated compression,

    G. Sun, S. Kang, and S.-W. Jun, “Burstz+: Eliminating the communi- cation bottleneck of scientific computing accelerators via accelerated compression,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 15, no. 2, pp. 1–34, 2022

    work page 2022

Show all 86 references
  1. [9]

    Smurf: Scalar multiple- precision unum risc-v floating-point accelerator for scientific comput- ing,

    A. Bocco, Y . Durand, and F. De Dinechin, “Smurf: Scalar multiple- precision unum risc-v floating-point accelerator for scientific comput- ing,” in Proceedings of the Conference for Next Generation Arithmetic 2019, pp. 1–8, 2019

    2019

  2. [10]

    Com- paring hardware accelerators in scientific applications: A case study,

    R. Weber, A. Gothandaraman, R. J. Hinde, and G. D. Peterson, “Com- paring hardware accelerators in scientific applications: A case study,” IEEE Transactions on Parallel and Distributed Systems , vol. 22, no. 1, pp. 58–68, 2010

    2010

  3. [11]

    Hpc accelerators with 3d memory,

    M. Ujald ´on, “Hpc accelerators with 3d memory,” in 2016 IEEE Intl Conference on Computational Science and Engineering (CSE) and IEEE Intl Conference on Embedded and Ubiquitous Computing (EUC) and 15th Intl Symposium on Distributed Computing and Applications for Business Engin...

    2016

  4. [12]

    A defect-tolerant accelerator for emerging high-performance applications,

    O. Temam, “A defect-tolerant accelerator for emerging high-performance applications,” ACM SIGARCH Computer Architecture News , vol. 40, no. 3, pp. 356–367, 2012

    2012

  5. [13]

    Quantum accelerators for high-performance computing systems,

    K. A. Britt, F. A. Mohiyaddin, and T. S. Humble, “Quantum accelerators for high-performance computing systems,” in 2017 IEEE International Conference on Rebooting Computing (ICRC) , pp. 1–7, IEEE, 2017

    2017

  6. [14]

    A vector systolic accelerator for multi-precision floating- point high-performance computing,

    K. Li, W. Mao, J. Zhou, B. Li, Z. Yang, S. Yang, L. Du, S. Huang, and H. Yu, “A vector systolic accelerator for multi-precision floating- point high-performance computing,” IEEE Transactions on Circuits and Systems II: Express Briefs , vol. 69, no. 10, pp. 4123–4127, 2022

    2022

  7. [15]

    Three-dimensional stacked neural network accelerator architectures for ar/vr applications,

    L. Yang, R. M. Radway, Y .-H. Chen, T. F. Wu, H. Liu, E. Ansari, V . Chandra, S. Mitra, and E. Beign´e, “Three-dimensional stacked neural network accelerator architectures for ar/vr applications,” IEEE Micro , vol. 42, no. 6, pp. 116–124, 2022

    2022

  8. [16]

    A fully-digital and row-pipelined compute-in-memory neural network accelerator with soc-level benchmarking for ar/vr applications,

    H. E. Sumbul, J.-s. Seo, D. H. Morris, and E. Beigne, “A fully-digital and row-pipelined compute-in-memory neural network accelerator with soc-level benchmarking for ar/vr applications,” IEEE Micro, 2023

    2023

  9. [17]

    Fusion-3d: Integrated acceleration for instant 3d reconstruction and real-time rendering,

    S. Li, Y . Zhao, C. Li, B. Guo, J. Zhang, W. Zhu, Z. Ye, C. Wan, and Y . C. Lin, “Fusion-3d: Integrated acceleration for instant 3d reconstruction and real-time rendering,” in 2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 78–91, IEEE, 2024

    2024

  10. [18]

    Automatic domain-specific soc design for autonomous unmanned aerial vehicles,

    S. Krishnan, Z. Wan, K. Bhardwaj, P. Whatmough, A. Faust, S. Neuman, G.-Y . Wei, D. Brooks, and V . J. Reddi, “Automatic domain-specific soc design for autonomous unmanned aerial vehicles,” in 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO) , pp. 300–31...

    2022

  11. [19]

    Orianna: An accelerator generation framework for optimization-based robotic applications,

    Y . Hao, Y . Gan, B. Yu, Q. Liu, Y . Han, Z. Wan, and S. Liu, “Orianna: An accelerator generation framework for optimization-based robotic applications,” in Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Sy...

    2024

  12. [20]

    An energy-efficient and runtime-reconfigurable fpga-based accelerator for robotic localization systems,

    Q. Liu, Z. Wan, B. Yu, W. Liu, S. Liu, and A. Raychowdhury, “An energy-efficient and runtime-reconfigurable fpga-based accelerator for robotic localization systems,” in 2022 IEEE Custom Integrated Circuits Conference (CICC), pp. 01–02, IEEE, 2022

    2022

  13. [21]

    S. Liu, Z. Wan, B. Yu, and Y . Wang, Robotic computing on fpgas . Springer, 2021

    2021

  14. [22]

    Timeloop: A systematic approach to dnn accelerator evaluation,

    A. Parashar, P. Raina, Y . S. Shao, Y .-H. Chen, V . A. Ying, A. Mukkara, R. Venkatesan, B. Khailany, S. W. Keckler, and J. Emer, “Timeloop: A systematic approach to dnn accelerator evaluation,” in 2019 IEEE inter- national symposium on performance analysis of systems and soft...

    2019

  15. [23]

    Stonne: Enabling cycle-level microarchitectural simulation for dnn inference accelerators,

    F. Mu ˜noz-Mart´ınez, J. L. Abell ´an, M. E. Acacio, and T. Krishna, “Stonne: Enabling cycle-level microarchitectural simulation for dnn inference accelerators,” in 2021 IEEE International Symposium on Workload Characterization (IISWC), pp. 201–213, IEEE, 2021

    2021

  16. [24]

    Scale-sim: Systolic cnn accelerator simulator,

    A. Samajdar, Y . Zhu, P. Whatmough, M. Mattina, and T. Kr- ishna, “Scale-sim: Systolic cnn accelerator simulator,” arXiv preprint arXiv:1811.02883, 2018

    2018 arXiv

  17. [25]

    Maestro: A data-centric approach to understand reuse, performance, and hardware cost of dnn mappings,

    H. Kwon, P. Chatarasi, V . Sarkar, T. Krishna, M. Pellauer, and A. Parashar, “Maestro: A data-centric approach to understand reuse, performance, and hardware cost of dnn mappings,” IEEE micro, vol. 40, no. 3, pp. 20–29, 2020

    2020

  18. [26]

    usystolic: Byte-crawling unary systolic array,

    D. Wu and J. San Miguel, “usystolic: Byte-crawling unary systolic array,” in 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA), pp. 12–24, IEEE, 2022

    2022

  19. [27]

    Eyeriss: An energy- efficient reconfigurable accelerator for deep convolutional neural net- works,

    Y .-H. Chen, T. Krishna, J. S. Emer, and V . Sze, “Eyeriss: An energy- efficient reconfigurable accelerator for deep convolutional neural net- works,” IEEE journal of solid-state circuits, vol. 52, no. 1, pp. 127–138, 2016

    2016

  20. [28]

    Understanding reuse, performance, and hardware cost of dnn dataflow: A data-centric approach,

    H. Kwon, P. Chatarasi, M. Pellauer, A. Parashar, V . Sarkar, and T. Kr- ishna, “Understanding reuse, performance, and hardware cost of dnn dataflow: A data-centric approach,” in Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 754–768, 2019

    2019

  21. [29]

    Cacti 6.0: A tool to model large caches,

    N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “Cacti 6.0: A tool to model large caches,” HP laboratories, vol. 27, p. 28, 2009

    2009

  22. [30]

    Sigma: A sparse and irregular gemm ac- celerator with flexible interconnects for dnn training,

    E. Qin, A. Samajdar, H. Kwon, V . Nadella, S. Srinivasan, D. Das, B. Kaul, and T. Krishna, “Sigma: A sparse and irregular gemm ac- celerator with flexible interconnects for dnn training,” in 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp...

    2020

  23. [31]

    Accelergy: An architecture- level energy estimation methodology for accelerator designs,

    Y . N. Wu, J. S. Emer, and V . Sze, “Accelergy: An architecture- level energy estimation methodology for accelerator designs,” in 2019 IEEE/ACM International Conference on Computer-Aided Design (IC- CAD), pp. 1–8, IEEE, 2019

    2019

  24. [32]

    Cacti 7: New tools for interconnect exploration in innovative off-chip memories,

    R. Balasubramonian, A. B. Kahng, N. Muralimanohar, A. Shafiee, and V . Srinivas, “Cacti 7: New tools for interconnect exploration in innovative off-chip memories,” ACM Transactions on Architecture and Code Optimization (TACO), vol. 14, no. 2, pp. 1–25, 2017

    2017

  25. [33]

    Ramulator: A fast and extensible dram simulator,

    Y . Kim, W. Yang, and O. Mutlu, “Ramulator: A fast and extensible dram simulator,” IEEE Computer architecture letters , vol. 15, no. 1, pp. 45– 49, 2015

    2015

  26. [34]

    Feather: A reconfigurable accelerator with data reordering support for low-cost on-chip dataflow switching,

    J. Tong, A. Itagi, P. Chatarasi, and T. Krishna, “Feather: A reconfigurable accelerator with data reordering support for low-cost on-chip dataflow switching,” 2024

    2024

  27. [35]

    Ark: Fully homomorphic encryption accelerator with runtime data generation and inter-operation key reuse,

    J. Kim, G. Lee, S. Kim, G. Sohn, M. Rhu, J. Kim, and J. H. Ahn, “Ark: Fully homomorphic encryption accelerator with runtime data generation and inter-operation key reuse,” in 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 1237–1254, IEEE, 2022

    2022

  28. [36]

    Camj: Enabling system- level energy modeling and architectural exploration for in-sensor visual computing,

    T. Ma, Y . Feng, X. Zhang, and Y . Zhu, “Camj: Enabling system- level energy modeling and architectural exploration for in-sensor visual computing,” in Proceedings of the 50th Annual International Symposium on Computer Architecture, pp. 1–14, 2023

    2023

  29. [37]

    Cambricon-u: A systolic random increment memory architecture for unary computing,

    H. Guo, Y . Zhao, Z. Li, Y . Hao, C. Liu, X. Song, X. Li, Z. Du, R. Zhang, Q. Guo, et al. , “Cambricon-u: A systolic random increment memory architecture for unary computing,” in Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 424–437, 2023

    2023

  30. [38]

    Self adaptive recon- figurable arrays (sara) learning flexible gemm accelerator configuration and mapping-space using ml,

    A. Samajdar, E. Qin, M. Pellauer, and T. Krishna, “Self adaptive recon- figurable arrays (sara) learning flexible gemm accelerator configuration and mapping-space using ml,” in Proceedings of the 59th ACM/IEEE Design Automation Conference , pp. 583–588, 2022

    2022

  31. [39]

    Deja vu: Contextual sparsity for efficient llms at inference time,

    Z. Liu, J. Wang, T. Dao, T. Zhou, B. Yuan, Z. Song, A. Shrivastava, C. Zhang, Y . Tian, C. Re, et al. , “Deja vu: Contextual sparsity for efficient llms at inference time,” in International Conference on Machine Learning, pp. 22137–22176, PMLR, 2023

    2023

  32. [40]

    The state of sparsity in deep neural networks,

    T. Gale, E. Elsen, and S. Hooker, “The state of sparsity in deep neural networks,” arXiv preprint arXiv:1902.09574 , 2019

    1902 arXiv

  33. [41]

    Sparse convolutional neural networks,

    B. Liu, M. Wang, H. Foroosh, M. Tappen, and M. Pensky, “Sparse convolutional neural networks,” in Proceedings of the IEEE conference on computer vision and pattern recognition , pp. 806–814, 2015. 12

    2015

  34. [42]

    Megablocks: Effi- cient sparse training with mixture-of-experts,

    T. Gale, D. Narayanan, C. Young, and M. Zaharia, “Megablocks: Effi- cient sparse training with mixture-of-experts,” Proceedings of Machine Learning and Systems , vol. 5, pp. 288–304, 2023

    2023

  35. [43]

    An efficient sparse inference software accelerator for transformer-based language models on cpus,

    H. Shen, H. Meng, B. Dong, Z. Wang, O. Zafrir, Y . Ding, Y . Luo, H. Chang, Q. Gao, Z. Wang, et al. , “An efficient sparse inference software accelerator for transformer-based language models on cpus,” arXiv preprint arXiv:2306.16601 , 2023

    2023 arXiv

  36. [44]

    Towards efficient sparse matrix vector multiplication on real processing-in-memory architectures,

    C. Giannoula, I. Fernandez, J. G ´omez-Luna, N. Koziris, G. Goumas, and O. Mutlu, “Towards efficient sparse matrix vector multiplication on real processing-in-memory architectures,” ACM SIGMETRICS Performance Evaluation Review, vol. 50, no. 1, pp. 33–34, 2022

    2022

  37. [45]

    NVIDIA Ampere Architecture

    “NVIDIA Ampere Architecture.” https://www.nvidia.com/en-in/data- center/ampere-architecture/, 2020

    2020

  38. [46]

    Vegeta: Vertically-integrated extensions for sparse/dense gemm tile acceleration on cpus,

    G. Jeong, S. Damani, A. R. Bambhaniya, E. Qin, C. J. Hughes, S. Subramoney, H. Kim, and T. Krishna, “Vegeta: Vertically-integrated extensions for sparse/dense gemm tile acceleration on cpus,” in 2023 IEEE International Symposium on High-Performance Computer Archi- tecture (HPC...

    2023

  39. [47]

    Smash: Co- designing software compression and hardware-accelerated indexing for efficient sparse matrix operations,

    K. Kanellopoulos, N. Vijaykumar, C. Giannoula, R. Azizi, S. Koppula, N. M. Ghiasi, T. Shahroodi, J. G. Luna, and O. Mutlu, “Smash: Co- designing software compression and hardware-accelerated indexing for efficient sparse matrix operations,” in Proceedings of the 52nd annual IE...

    2019

  40. [48]

    Cambricon-s: Addressing irregularity in sparse neural networks through a cooperative software/hardware approach,

    X. Zhou, Z. Du, Q. Guo, S. Liu, C. Liu, C. Wang, X. Zhou, L. Li, T. Chen, and Y . Chen, “Cambricon-s: Addressing irregularity in sparse neural networks through a cooperative software/hardware approach,” in 2018 51st Annual IEEE/ACM International Symposium on Microarchi- tectur...

    2018

  41. [49]

    Google, “TPUv5e.” https://cloud.google.com/tpu/docs/v5e

  42. [50]

    Hbm (high bandwidth memory) dram technology and architecture,

    H. Jun, J. Cho, K. Lee, H.-Y . Son, K. Kim, H. Jin, and K. Kim, “Hbm (high bandwidth memory) dram technology and architecture,” in 2017 IEEE International Memory Workshop (IMW) , pp. 1–4, IEEE, 2017

    2017

  43. [51]

    The rowhammer problem and other issues we may face as memory becomes denser,

    O. Mutlu, “The rowhammer problem and other issues we may face as memory becomes denser,” in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 , pp. 1116–1121, IEEE, 2017

    2017

  44. [52]

    Rowhammer: A retrospective,

    O. Mutlu and J. S. Kim, “Rowhammer: A retrospective,” IEEE Trans- actions on Computer-Aided Design of Integrated Circuits and Systems , vol. 39, no. 8, pp. 1555–1571, 2019

    2019

  45. [53]

    Systolic arrays (for vlsi),

    H. T. Kung and C. E. Leiserson, “Systolic arrays (for vlsi),” in Sparse Matrix Proceedings 1978 , vol. 1, pp. 256–282, Society for industrial and applied mathematics Philadelphia, PA, USA, 1979

    1978

  46. [54]

    Kung, Why systolic architecture? Design Research Center, Carnegie-Mellon University, 1982

    H.-T. Kung, Why systolic architecture? Design Research Center, Carnegie-Mellon University, 1982

    1982

  47. [55]

    Introduction to vlsi systems,

    C. Mead and L. Conway, “Introduction to vlsi systems,” 1980

    1980

  48. [56]

    Design and implementation of vlsi systolic array multiplier for dsp applications,

    B. K. Saptalakar, D. Kale, M. Rachannavar, and M. Pavankumar, “Design and implementation of vlsi systolic array multiplier for dsp applications,” International Journal of Scientific Engineering and Tech- nology, vol. 2, no. 3, pp. 156–159, 2013

    2013

  49. [57]

    A systolic array architecture for the discrete sine transform,

    D.-F. Chiper, M. Swamy, M. O. Ahmad, and T. Stouraitis, “A systolic array architecture for the discrete sine transform,” IEEE transactions on signal processing, vol. 50, no. 9, pp. 2347–2354, 2002

    2002

  50. [58]

    Quinton, The systematic design of systolic arrays

    P. Quinton, The systematic design of systolic arrays. PhD thesis, INRIA, 1983

    1983

  51. [59]

    General-purpose systolic arrays,

    K. T. Johnson, A. R. Hurson, and B. Shirazi, “General-purpose systolic arrays,” Computer, vol. 26, no. 11, pp. 20–31, 1993

    1993

  52. [60]

    AI and compute

    OpenAI, “AI and compute.” https://openai.com/index/ai-and-compute/

  53. [61]

    The llama 3 herd of models,

    A. Dubey, A. Jauhri, A. Pandey, A. Kadian, A. Al-Dahle, A. Letman, A. Mathur, A. Schelten, A. Yang, A. Fan, et al., “The llama 3 herd of models,” arXiv preprint arXiv:2407.21783 , 2024

    2024 arXiv

  54. [62]

    Gemini: a family of highly capable multimodal models,

    G. Team, R. Anil, S. Borgeaud, J.-B. Alayrac, J. Yu, R. Soricut, J. Schalkwyk, A. M. Dai, A. Hauth, K. Millican,et al., “Gemini: a family of highly capable multimodal models,”arXiv preprint arXiv:2312.11805, 2023

    2023 arXiv

  55. [63]

    Gpt-4 technical report,

    J. Achiam, S. Adler, S. Agarwal, L. Ahmad, I. Akkaya, F. L. Aleman, D. Almeida, J. Altenschmidt, S. Altman, S. Anadkat, et al. , “Gpt-4 technical report,” arXiv preprint arXiv:2303.08774 , 2023

    2023 arXiv

  56. [64]

    Genad: Generative end-to-end autonomous driving,

    W. Zheng, R. Song, X. Guo, C. Zhang, and L. Chen, “Genad: Generative end-to-end autonomous driving,” in European Conference on Computer Vision, pp. 87–104, Springer, 2025

    2025

  57. [65]

    Planning-oriented autonomous driving,

    Y . Hu, J. Yang, L. Chen, K. Li, C. Sima, X. Zhu, S. Chai, S. Du, T. Lin, W. Wang, et al. , “Planning-oriented autonomous driving,” in Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, pp. 17853–17862, 2023

    2023

  58. [66]

    Explainable artificial intelligence for autonomous driving: A comprehensive overview and field guide for future research directions,

    S. Atakishiyev, M. Salameh, H. Yao, and R. Goebel, “Explainable artificial intelligence for autonomous driving: A comprehensive overview and field guide for future research directions,” IEEE Access, 2024

    2024

  59. [67]

    Ambiguous medical image segmentation using diffusion models,

    A. Rahman, J. M. J. Valanarasu, I. Hacihaliloglu, and V . M. Patel, “Ambiguous medical image segmentation using diffusion models,” in Proceedings of the IEEE/CVF conference on computer vision and pattern recognition, pp. 11536–11546, 2023

    2023

  60. [68]

    Contrastive learning of medical visual representations from paired images and text,

    Y . Zhang, H. Jiang, Y . Miura, C. D. Manning, and C. P. Langlotz, “Contrastive learning of medical visual representations from paired images and text,” in Machine Learning for Healthcare Conference , pp. 2–25, PMLR, 2022

    2022

  61. [69]

    Human action monitoring for healthcare based on deep learning,

    Y . Gao, X. Xiang, N. Xiong, B. Huang, H. J. Lee, R. Alrifai, X. Jiang, and Z. Fang, “Human action monitoring for healthcare based on deep learning,” Ieee Access, vol. 6, pp. 52277–52285, 2018

    2018

  62. [70]

    DGX GH200 for Large Memory AI Supercomputer

    Nvidia, “DGX GH200 for Large Memory AI Supercomputer.” https: //www.nvidia.com/en-in/data-center/dgx-gh200/

  63. [71]

    Dojo: The microarchitecture of tesla’s exa-scale computer,

    E. Talpes, D. Williams, and D. D. Sarma, “Dojo: The microarchitecture of tesla’s exa-scale computer,” in 2022 IEEE Hot Chips 34 Symposium (HCS), pp. 1–28, IEEE Computer Society, 2022

    2022

  64. [72]

    Versa: Versatile systolic array architecture for sparse and dense matrix multiplications,

    J. Seo and J. Kong, “Versa: Versatile systolic array architecture for sparse and dense matrix multiplications,” Electronics, vol. 13, no. 8, p. 1500, 2024

    2024

  65. [73]

    Ramulator 2.0: A modern, modular, and extensible dram simulator,

    H. Luo, Y . C. Tu ˘grul, F. N. Bostancı, A. Olgun, A. G. Ya ˘glıkc ¸ı, and O. Mutlu, “Ramulator 2.0: A modern, modular, and extensible dram simulator,” IEEE Computer Architecture Letters, vol. 23, no. 1, pp. 112– 116, 2023

    2023

  66. [74]

    Dramsim3: A cycle-accurate, thermal-capable dram simulator,

    S. Li, Z. Yang, D. Reddy, A. Srivastava, and B. Jacob, “Dramsim3: A cycle-accurate, thermal-capable dram simulator,” IEEE Computer Architecture Letters, vol. 19, no. 2, pp. 106–109, 2020

    2020

  67. [75]

    Simba: Scaling deep-learning inference with multi-chip-module-based architecture,

    Y . S. Shao, J. Clemons, R. Venkatesan, B. Zimmer, M. Fojtik, N. Jiang, B. Keller, A. Klinefelter, N. Pinckney, P. Raina, et al., “Simba: Scaling deep-learning inference with multi-chip-module-based architecture,” in Proceedings of the 52nd Annual IEEE/ACM International Sympos...

    2019

  68. [76]

    Towards heterogeneous multi-core accelerators exploiting fine- grained scheduling of layer-fused deep neural networks,

    A. Symons, L. Mei, S. Colleman, P. Houshmand, S. Karl, and M. Ver- helst, “Towards heterogeneous multi-core accelerators exploiting fine- grained scheduling of layer-fused deep neural networks,” arXiv preprint arXiv:2212.10612, 2022

    2022

  69. [77]

    Accelerating deep learning on heterogenous architectures,

    A. Nandakumar, S. Shao, and B. Nikolic, “Accelerating deep learning on heterogenous architectures,” 2022

    2022

  70. [78]

    Targeting dnn inference via efficient utilization of heterogeneous precision dnn accelerators,

    O. Spantidi, G. Zervakis, S. Alsalamin, I. Roman-Ballesteros, J. Henkel, H. Amrouch, and I. Anagnostopoulos, “Targeting dnn inference via efficient utilization of heterogeneous precision dnn accelerators,” IEEE Transactions on Emerging Topics in Computing, vol. 11, no. 1, pp. ...

    2022

  71. [79]

    J. H. Lau, Chip on board: technology for multichip modules . Springer Science & Business Media, 1994

    1994

  72. [80]

    D. A. Doane and P. Franzon, Multichip module technologies and alternatives: the basics . Springer Science & Business Media, 2013

    2013

  73. [81]

    Mcm-gpu: Multi-chip-module gpus for continued performance scalability,

    A. Arunkumar, E. Bolotin, B. Cho, U. Milic, E. Ebrahimi, O. Villa, A. Jaleel, C.-J. Wu, and D. Nellans, “Mcm-gpu: Multi-chip-module gpus for continued performance scalability,” ACM SIGARCH Computer Architecture News, vol. 45, no. 2, pp. 320–332, 2017

    2017

  74. [82]

    Multi-chip stacked memory module development using chip to wafer (c2w) hybrid bonding for heterogeneous integration applications,

    V . N. Sekhar, M. D. Kumar, S. K. Tippabhotla, B. C. Rao, I. C. Daniel, S. C. Chong, and V . S. Rao, “Multi-chip stacked memory module development using chip to wafer (c2w) hybrid bonding for heterogeneous integration applications,” in 2024 IEEE 74th Electronic Components and ...

    2024

  75. [83]

    Micron DDR4 Verilog Model,

    Micron Technology, “Micron DDR4 Verilog Model,” 2018

    2018

  76. [84]

    Nvidia a100 tensor core gpu architecture

    “Nvidia a100 tensor core gpu architecture.” https://images.nvidia. com/aem-dam/en-zz/Solutions/data-center/nvidia-ampere-architecture- whitepaper.pdf

  77. [85]

    Sparseloop: An analytical approach to sparse tensor accelerator modeling,

    Y . N. Wu, P.-A. Tsai, A. Parashar, V . Sze, and J. S. Emer, “Sparseloop: An analytical approach to sparse tensor accelerator modeling,” in 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 1377–1395, IEEE, 2022

    2022

  78. [86]

    Muchisim: A simulation framework for design exploration of multi-chip manycore systems,

    M. Orenes-Vera, E. Tureci, M. Martonosi, and D. Wentzlaff, “Muchisim: A simulation framework for design exploration of multi-chip manycore systems,” in 2024 IEEE International Symposium on Performance Anal- ysis of Systems and Software (ISPASS) , pp. 48–60, IEEE, 2024. 13

    2024

Pith tools

Reviewed August 16, 2026 · model on record in the stance chip above.