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REVIEW 4 major objections 5 minor 101 references

What Is Next for LLMs? Next-Generation AI Computing Hardware Using Photonic Chips

T0 review · 4 major / 5 minor · reviewed 2026-08-15 · deepseek-v4-flash

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Pith's one-line read Photonic chips could outrun GPUs for LLMs — if memory catches up

desk verdict Broad, uneven survey of photonic LLM hardware; the honest challenges section is the best part, but the abstract and conclusion overclaim relative to what the paper actually demonstrates. read the letter →

arxiv 2505.05794 v1 pith:2RGAXY4A submitted 2025-05-09 cs.AR cs.AIcs.NE

Renjie Li , Wenjie Wei , Qi Xin , Xiaoli Liu , Sixuan Mao , Erik Ma , Zijian Chen , Malu Zhang
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Haizhou Li Zhaoyu Zhang
This is my paper · ORCID
classification cs.ARcs.AIcs.NE
keywords photoniccomputinglargelanguagemodelsintegratedcircuitsMach-Zehnderinterferometermicroringresonatorspikingneuralnetworksspintronics2Dmaterials
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Large language models are hitting an energy wall: training GPT-3 consumed an estimated 1,300 MWh, and future models could need gigawatt-scale power budgets. This review argues that photonic integrated circuits, which compute with light rather than electrical currents, are the leading candidate to break that wall. It claims photonic systems can outperform electronic processors by orders of magnitude in throughput and energy efficiency for the matrix operations that dominate transformer models, while stressing that the advantage disappears unless on-chip memory, weight storage, precision, and nonlinear activation problems are solved. The paper's roadmap combines interferometer-based optical matrix multipliers, wavelength-multiplexed microring weight banks, 2D-material modulators, and spintronic synapses as the components of a future photonic LLM accelerator.

What carries the argument

The load-bearing object is the Mach-Zehnder interferometer (MZI) mesh, a cascaded array of optical splitters and phase shifters that applies programmable $2\times 2$ unitary rotations and, in aggregate, acts as an optical matrix multiplier, alongside microring-resonator (MRR) weight banks that use wavelength-division multiplexing to run many multiply-accumulate operations in parallel. These devices perform the linear algebra at the heart of transformer self-attention and feed-forward layers. To supply the missing memory and nonlinearity, the paper brings in phase-change and spintronic synapses for non-volatile weight storage, 2D materials such as graphene and TMDCs for high-speed modulators and detectors, and delay-line reservoir schemes for temporal context. The mechanism that carries the argument is the mapping of transformer dynamic weight matrices onto reconfigurable optical meshes, with electronic or optical nonlinear elements completing each layer.

What would settle it

Build a complete photonic LLM inference accelerator, including ADC/DAC conversion, weight programming, and off-chip memory traffic, and compare its energy per token and latency against a current electronic GPU for a 7B-parameter model at a 100K-token context. If the photonic system does not beat the electronic baseline at system level, or if the measured on-chip weight storage and precision force frequent external memory access, the central claim fails. A simpler check is to measure the fraction of time the optical core is idle waiting for data; if that fraction is not near zero in a realistic workload, the memory bottleneck dominates.

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Extended reading notes

Core claim

The central claim is that transformer LLM workloads, dominated by dense matrix multiplications in attention and feed-forward layers, can be mapped onto photonic hardware that performs those multiplications at the speed of light, giving order-of-magnitude gains over electronic GPUs in throughput and energy efficiency. The paper documents component-level demonstrations of optical matrix-vector multiplication with Mach-Zehnder interferometer meshes, wavelength-multiplexed microring-resonator weight banks, all-optical spiking neurons, and 2D-material-integrated modulators, and argues these can be integrated into full accelerators. It is equally explicit that the claim is conditional: without large on-chip memory for long context windows and multi-terabyte datasets, photonic systems stream data in and out and reintroduce the von Neumann bottleneck; without native nonlinearities they depend on electronic conversions; and ADC/DAC circuitry can consume more than half of chip area and power. Projecting past these obstacles, the conclusion states that photonic integrated circuits will eventually replace electronic integrated circuits as the backbone of computing.

Load-bearing premise

The load-bearing premise is that the demonstrated photonic building blocks, including interferometer meshes, microring weight banks, and spintronic or phase-change synapses, can be assembled into a full LLM accelerator with reconfigurable weights, sufficient precision, and enough on-chip memory that data movement does not reintroduce the von Neumann bottleneck; the paper itself flags this as unresolved.

Editorial extensions

If this is right

  • Transformer matrix multiplications, including query-key-value projections and attention-weighted sums, can in principle be executed optically in parallel, shifting LLM compute from electronic multiply-accumulate units to light-speed interference.
  • Long-context inference will remain memory-bound until on-chip non-volatile storage reaches multi-terabyte capacity and bandwidth comparable to the optical core.
  • ADC/DAC conversion and electronic nonlinearities are likely to remain part of any near-term photonic LLM chip, making hybrid optical-electronic designs the practical stepping stone.
  • If the roadmap is realized, training and inference energy could drop by orders of magnitude, easing the gigawatt-scale power projections for next-generation models.
  • The paper projects that photonic integrated circuits will eventually replace electronic integrated circuits as the backbone of computing systems.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A near-term testable milestone follows implicitly: a photonic transformer accelerator must beat a GPU on system-level energy-delay product for a standard open model; the paper does not predict when or at what scale this will happen.
  • Because attention weights are input-dependent, the fastest path to practical photonic LLMs may be to keep dynamic weights in electronic memory and send only the large static weight matrices, such as feed-forward layers and value projections, to the optical core, an allocation the paper suggests but does not prescribe.
  • The memory bottleneck implies photonic hardware may first find a niche in inference with static, pre-trained weights rather than in training, where frequent weight updates and high precision are unavoidable; this is an editorial inference, not a paper claim.
  • If optical saturable absorbers or other native nonlinearities mature, an all-optical transformer block with delay-line memory could remove electronic conversion overhead; a direct experiment would measure per-layer latency and energy against a hybrid design.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. This review-style manuscript surveys photonic and neuromorphic hardware candidates for future LLM computing. It reviews microring resonators, Mach-Zehnder interferometer meshes, metasurfaces, 2D-material-integrated photonics, spintronic devices, transformer and spiking-neural-network principles, and current challenges. The abstract claims that photonic systems could potentially surpass electronic processors by orders of magnitude in throughput and energy efficiency but require breakthroughs in memory and storage; the conclusion asserts that photonic integrated circuits will eventually replace electronic integrated circuits as the backbone of computing.

Significance. A broad, readable synthesis of a large and fragmented literature is potentially useful to the AI-hardware community, and the paper deserves credit for explicitly naming the main system-level obstacles: memory streaming, ADC/DAC conversion overhead, and missing native optical nonlinearities. The survey also collects a wide range of component-level demonstrations in one place. However, the central quantitative claim is an extrapolation rather than a synthesis: the manuscript contains no end-to-end energy or latency model of a photonic LLM system, and several load-bearing references and benchmarks are untraceable or garbled. The paper is therefore valuable as a roadmap but does not currently provide evidence for its headline orders-of-magnitude claim.

major comments (4)
  1. [Abstract; §8; §7.1; §7.3] The abstract's 'orders of magnitude' claim and the conclusion's 'PICs will eventually replace ICs' are not supported by a system-level accounting. Section 7.1 states that without extensive on-chip SRAM or NVM, photonic systems must stream data in and out, reintroducing the von Neumann bottleneck, and Section 7.3 reports a photonic transformer accelerator in which ADC/DAC circuitry occupied over 50% of the chip and became a performance bottleneck. Component-level demonstrations cannot establish system-level gains unless these dominant cost terms are quantified, so the headline claim should be reworded as a research hypothesis or supported by an end-to-end energy/latency model.
  2. [§5.9] The DeepSeek description confuses the two architectural innovations: it says DeepSeek introduces 'Multi-Head Attention (MoE) for parameter sparsity and Multi-Layer Perceptron (MLA)', whereas the correct terms are Mixture-of-Experts (MoE) and Multi-head Latent Attention (MLA). This is a factual error in the LLM survey portion and should be corrected; it also makes the surrounding efficiency discussion unreliable.
  3. [§4; Table 2; Table 1] Many quantitative claims are not traceable. Section 4 cites author-year keys such as Grollier2020, Chen2021, Camsari2019, Locatelli2014, and Sengupta2017 that do not appear in the numbered reference list; Table 2 reports benchmark numbers (e.g., Photonic STDP latency 0.1 ps, energy 0.3 aJ) with no source or methodology; and Table 1 contains garbled entries, including 'MoS2 37.515.28' and 'Graphene 2.085.6910.692.78'. Without clean values and traceable sources, these quantitative claims cannot be verified.
  4. [§3.3; §6.1; References] The reference apparatus is incomplete. The text cites '[graphenea]' in Section 3.3 and '[Li2023NatPhoton]' and '[Zhang2024Optica]' in Section 6.1, none of which appear in the reference list, and Figures 13 and 14 carry '<empty citation>' placeholders. The survey cannot be properly assessed until every in-text citation resolves to a full bibliographic entry.
minor comments (5)
  1. [§5.1; §3.2; §3.5] There are numerous typographical errors: 'Transformer achitecture' in the Section 5.1 heading, 'aquired', 'shocasing', and 'softy' in Section 3.2, and 'continuining' in Section 3.5. These should be corrected throughout.
  2. [§6.1] The displayed equations (i)-(iii) lack a source and do not define all symbols; please provide citations or brief derivations for the leaky integrate-and-fire model, the STDP update rule, and the nonlinear Schrödinger equation as used here.
  3. [§8] The conclusion introduces terms such as PCSELs and topological insulators that are not discussed in the body of the paper; aligning the conclusion with the material actually reviewed would improve coherence.
  4. [Author contributions] The author contributions list names Y.G., H.H., and Y.Z. that do not appear in the author list, suggesting stale boilerplate; this should be corrected.
  5. [§5.9] In addition to the MoE/MLA error, the sentence 'By integrating Multi-Head Attention (MoE) for parameter sparsity and Multi-Layer Perceptron (MLA) with low precision, the architecture achieves high capacity at a reduced computational cost' is garbled and should be rewritten for clarity.

Circularity Check

0 steps flagged · score 2.0 of 10

No circular derivation: the central claim is a conditional survey-level extrapolation resting on external component literature, with only a non-load-bearing self-citation.

full rationale

By its own structure this is a survey, not a derivation: no target quantity is computed from an input, no parameter is fitted to a subset of data and then re-predicted, and no uniqueness theorem is invoked. The abstract's "orders of magnitude" sentence is explicitly conditional ("could potentially ... but require breakthroughs"), and its support is the component-level literature surveyed in Sections 2-4, including MZI meshes, MRR weight banks, 2D-material modulators, and spintronic synapses. The conclusion "PICs will eventually replace ICs" is presented as an expectation ("we expect"), not as a consequence of an equation. The one self-citation, reference [1] (the authors' own Advanced Materials survey), appears in the introduction to support the widely known existence of memory-processor bottlenecks; that premise is independently established, and removing [1] would not change any later claim. The paper even concedes in Sections 7.1, 7.3, and 7.4 that memory I/O reintroduces the von Neumann bottleneck, that ADC/DAC circuitry can occupy over 50% of a photonic transformer chip, and that native nonlinear functions are missing. These concessions weaken the extrapolation but do not make it circular. I therefore find no circular step; the score of 2 reflects only the presence of a non-load-bearing self-citation.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

No new free parameters or invented entities are introduced in this review; the axioms listed are domain assumptions required for the paper's central projection.

assumptions (4)
  • domain assumption Photonic components demonstrated in isolation can be scaled to LLM-scale integrated systems.
    The entire projection depends on scaling MZI meshes, MRR banks, and spintronic synapses to transformer-class models; Section 7 lists this as an open challenge.
  • domain assumption The performance numbers cited from prior component work (e.g., Table 2) are accurate and transferable to end-to-end LLM workloads.
    The 'orders of magnitude' claim rests on component-level benchmarks, several of which are presented without citations or measurement context.
  • domain assumption Nonlinear activation functions (softmax, GeLU) can be implemented optically or hybridized without dominating cost.
    Section 7.4 acknowledges photonic hardware lacks native nonlinear functions; the vision of all-optical LLM inference requires this.
  • domain assumption Memory and storage bottlenecks can be overcome by future integration (on-chip nonvolatile memory, co-packaged optics, novel weight storage).
    Sections 7.1 and 7.2 identify memory and I/O as the main bottlenecks; the central claim assumes these will be solved.

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Cite this review

Pith. "Pith review of What Is Next for LLMs? Next-Generation AI Computing Hardware Using Photonic Chips." pith.science (2026). https://pith.science/paper/2RGAXY4A

@misc{pith2026250505794,
  author       = {Pith},
  title        = {Pith review of: What Is Next for LLMs? Next-Generation AI Computing Hardware Using Photonic Chips},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/2RGAXY4A}},
  note         = {Machine review of arXiv:2505.05794}
}
read the original abstract

Large language models (LLMs) are rapidly pushing the limits of contemporary computing hardware. For example, training GPT-3 has been estimated to consume around 1300 MWh of electricity, and projections suggest future models may require city-scale (gigawatt) power budgets. These demands motivate exploration of computing paradigms beyond conventional von Neumann architectures. This review surveys emerging photonic hardware optimized for next-generation generative AI computing. We discuss integrated photonic neural network architectures (e.g., Mach-Zehnder interferometer meshes, lasers, wavelength-multiplexed microring resonators) that perform ultrafast matrix operations. We also examine promising alternative neuromorphic devices, including spiking neural network circuits and hybrid spintronic-photonic synapses, which combine memory and processing. The integration of two-dimensional materials (graphene, TMDCs) into silicon photonic platforms is reviewed for tunable modulators and on-chip synaptic elements. Transformer-based LLM architectures (self-attention and feed-forward layers) are analyzed in this context, identifying strategies and challenges for mapping dynamic matrix multiplications onto these novel hardware substrates. We then dissect the mechanisms of mainstream LLMs, such as ChatGPT, DeepSeek, and LLaMA, highlighting their architectural similarities and differences. We synthesize state-of-the-art components, algorithms, and integration methods, highlighting key advances and open issues in scaling such systems to mega-sized LLM models. We find that photonic computing systems could potentially surpass electronic processors by orders of magnitude in throughput and energy efficiency, but require breakthroughs in memory, especially for long-context windows and long token sequences, and in storage of ultra-large datasets.

Figures

Figures reproduced from arXiv: 2505.05794 by the authors.

Figure 1
Figure 1. Microring resonator: a Neuromorphic ONNs can be realized through microring resonator [PITH_FULL_IMAGE:figures/full_fig_p005_1.png] view at source ↗
Figure 2
Figure 2. Mach-Zehnder Interferometer: a Training methodology diagram for ONNs enabling real [PITH_FULL_IMAGE:figures/full_fig_p006_2.png] view at source ↗
Figure 3
Figure 3. 2D Metasurface: a Conceptual representation of the inference mechanism in diffractive [PITH_FULL_IMAGE:figures/full_fig_p007_3.png] view at source ↗
Figures from the paper (19 more)
Figure 4
Figure 4. Figure 4: 1D Metasurface: a Experimental validation of 1D DONNs for photonic machine learning. [PITH_FULL_IMAGE:figures/full_fig_p007_4.png]
Figure 5
Figure 5. Figure 5: 4f system: a A hybrid optoelectronic CNN using 4f optical setup. [19] b An entirely [PITH_FULL_IMAGE:figures/full_fig_p008_5.png]
Figure 6
Figure 6. Figure 6: Other types of laser: a Theoretical analysis of the all-optical SNN using VCSELs. [20] [PITH_FULL_IMAGE:figures/full_fig_p008_6.png]
Figure 7
Figure 7. Figure 7: Crystal structures of a) graphene, b) TMDC, c) black phosphorus, d) hexagonal boron [PITH_FULL_IMAGE:figures/full_fig_p009_7.png]
Figure 8
Figure 8. Figure 8: Diagram (left) and images aquired from optical microscope (right) shocasing the softy [PITH_FULL_IMAGE:figures/full_fig_p010_8.png]
Figure 9
Figure 9. Figure 9: Depiction of a schematic flow of the water immersion method used for constructing Van [PITH_FULL_IMAGE:figures/full_fig_p011_9.png]
Figure 10
Figure 10. Figure 10: Roadmap of waveguide-integrated photodetectors that are dependent on 2D materials. [PITH_FULL_IMAGE:figures/full_fig_p012_10.png]
Figure 11
Figure 11. Figure 11: Graphene-quantum dot photodetector implemented within CMOS circuits. [26] [PITH_FULL_IMAGE:figures/full_fig_p012_11.png]
Figure 12
Figure 12. Figure 12: Artistic depiction of the hierarchal structure based on Kerr frequency comb-driven silicon [PITH_FULL_IMAGE:figures/full_fig_p013_12.png]
Figure 13
Figure 13. Figure 13: Magnetic tunnel junctions for memory applications. a, A magnetic tunnel junction consists [PITH_FULL_IMAGE:figures/full_fig_p017_13.png]
Figure 14
Figure 14. Figure 14: | Spintronic-based memristors. a, Domain-wall memristor. The resistance of the magnetic [PITH_FULL_IMAGE:figures/full_fig_p017_14.png]
Figure 15
Figure 15. Figure 15: Transformer neural networks used in modern LLMs. (a) The scaled dot-product attention [PITH_FULL_IMAGE:figures/full_fig_p018_15.png]
Figure 16
Figure 16. Figure 16: Chain-of-thought prompting enables large language models to tackle complex arith [PITH_FULL_IMAGE:figures/full_fig_p019_16.png]
Figure 17
Figure 17. Figure 17: The core of RLHF is training a separate AI reward model based on human feedback, and [PITH_FULL_IMAGE:figures/full_fig_p021_17.png]
Figure 18
Figure 18. Figure 18: Tool use demonstration. Illustrated is for a question answering tool: Given an input text [PITH_FULL_IMAGE:figures/full_fig_p022_18.png]
Figure 19
Figure 19. Figure 19: SpiNNaker Neuron Binned Input Array. Inputs arrive into the bin corresponding to their [PITH_FULL_IMAGE:figures/full_fig_p025_19.png]
Figure 20
Figure 20. Figure 20: SpiNNaker Neuron Binned Input Array. Inputs arrive into the bin corresponding to their [PITH_FULL_IMAGE:figures/full_fig_p027_20.png]
Figure 21
Figure 21. Figure 21: Roadmap of SNN: the evolution of spiking neural network architecture in five stages: [PITH_FULL_IMAGE:figures/full_fig_p028_21.png]
Figure 22
Figure 22. Figure 22: Specific applications of SNNs: a. speech separation [96], b. high-speed object tracking [PITH_FULL_IMAGE:figures/full_fig_p029_22.png]

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Pith tools

Reviewed August 15, 2026 · model on record in the stance chip above.