Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links
Paper Citation Record · LEDGER
ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification
As of 8 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 3 inbound Pith citation observations for arXiv:2505.06821.
A citation records a reference. It does not transfer a finding from one paper to another.
Coverage vector
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-08T06:32:00.761636+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links, observed 2026-08-06T18:54:05.579429Z
A source-named dated measurement, never combined with another source.
Source: arxiv_reference, observed 2026-05-15T18:26:27.109049Z
Reference resolution
0 of 0 outbound references displayed
- verified exact0
- verified fuzzy0
- unresolved0
- parse uncertain0
- malformed identifier0
- metadata mismatch0
External citation measurements
No source-named external measurement is stored.
Outbound references
No outbound reference observations are available for this paper version.
Pith citing papers
Observation ae80009f-77bb-4a72-aac3-743dd156a81a · inbound
VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation cites this paper.
VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification
Reference 35
- Resolution
- unresolved
- no resolver link, observed 2026-08-06T18:54:05.579429Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 22748f23-c89c-4c16-93ae-7d383587576e · inbound
Distilled Large Language Model in Confidential Computing Environment for System-on-Chip Design cites this paper.
Distilled Large Language Model in Confidential Computing Environment for System-on-Chip Design ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification
Reference 20
- Resolution
- unresolved
- no resolver link, observed 2026-08-06T15:18:32.308082Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation cd912065-1e07-4cf3-8583-7714b46392c1 · inbound
ATLAS: AI-Assisted Threat-to-Assertion Learning for System-on-Chip Security Verification cites this paper.
ATLAS: AI-Assisted Threat-to-Assertion Learning for System-on-Chip Security Verification ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification
Reference 46
- Resolution
- verified exact
- arxiv_id, observed 2026-05-15T18:26:27.112176Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.