Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS

Frank K. G\"urkaynak; Luca Benini; Martin Povi\v{s}er; Paul Scheffler; Philippe Sauter; Thomas Benz

REVIEW 4 major objections 5 minor 3 references

Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS

T0 review · 4 major / 5 minor · reviewed 2026-08-15 · deepseek-v4-flash

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Pith's one-line read The largest end-to-end open-source SoC to date is a 34 mm², 64-bit Linux-capable RISC-V design that reaches 62 MHz at nominal voltage and 102 MHz at 1.64 V.

desk verdict Basilisk is the first Linux-capable application-class SoC built end-to-end with open-source EDA tools and measured on silicon; a real milestone, though the flow-improvement ratios rest on a baseline that needs pinning down. read the letter →

arxiv 2505.10060 v1 pith:U5SMI2BR submitted 2025-05-15 cs.AR

Philippe Sauter , Thomas Benz , Paul Scheffler , Martin Povišer , Frank K. Gürkaynak , Luca Benini This is my paper · ORCID

classification cs.AR

keywords open-sourcesiliconRISC-VSoCsystem-on-chipYosysOpenROADLinux-capable130nmBiCMOSenergyefficiency

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper reports the largest end-to-end open-source system-on-chip to date: Basilisk, a 34 mm² design with about 2.7 million gate equivalents, built around a 64-bit Linux-capable RISC-V core. The central claim is that a fully open design toolchain can now carry an application-class SoC through synthesis, place and route, and fabrication, not just small microcontrollers. Supporting that claim, the authors' improvements to the open synthesis flow yield 2.3× better timing and 1.6× smaller standard-cell area relative to the baseline open flow, and their placement-and-routing tuning reduces die size by 12%. Silicon measurements show 62 MHz at the nominal 1.2 V supply, up to 102 MHz at 1.64 V, and a peak energy efficiency of 18.9 MFLOP/s/W on FP64 matrix multiply at 0.88 V. If true, this means the open EDA stack has crossed a scale threshold, making Linux-class chips feasible without proprietary tools.

What carries the argument

The load-bearing mechanism is the open synthesis toolchain: Yosys-Slang, a SystemVerilog frontend for the open synthesizer Yosys built on the Slang compiler, which elaborates industry-grade SystemVerilog directly instead of converting it to simpler Verilog first. Around it, the authors build a high-effort synthesis script using the 'lazy man's synthesis' technique, add an optimization that maps shift operations to multiplexers, and then tune the open place-and-route flow, including small routing blockages near power-grid connections, to relieve congestion. This combination preserves design intent through elaboration, which yields smaller netlists, and then makes better use of the 130 nm cell library during logic optimization and physical design.

What would settle it

Re-run the Basilisk RTL through the unmodified baseline open synthesis flow on the same 130 nm process design kit and compare the resulting clock frequency and standard-cell area; if the gap is materially smaller than 2.3× and 1.6×, the claimed flow improvement is overstated.

Watch

Extended reading notes

Core claim

In the authors' own framing, the discovery is that the gap between open-source and commercial electronic design automation has narrowed enough that a large, Linux-capable SoC can be produced end to end with open tools and still meet competitive performance targets. Basilisk is the demonstration: a 34 mm², 2.7 MGE design in an open 130 nm BiCMOS process, containing an RV64GC-compliant 64-bit RISC-V core, a 124 MB/s DRAM controller with a four-way 64 KiB last-level cache, a USB 1.1 host, a VGA output, and a 62 Mb/s chip-to-chip link. The measured chip reaches 62 MHz at 1.2 V and 102 MHz at 1.64 V, with 18.9 MFLOP/s/W on FP64 GEMM at 0.88 V, and its longest path is 51 logic levels, comparable to a commercial implementation of the same platform at 46 logic levels. The authors attribute the result to a new SystemVerilog frontend for the Yosys synthesizer, a tuned synthesis script, and targeted place-and-route adjustments, which together reduce standard-cell area from 1.8 to 1.1 MGE and raise post-synthesis frequency from 33 to 77 MHz.

Load-bearing premise

The reported 2.3× timing and 1.6× area improvements are measured against a baseline synthesis flow that the paper only describes as 'derived from [9]', so if that baseline is not representative of the prior state of the art, the improvements would be overstated even though the chip itself is real.

Editorial extensions

If this is right

Linux-capable 64-bit SoCs are no longer out of reach for fully open design flows, so a research group or small company can produce an application-class chip without licensing commercial EDA.
The 2.3× timing and 1.6× area synthesis gains imply that open synthesis is no longer the dominant quality bottleneck for designs of this size; more of the remaining gap sits in physical design and process design kit maturity.
At 62 to 102 MHz in 130 nm, the chip is fast enough for real embedded Linux workloads, and the 18.9 MFLOP/s/W peak suggests low-voltage operation is the sensible energy point.
The complexity-normalized runtime comparison in the paper suggests the tuned flow transfers to other designs, shortening the path from RTL to GDSII for future open chips.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

If the same synthesis and place-and-route improvements transfer to other open process design kits, the cost and time to enter custom silicon could drop well below what the paper itself demonstrates; this is an extrapolation, since the paper evaluates one process.
The digital 62 Mb/s chip-to-chip link opens an implicit path to multi-die open-source systems, where several Basilisk-class chips are connected without proprietary high-speed transceivers; the paper does not develop this direction.
Because the frontend preserves SystemVerilog intent, designs that rely heavily on advanced SV constructs such as interfaces and structs may see larger synthesis gains than the simpler Verilog designs used in earlier open-flow demonstrations; this is a testable prediction.
The measured energy-efficiency peak is reported at 0.88 V and 10 MHz, well below nominal voltage; a reader could reasonably use this as evidence to under-clock rather than power-gate for floating-point workloads, though the paper does not make that recommendation.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

The thing to know about this paper: it delivers what it promises. Basilisk is the largest end-to-end open-source SoC to date, it runs Linux, and the silicon measurements are real. The authors took the Cheshire platform and CVA6 core, pushed it through Yosys-Slang and OpenROAD into IHP's open 130 nm PDK, fabricated it, and got a working 34 mm2, 2.7 MGE chip that does 62 MHz at 1.2 V and 102 MHz at 1.64 V. That is a concrete milestone for open-source hardware, not a simulation or a promise. The measured FP64 GEMM energy efficiency and the leakage data across ten chips are also credible and useful. Credit where it is due: the Yosys-Slang SystemVerilog frontend is a genuine tool contribution, and the OpenROAD tuning with routing blockages is specific enough that someone could reproduce it, assuming the scripts are in the repo.

The soft spots are real but not fatal. The biggest one is the baseline for the 2.3x timing and 1.6x area improvements. Section III says the baseline is "derived from [9]" and nothing more. No ORFS commit, no Yosys/Slang versions, no exact synthesis script. Since OpenROAD-flow-scripts changes fast and QoR is version-sensitive, that ratio is not reproducible as reported. The timing comparison is also only post-synthesis (33 to 77 MHz); we never learn whether the 2.3x survives place and route or shows up in measured silicon. The 12% die-area reduction from OpenROAD tuning has the same problem. If the baseline was reasonable, the improvements are probably real, but I cannot fully verify that from the paper text alone. A reproducibility appendix with exact versions, scripts, and the baseline's post-P&R numbers would close the gap.

The self-citations are not a problem: the paper builds directly on Cheshire, CVA6, and prior flow work, and it cites them properly. The circularity of engineering the flow on the same design you then measure is mild for a chip paper; the portability claim gets some support from MLEM reusing the flow. Measurement error bars or chip-to-chip frequency spread would be nice, but for a first silicon report the single shmoo curve is acceptable.

Who is this for? Anyone working on open EDA flows, open PDKs, or open-source SoC enablement. It deserves a serious referee: the central claim is important and backed by silicon, and the questions about the baseline are answerable with a revision. I would take it for peer review and push for the reproducibility details before acceptance.

Referee Report

4 major / 5 minor

Summary. The manuscript reports the design, implementation, and first silicon measurements of Basilisk, a 34 mm2 SoC in IHP's open 130 nm BiCMOS technology. Basilisk is based on the Cheshire platform and the CVA6 64-bit RISC-V core, with a HyperRAM controller, USB 1.1 host, VGA output, C2C link, and other peripherals. The authors claim this is the largest end-to-end open-source SoC to date, with 2.7 MGE total complexity and 1.14 MGE standard-cell complexity. They also report OSEDA flow improvements: a Yosys-Slang frontend and synthesis optimizations that reduce post-synthesis cell area from 1.8 to 1.1 MGE (1.6x) and increase post-synthesis clock frequency from 33 to 77 MHz (2.3x), plus OpenROAD tuning that reduces die area from 39 to 34 mm2 (-12%). Measured silicon performance reaches 62 MHz at 1.2 V, 102 MHz at 1.64 V, and 18.9 DP MFLOP/s/W on FP64 GEMM at 0.88 V.

Significance. If the results hold, this is a notable milestone for open-source EDA: it demonstrates that an application-class, Linux-capable SoC can be designed end-to-end with open tools and fabricated in an open PDK. The silicon measurements are concrete and credible, and the availability of the source repository and the comparison to prior open-flow chips are valuable. The flow improvements, if made reproducible, would be a useful contribution to the OSEDA community, but the current manuscript does not yet provide enough detail to validate the claimed 2.3x timing and 1.6x area improvements or the 12% die-area reduction.

major comments (4)

[Section III, 'Compared to a baseline synthesis flow derived from [9]'] The baseline synthesis flow is underspecified: the authors do not state the ORFS commit or tag, the Yosys/Yosys-Slang and ABC versions, the frontend path (native Yosys-Slang vs sv2v conversion), or the exact synthesis script used for the baseline. Because ORFS quality-of-results varies strongly with tool versions and script configuration, this prevents reproducibility of the claimed 2.3x timing and 1.6x area improvements and the associated runtime and memory reductions. Please provide the exact configuration of the baseline flow, for example by committing the baseline scripts and tool versions to the repository.
[Section III, timing comparison] The 2.3x timing improvement is reported only at the post-synthesis level (33 vs 77 MHz). It is not shown whether this improvement persists after placement and routing; the baseline's post-place-and-route Fmax or its measured silicon frequency should be reported, or the claim should be explicitly scoped to synthesis. Without this, the 'timing improvement' headline is not fully substantiated as an end-to-end flow result.
[Section III, OpenROAD tuning] The 12% die-area reduction (from 39 to 34 mm2) is attributed to tuned OpenROAD hyperparameters and 'strategically added small routing blockages,' but no details are given about which hyperparameters were changed, where the blockages were placed, or their sizes. To make this result reproducible and auditable, please document the configuration, ideally as a commit or configuration file in the OpenROAD-flow-scripts repository, and state the OpenROAD version used.
[Section IV, silicon results] The abstract and title describe Basilisk as 'Linux-capable,' but the silicon results section reports only a GEMM benchmark, frequency, and leakage measurements. Please clarify whether Linux was actually booted on the fabricated chip; if it was, report the boot and the peripherals tested, and if it was not, temper the claim or explicitly state that Linux capability is inherited from the CVA6 core and platform rather than demonstrated on this silicon.

minor comments (5)

[Abstract vs. Section III] The abstract states that synthesis runtime is reduced by 2.5x, while Section III states a reduction from 5.4 h to 1.7 h, which is 3.2x; please reconcile these numbers.
[Section III, Yosys-Slang description] The 'specialized optimization mapping aligned shift operations to multiplexers' is mentioned without a reference or a code link; please provide a pointer to the implementation or a more detailed description so that the optimization can be evaluated.
[Table I] The table footnotes for the 'd' and 'e' markers are difficult to parse, and the notation '130 d/110be' is unclear; please present the raw and normalized runtimes in separate columns or explain the normalization in the caption.
[End-to-end verification claim] The paper claims an 'end-to-end' open-source flow but does not report whether logic equivalence checking, DRC, or LVS were performed and passed; if these checks were run, please state the results, and if not, consider qualifying the 'end-to-end' claim.
[Section IV, portability claim] The statement that the flow improvements are portable, based on MLEM reusing Basilisk's tuned flow, is weak because MLEM is a simple microcontroller by the same authors; either temper the portability claim or provide evidence from a more distinct design.

Circularity Check

0 steps flagged · score 1.0 of 10

No significant circularity: Basilisk's headline results are measured silicon data, and the flow-improvement claims are before/after ablations against an external open-source baseline; only minor, non-load-bearing same-team self-citations appear.

full rationale

Basilisk is an experimental chip paper: the headline results (62 MHz at 1.2 V, 102 MHz at 1.64 V, 18.9 MFLOP/s/W, 34 mm2, 2.7 MGE) are direct measurements from fabricated silicon and physical design, not derived quantities. The synthesis and area improvement claims are before/after ablations of the authors' Yosys-Slang frontend and Yosys script changes against a baseline 'derived from [9]' (ORFS), an external open-source flow; the baseline is underspecified with respect to commit and tool versions, which is a reproducibility weakness, but it is not defined in terms of the target result and therefore not circular. The 12% die-area reduction from OpenROAD tuning is likewise an optimization comparison, not a prediction fitted to the outcome. The architecture reuses the authors' Cheshire platform and CVA6 core, and the portability remark cites MLEM [15], a same-team design that reuses the tuned flow; these are self-citations, but they are not load-bearing for the paper's central measured claims, and the Table I comparison against four external open designs supports the 'largest open-source SoC' claim. No equation is shown to equal its own input, and no fitted parameter is renamed as a prediction. The paper's derivation chain is therefore self-contained for its primary claims; the main concerns are baseline reproducibility and generalizability, which are correctness-risk issues rather than circularity.

Assumptions & free parameters 1 free parameters · 3 assumptions · 0 invented entities

This hardware implementation paper has no mathematical model being fitted. The only hand-chosen parameters are EDA flow tuning choices. The central assumptions are the correctness of the open PDK, the correctness of inherited IP blocks, and the representativeness of the baseline flow used for comparison.

free parameters (1)

OpenROAD placement and routing hyperparameters = Not stated
Hand-tuned for the Basilisk design to achieve a 12 percent die area reduction. These are empirical design choices, not derived from first principles, but they do not affect the chip's fundamental functionality.

assumptions (3)

domain assumption IHP 130 nm open PDK is accurate for design and measurement.
The design and silicon results rely on the PDK device models and design rules being correct. This is standard practice in chip design and is not validated within the paper.
domain assumption The baseline flow derived from OpenROAD-flow-scripts is representative of the state of the art.
The claimed improvements in timing and area are measured relative to this baseline. If the baseline is poorly configured, the improvements would be overstated.
domain assumption The Cheshire SoC platform and CVA6 core are functionally correct as inherited open-source IPs.
Section II states the design is based on these prior IPs; any undiscovered bug in them would weaken the demonstration, though the successful Linux boot provides some evidence.

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Cite this review

Pith. "Pith review of Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS." pith.science (2026). https://pith.science/paper/U5SMI2BR

@misc{pith2026250510060,
  author       = {Pith},
  title        = {Pith review of: Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/U5SMI2BR}},
  note         = {Machine review of arXiv:2505.10060}
}

read the original abstract

End-to-end open-source electronic design automation (OSEDA) enables a collaborative approach to chip design conducive to supply chain diversification and zero-trust step-by-step design verification. However, existing end-to-end OSEDA flows have mostly been demonstrated on small designs and have not yet enabled large, industry-grade chips such as Linux-capable systems-on-chip (SoCs). This work presents Basilisk, the largest end-to-end open-source SoC to date. Basilisk's 34 mm2, 2.7 MGE design features a 64-bit Linux-capable RISC-V core, a lightweight 124 MB/s DRAM controller, and extensive IO, including a USB 1.1 host, a video output, and a fully digital 62 Mb/s chip-to-chip (C2C) link. We implement Basilisk in IHP's open 130 nm BiCMOS technology, significantly improving on the state-of-the-art (SoA) OSEDA flow. Our enhancements of the Yosys-based synthesis flow improve design timing and area by 2.3x and 1.6x, respectively, while consuming significantly less system resources. By tuning OpenROAD place and route (P&R) to our design and technology, we decrease the die size by 12%. The fabricated Basilisk chip reaches 62 MHz at its nominal 1.2 V core voltage and up to 102 MHz at 1.64 V. It achieves a peak energy efficiency of 18.9 DP MFLOP/s/W at 0.88 V.

Figures

Figures reproduced from arXiv: 2505.10060 by the authors.

**Figure 5.** Basilisk evaluation board. we tuned OpenROAD’s flow and hyperparameters in the global placement and routing stages to our design by better balancing routing and timing goals. We strategically added small routing blockages, especially around power grid connections, to guide local routing behavior. This significantly reduced routing congestion in dense modules like the boot ROM, allowing us to reduce the die area fro… view at source ↗

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Reference graph

Works this paper leans on

3 extracted references · 2 canonical work pages

[1]

european-chips-act.com [2] congress.gov/bill/117th-congress/house- bill/4346 [3] spectrum.ieee.org/indian-semiconductor-manufacturing

work page
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Croc: An End-to-End Open-Source Extensible RISC-V MCU Platform to Democratize Silicon

A. Ottaviano et al., IEEE TCAS II , 2023 [5] F. Zaruba et al., IEEE VLSI, 2019 [6] C. X. Wolf et al., Austrochip, 2013 [7] T. Ajayi et al., Proc. GOMACTECH, 2019 [8] K. Herman et al., IEEE SSC Magazine , 2024 [9] github.com/The-OpenROAD-Project/OpenROAD-flow-scripts. 2024 [10] A. Ghazy et al., WOSET, 2020 [11] T. Henkes et al., DATE, 2024 [12] Z. R. Khan ...

work page Pith review arXiv 2023
[18]

Benz et al., IEEE Trans

T. Benz et al., IEEE Trans. Comput. , 2023 [19] github.com/zachjs/ sv2v. 2020 [20] P. Sauter et al., arXiv:2405.04257, 2024 [21] github. com/MikePopolski/slang. 2015 [22] W. Yang et al., IEEE/ACM ICCAD, 2012 [23] T. Benz et al., RISC-V Summit Europe , 2024

arXiv 2023

Pith tools

Reviewed August 15, 2026 · model on record in the stance chip above.

[1] [1]

european-chips-act.com [2] congress.gov/bill/117th-congress/house- bill/4346 [3] spectrum.ieee.org/indian-semiconductor-manufacturing

work page

[2] [4]

Croc: An End-to-End Open-Source Extensible RISC-V MCU Platform to Democratize Silicon

A. Ottaviano et al., IEEE TCAS II , 2023 [5] F. Zaruba et al., IEEE VLSI, 2019 [6] C. X. Wolf et al., Austrochip, 2013 [7] T. Ajayi et al., Proc. GOMACTECH, 2019 [8] K. Herman et al., IEEE SSC Magazine , 2024 [9] github.com/The-OpenROAD-Project/OpenROAD-flow-scripts. 2024 [10] A. Ghazy et al., WOSET, 2020 [11] T. Henkes et al., DATE, 2024 [12] Z. R. Khan ...

work page Pith review arXiv 2023

[3] [18]

Benz et al., IEEE Trans

T. Benz et al., IEEE Trans. Comput. , 2023 [19] github.com/zachjs/ sv2v. 2020 [20] P. Sauter et al., arXiv:2405.04257, 2024 [21] github. com/MikePopolski/slang. 2015 [22] W. Yang et al., IEEE/ACM ICCAD, 2012 [23] T. Benz et al., RISC-V Summit Europe , 2024

arXiv 2023