Decentralized Framework for Teleportation in Quantum Core Interconnects

John Jose; Maurizio Palesi; Rajeswari Suance P S; Ruchika Gupta

REVIEW 3 major objections 6 minor 21 references

Decentralized Framework for Teleportation in Quantum Core Interconnects

T0 review · 3 major / 6 minor · reviewed 2026-08-15 · deepseek-v4-flash

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Pith's one-line read Decentralized two-way teleportation cuts multi-core quantum latency by 40%.

desk verdict Two-way teleportation is a plausible new optimization, but the headline numbers outrun the evidence: no artifacts, inconsistent reporting, and a depth model that ignores qubit relocation. read the letter →

arxiv 2505.11195 v1 pith:RM332O4E submitted 2025-05-16 quant-ph

Rajeswari Suance P S , Ruchika Gupta , Maurizio Palesi , John Jose This is my paper · ORCID

classification quant-ph

keywords multicorequantumcomputingteleportationdecentralizedinterconnectnetwork-on-chiptwo-waycircuitdepthcommunicationlatencyentanglement

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to establish that inter-core qubit transfer in a multi-core quantum processor need not be a one-way journey from source to destination. It proposes a decentralized teleportation framework in which each adjacent pair of cores generates its own entanglement, and it introduces two variants: hop-by-hop teleportation, where only the source qubit moves, and two-way teleportation, where both the source and destination qubits move simultaneously toward a middle core, where the two-qubit gate is executed. The central claim is that two-way teleportation cuts end-to-end communication latency by about 40% on synthetic benchmarks, by 30% to 42% on real benchmark subroutines, and reduces circuit depth by 24% to 45% compared with hop-by-hop teleportation. A sympathetic reader would care because communication latency and circuit depth directly limit how long qubits must stay coherent, so reducing both could make modular, multi-core quantum architectures more practical.

What carries the argument

The mechanism is decentralized entanglement generation through Bell State Measurement nodes placed between adjacent quantum cores, combined with deterministic XY routing for movement. Each adjacent pair of cores entangles its communication qubits by emitting photons to the shared BSM node, and a successful measurement establishes an EPR pair that enables one teleportation hop. In two-way teleportation, the source and destination cores each route their relevant qubit along the XY path at the same time, so the qubits meet at an intermediate core, where the two-qubit gate is executed. This halves the number of sequential hops and, under the paper's cost model, reduces both end-to-end latency and compiled circuit depth.

What would settle it

Run the same two-way protocol in a simulator or experiment that tracks actual circuit depth and wall-clock latency while varying the number of hops, including classical message delays, entanglement-generation retry rates, and the cost of later retrieving a qubit that left its home core; if one hop does not cost one depth unit, the reported 24% depth reduction and the part of the latency gain based on it are not supported.

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Extended reading notes

Core claim

The paper's central claim is that two-way teleportation outperforms hop-by-hop teleportation in a decentralized multi-core quantum architecture by moving both operands of a distant two-qubit gate toward each other rather than moving one operand all the way to the other's core. In a simulated 4 by 4 mesh of quantum cores, with entanglement generated locally between adjacent cores through Bell State Measurement nodes, two-way teleportation reduces end-to-end communication delay by an average of 40% on random circuits of depth 5 and 10, and by 30% on the Cuccaro adder and MCMTV benchmarks and 42% on QFT and Quantum Volume. The paper also reports that compiled circuit depth decreases by 24% for the adder and MCMTV and by 45% for QFT and Quantum Volume. The explanation offered is that simultaneous movement halves the number of sequential teleportation hops before the gate can execute, and the gate fires at an intermediate core instead of the destination.

Load-bearing premise

The load-bearing premise is the cost model that each teleportation hop that moves a qubit one core closer adds exactly one unit to circuit depth, with no overhead counted for classical coordination, failed entanglement attempts, or the fact that the destination's qubit leaves its home core.

Editorial extensions

If this is right

If the reported gains hold, inter-core communication latency for distant operand pairs scales with roughly half the source-to-destination distance, so applications like QFT and Quantum Volume, which involve many far-apart two-qubit gates, benefit the most.
Reduced circuit depth means qubits spend fewer layers waiting for distant gates, lowering their exposure to decoherence and potentially enabling larger computations within coherence limits.
Decentralized entanglement generation removes the single EPR-pair generator as a bottleneck, so multiple teleportations in disjoint regions of the mesh can proceed in parallel.
Executing two-qubit gates at an intermediate meeting core rather than at the destination means qubit traffic is redistributed across the network and destination cores no longer serve as the sole convergence point.
Compilers for multi-core quantum architectures could be designed to choose a meeting point for each two-qubit gate based on current qubit locations, rather than always routing one operand to the other's core.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

If the one-depth-unit-per-hop cost model is replaced by a more realistic accounting that includes classical handshakes and entanglement-generation retries, the optimal meeting point may shift; the same two-way protocol could be tuned rather than discarded.
The underlying idea, moving both operands toward a rendezvous point, is not specific to 2D meshes; it could plausibly extend to higher-dimensional or irregular topologies and even to multi-operand gates, though the paper only evaluates pairwise gates on a 4 by 4 mesh.
A direct testable extension is to vary mesh size and entanglement success probability: the paper's fixed 4 by 4 ideal-BSM setting leaves open whether the 40% figure persists under practical noise and retry overhead.
The acknowledged congestion at middle cores under deterministic XY routing suggests that adaptive routing, which chooses meeting points based on current load, could make two-way teleportation even more attractive in larger networks.

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Signed reviews

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Short version: this is a genuinely new, plausible optimization for inter-core qubit transfer, and the two-way teleportation variant is worth knowing about. But the headline reductions are not backed by the evidence as written. I would not take the 30–40% latency or 24% depth figures at face value without code and a better cost model.

What is actually new: existing teleportation interconnects use a centralized EPR generator; the paper replaces it with per-link BSM nodes, and proposes moving both operands toward a middle core rather than moving the source all the way to the destination. The XY-routing protocol is simple, but the idea is not in the cited prior work. The paper also evaluates on small real circuits (QFT, Cuccaro adder, MCMT, Quantum Volume) in addition to synthetic traffic, which is the right instinct.

Soft spots, in rough order of severity. First, there is no code, no data, and no description of the simulator parameters or SeQUeNCe modifications. Nobody can reproduce the latency numbers. Second, the abstract and conclusion say 30% real-benchmark latency reduction and 24% depth reduction, while Section V.B reports 30% for two benchmarks and 42% for two others, with the same split for depth (24% vs 45%). The headline understates the reported range, which is misleading. Third, the depth model in Section V.C is load-bearing: one depth unit per hop, per request, as if each inter-core gate is isolated. But both protocols physically relocate logical qubits. After a two-way teleport, both operands sit in a middle core; a later gate involving one of those qubits and a qubit that stayed home requires extra movement. The paper never tracks qubit locations across the circuit. That omission systematically favors two-way teleportation and likely overstates the depth reduction. The stress-test note is right. The latency comparison may survive a more careful accounting, but the current 24% depth figure is not supported.

Minor concerns: congestion in middle cores is admitted but not modeled, and there are no error bars. The citation pattern looks fair; the self-citations to earlier multicore architecture work are relevant.

Who this is for: researchers working on multi-core quantum architectures and circuit mapping. The paper deserves a serious referee, not a desk rejection. Ask for open artifacts, corrected headline numbers, and a location-aware cost model before trusting the quantitative claims.

Referee Report

3 major / 6 minor

Summary. The paper proposes a decentralized teleportation framework for multi-core quantum computing, in which entanglement is generated locally at BSM nodes between neighboring cores rather than by a centralized EPR generator. Two protocols are compared: hop-by-hop teleportation, where the source qubit moves one hop at a time to the destination core using deterministic XY routing, and two-way teleportation, where both source and destination qubits move simultaneously toward an intermediate core where the two-qubit gate is executed. The authors simulate 4x4 mesh networks by modifying the SeQUeNCe simulator, using synthetic random circuits and four real benchmark circuits (QFT, Cuccaro adder, MCMTV, Quantum Volume). They report that two-way teleportation reduces end-to-end communication latency by 40% on synthetic benchmarks and 30% on real applications, and reduces circuit depth by 24%, compared to hop-by-hop teleportation. The paper also discusses a congestion limitation arising from deterministic XY routing and suggests adaptive routing as future work.

Significance. If the reported reductions hold, the two-way teleportation scheme would be a simple and interesting architectural improvement: moving both operands toward each other roughly halves the communication distance for inter-core two-qubit gates in small mesh networks, without requiring compiler-level optimization. The conceptual contribution is clear and the paper is honest about at least one limitation (middle-core congestion). The use of an established simulator (SeQUeNCe) and a direct comparison against a well-defined baseline are strengths. However, the quantitative claims are currently not adequately supported: the depth model in Section V.C is asserted rather than validated, the simulation methodology is under-specified, and the headline numbers in the abstract conflict with per-benchmark numbers in Section V.B. The central idea is plausible, but the evidence as presented is not yet sufficient to verify the claimed magnitudes.

major comments (3)

[Section V.C, Fig. 8] The cost model 'each time a qubit is moved closer to the destination core, the circuit depth increases by one' is a load-bearing assumption, but it is neither derived nor validated. Under the paper's own setup of a direct 1:1 mapping of logical to physical qubits without compiler optimization (Section V.A), teleportation physically relocates logical qubits. In two-way teleportation the destination operand leaves its home core, so if that qubit is later needed for another two-qubit gate with a qubit that has remained at (or returned to) the original home core, additional teleportation hops are required. The paper appears to evaluate each inter-core communication request with source and destination cores fixed to their original locations and never maintains a location map across the circuit. Ignoring these residual relocation costs can systematically favor two-way teleportation and undermines both the 24% depth reduction and, to a lesser extent, the latency reduction. Please either track qubit locations throughout the circuit and re-evaluate the depth, or explicitly justify why later gates are unaffected by the relocation.
[Section V.B, Abstract, Conclusion] The headline numbers are inconsistent. The abstract and conclusion report a 30% reduction in end-to-end latency for real benchmark applications, but Section V.B states that Cuccaro's Adder and MCMTV show 30%, while QFT and Quantum Volume show 42%. Similarly, the abstract reports a 24% depth reduction, while Section V.B reports 24% for Cuccaro's Adder and MCMTV but 45% for QFT and Quantum Volume. The paper should either report a single aggregate number with a clear averaging procedure or consistently report per-benchmark ranges.
[Section V.A] The simulation methodology is not described in enough detail to reproduce or verify the results. The text says 'we modify SeQUeNCe' but does not specify the modifications, the parameters for entanglement generation (success probability, decoherence times, classical communication latency), or the number of simulation runs. No error bars are shown in Figures 6-8, and no code or data repository is provided. Given that the quantitative claims are the main contribution, the experimental setup must be documented at a level that allows independent verification.

minor comments (6)

[Abstract] There are grammatical errors, e.g., 'We proposes a decentralized framework' and 'the issue of transferring quantum information across the cores remains unresolved' should be 'remains'.
[Section IV.B, Algorithm 1] The variable names are inconsistent: the pseudocode uses 'tele src dir' and 'tele dest dir' while the text and algorithm description use 'tel src dir' and 'tel dest dir'. Please unify.
[Section IV.B, Fig. 5] The figure caption mentions blue arrows for hop-by-hop and green arrows for two-way, but the printed figure appears in grayscale; consider using distinct line styles or labels so that the two paths are distinguishable.
[Section V.A, Benchmarks] The acronym 'MCMTV' is used without expansion; define it (presumably multi-controlled multi-target gate or similar).
[Section V.C] The congestion limitation in middle cores is mentioned only qualitatively. Since this is a known drawback of two-way teleportation with XY routing, a quantitative evaluation (e.g., qubit density or hot-spot metrics) would strengthen the discussion, even if only as a limitation.
[References] The text says 'Barret-Kok generation principle' but the reference [17] is by Barrett and Kok; fix the spelling.

Circularity Check

0 steps flagged · score 1.0 of 10

No significant circularity: the latency and depth reductions are simulation outputs from fixed protocols on external benchmarks, not fitted predictions.

full rationale

The paper's central comparison is between two teleportation strategies (hop-by-hop and two-way) simulated in a modified SeQUeNCe simulator on synthetic random circuits and real benchmark subroutines (QFT, Cuccaro adder, Multi-Target Gate, Quantum Volume). No parameter is fitted to produce the reported reductions: the 40% synthetic and 30% real benchmark latency improvements, and the 24% depth reduction, are measured after fixing the protocols, routing algorithm, and the direct 1:1 logical-to-physical mapping. The depth result does rely on the stated cost model in Section V.C ('each time a qubit is moved closer to the destination core, the circuit depth increases by one'), but that is an explicit modeling assumption, not a hidden reuse of the target result; the reduction percentages are computed consequences of that assumption together with the benchmark traffic distributions, not a prediction whose input already contains the conclusion. The only self-citations are background references ([3], [5]) supporting general claims about multi-core scalability challenges and the existence of centralized interconnection approaches; they are not load-bearing for the derivation of the presented reductions. The skeptical concern about ignoring residual relocation costs for qubits that are teleported in earlier gates and then need to participate in later gates is a modeling/correctness caveat for future work, not a circularity of the kind that requires flagging. Under the review standard requiring an exhibited equation-level reduction or a fitted parameter renamed as a prediction, no circular step is present.

Assumptions & free parameters 4 free parameters · 4 assumptions · 0 invented entities

The central claim rests on several modeling choices: all-to-all intra-core connectivity, a one-depth-unit-per-hop model, and an underspecified simulation configuration. These are not artifacts of novelty but are load-bearing assumptions that a replication attempt would need to test.

free parameters (4)

Network size (4x4 mesh) = 4x4
The evaluation uses a 4x4 2D mesh; latency and depth reductions are measured on this topology and may not generalize to other sizes.
Connectivity radius Cr values = 1, 3, 6, random
The synthetic benchmarks use specific Cr values (fixed and random) that determine the distances between communicating cores; the reported reductions depend on these choices.
Circuit depth for synthetic benchmarks = 5 and 10
Random circuits are generated with depths 5 and 10, affecting the number of inter-core communication requests and the measured delay.
Simulator parameters (entanglement generation, classical latency, etc.) = not specified
The SeQUeNCe simulator is modified, but no parameters are given; these hidden settings affect the absolute latency numbers and the reported reductions.

assumptions (4)

domain assumption All-to-all connectivity among qubits within a core
Section IV states 'We assume an all-to-all connectivity among the qubits in the core.' This simplifies the intra-core cost and is unlikely to hold for large cores.
domain assumption Deterministic XY routing is used for inter-core paths
Section IV.A and Algorithm 1 rely on XY routing; the paper acknowledges this causes congestion, which is ignored in the reported results.
ad hoc to paper Each teleportation hop adds one unit to circuit depth
Section V.C states this depth model without justification; it is the basis for the claimed depth reductions.
domain assumption SeQUeNCe simulations faithfully model the network timing
The paper modifies SeQUeNCe but provides no validation of the timing or error models; the quantitative results rest on this.

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Cite this review

Pith. "Pith review of Decentralized Framework for Teleportation in Quantum Core Interconnects." pith.science (2026). https://pith.science/paper/RM332O4E

@misc{pith2026250511195,
  author       = {Pith},
  title        = {Pith review of: Decentralized Framework for Teleportation in Quantum Core Interconnects},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/RM332O4E}},
  note         = {Machine review of arXiv:2505.11195}
}

read the original abstract

Multi-core quantum computing architectures offer a promising and scalable solution to the challenges of integrating large number of qubits into existing monolithic chip design. However, the issue of transferring quantum information across the cores remains unresolved. Quantum Teleportation offers a potential approach for efficient qubit transfer, but existing methods primarily rely on centralized interconnection mechanisms for teleportation, which may limit scalability and parallel communication. We proposes a decentralized framework for teleportation in multi-core quantum computing systems, aiming to address these limitations. We introduce two variants of teleportation within the decentralized framework and evaluate their impact on reducing end-to-end communication delay and quantum circuit depth. Our findings demonstrate that the optimized teleportation strategy, termed two-way teleportation, results in a substantial 40% reduction in end-to-end communication latency for synthetic benchmarks and a 30% reduction for real benchmark applications, and 24% decrease in circuit depth compared to the baseline teleportation strategy. These results highlight the significant potential of decentralized teleportation to improve the performance of large-scale quantum systems, offering a scalable and efficient solution for future quantum architectures.

Figures

Figures reproduced from arXiv: 2505.11195 by the authors.

**Figure 1.** Quantum Teleportation Since qubits decohere over time, direct transmission of qubits is not suitable. Instead, quantum teleportation makes use of the fundamental property of qubits called entanglement for communication. The process of quantum teleportation is pictorially represented in [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗

**Figure 3.** Decentralized Interconnection Framework mines the optimal routing path for successful qubit transfer, and ensure overall synchronization of quantum operations [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗

**Figure 4.** Entanglement Generation Between Two Cores [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗

Figures from the paper (3 more)

**Figure 5.** Figure 5: Hop-by-Hop (blue arrows) and Two-Way (green ar [PITH_FULL_IMAGE:figures/full_fig_p004_5.png]

**Figure 6.** Figure 6: End-to-end Communication Delay versus the Number of Inter-core Communications for Synthetic Benchmarks [PITH_FULL_IMAGE:figures/full_fig_p005_6.png]

**Figure 8.** Figure 8: Quantum Circuit Depth Analysis C. Discussion The experimental results shows that two-way teleportation reduces the end-to-end communication delay compared to the hop-by-hop teleportation. This is due to the fact that, both qubits from the source and destination cores m…

Discussion (0). Continue with ORCID to comment.

Reference graph

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Pith tools

Reviewed August 15, 2026 · model on record in the stance chip above.

[1] [1]

Scaling Super- conducting Quantum Computers with Chiplet Architectures,

K. N. Smith, G. S. Ravi, J. M. Baker, and F. T. Chong, “Scaling Super- conducting Quantum Computers with Chiplet Architectures,” in 55th IEEE/ACM International Symposium on Microarchitecture (MICRO) , 2022, pp. 1092–1109

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J. Preskill, “Quantum computing in the NISQ era and beyond,” Quan- tum, vol. 2, p. 79, 2018

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[3] [3]

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E. Alarc ´on, S. Abadal, F. Sebastiano, M. Babaie, E. Charbon, P. H. Bol´ıvar, M. Palesi, E. Blokhina, D. Leipold, B. Staszewski et al. , “Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package,” in IEEE International Symposium on Circuits and Systems (ISCAS) , 2023, pp. 1–5

work page 2023

[4] [4]

Low-loss interconnects for modular superconduct- ing quantum processors,

J. Niu, Zhang et al., “Low-loss interconnects for modular superconduct- ing quantum processors,” Nature Electronics, vol. 6, pp. 235–241, 2023

work page 2023

[5] [5]

Assessing the Role of Communication in Scalable Multi-Core Quantum Architectures,

M. Palesi, E. Russo, D. Patti, G. Ascia, and V . Catania, “Assessing the Role of Communication in Scalable Multi-Core Quantum Architectures,” in IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 2024, pp. 482–489

work page 2024

[6] [6]

Correlated Charge Noise and Relaxation Errors in Superconducting Qubits,

C. D. Wilen, S. Abdullah, N. Kurinsky, C. Stanford, L. Cardani, G. d’Imperio, C. Tomei, L. Faoro, L. Ioffe, C. Liu et al. , “Correlated Charge Noise and Relaxation Errors in Superconducting Qubits,”Nature, vol. 594, pp. 369–373, 2021

work page 2021

[7] [7]

Teleporting an Unknown Quantum State via Dual Classi- cal and Einstein-Podolsky-Rosen Channels,

C. H. Bennett, G. Brassard, C. Cr ´epeau, R. Jozsa, A. Peres, and W. K. Wootters, “Teleporting an Unknown Quantum State via Dual Classi- cal and Einstein-Podolsky-Rosen Channels,” Physical Review Letters , vol. 70, p. 1895, 1993

work page 1993

[8] [8]

Modelling Short-range Quantum Teleportation for Scalable Multi-Core Quan- tum Computing Architectures,

S. Rodrigo, S. Abadal, C. G. Almud ´ever, and E. Alarc ´on, “Modelling Short-range Quantum Teleportation for Scalable Multi-Core Quan- tum Computing Architectures,” in ACM International Conference on Nanoscale Computing and Communication (NANOCOM) , 2021, pp. 1– 7

work page 2021