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REVIEW 4 major objections 3 minor 102 references

Understanding the Security Landscape of Embedded Non-Volatile Memories: A Comprehensive Survey

T0 review · 4 major / 3 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read This survey claims that the same physical features of embedded non-volatile memories that enable security primitives also expose those memories to a wide range of physical and logical attacks, and it maps that landscape across five memory…

desk verdict A useful but uneven eNVM security survey whose central attack table overstates at least one documented attack, and whose trend analysis is not reproducible. read the letter →

arxiv 2505.17253 v1 pith:D27JGSMO submitted 2025-05-22 cs.CR cs.ET

Zakia Tamanna Tisha , Ujjwal Guin This is my paper · ORCID
classification cs.CRcs.ET
keywords embeddednon-volatilememoryphysicallyunclonablefunctiontruerandomnumbergeneratorlogiclockingside-channelanalysisfaultinjectionrowhammerthermalattack
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Embedded non-volatile memories (eNVMs) — flash, PCM, MRAM, RRAM, and FeRAM — are moving from storage into caches, secure boot, and in-memory computing, and this survey tries to give designers and researchers one reference map of what that means for security. Its central contention is that the same physical properties that make these memories useful security building blocks are the properties that expose them to attack: data retention without power, high and asymmetric read/write currents, stochastic switching, and sensitivity to magnetic, electric, and thermal fields. The paper organizes the field into three layers: the five memory technologies and their architectural vulnerabilities, the security primitives built from them (physically unclonable functions, true random number generators, and logic locking), and seven attack classes (side-channel analysis, probing, fault injection, row hammer, information leakage, denial of service, and thermal attacks), summarized in two comparison tables. If this map is accurate, it gives a reader a fast way to see which attacks have actually been demonstrated on which memory, which primitives are mature, and where the literature is thin — for example, FeRAM appears in very few attack categories, which the authors explicitly say means underexplored rather than immune.

What carries the argument

The load-bearing mechanism is the dual use of the eNVM cell's physics: the exact properties that store data without power and supply entropy — data retention, high and asymmetric read/write currents, stochastic switching, and sensitivity to magnetic, electric, and thermal fields — are the channels through which the surveyed attacks operate. The organizational machinery is the two comparison tables: Table 1 maps each memory technology to published physically unclonable function (PUF, a chip-specific fingerprint from manufacturing variation), true random number generator (TRNG, a circuit that harvests physical randomness), and logic locking (a countermeasure that gates circuit behavior on a secret key) implementations, and Table 2 maps each technology to published side-channel, probing, fault-injection, row-hammer, information-leakage, denial-of-service, and thermal attacks. These tables turn a scattered literature into a grid on which both maturity and gaps are visible at a glance.

What would settle it

Take one row of Table 2 and check it against the cited original: for example, attempt the reported 15-trace differential power analysis key extraction from [71] on the commercial MRAM chip used in that study, or re-run the Section 5 publication counts with an explicit search query and compare the yearly totals. If the attack does not reproduce or the counts diverge materially, that part of the survey's claim fails.

Watch

Extended reading notes

Core claim

On the paper's own terms, its discovery is that eNVM security is a two-sided story with a common root. The non-volatility, asymmetric read/write currents, high write currents, and stochastic switching of these memories are what let PUFs and TRNGs generate entropy without storing keys on-chip; those same characteristics are what side-channel, probing, fault-injection, row-hammer, information-leakage, denial-of-service, and thermal attacks exploit. The paper supports that claim technology by technology: flash's thin tunnel oxide invites charge-injection faults, PCM's phase-change drift and analog resistance states enable both reconfigurable PUFs and thermal tampering, MRAM's magnetic tunnel junctions provide high-entropy switching but are flipped by magnetic fields, RRAM's conductive filaments and sneak-path currents give entropy and also create row-hammer and supply-noise channels, and FeRAM's data-dependent write currents enable power analysis. The paper concludes that the same features that enable eNVM applications also expose them to a wide range of physical and logical attacks, and it treats the absence of a published attack for a given memory as a gap in the literature, not as evidence of immunity.

Load-bearing premise

The load-bearing premise is that the 102 cited papers are accurately characterized and that the publication-database counts behind Figure 6 come from a representative search; if any cited attack or primitive is misdescribed, or the trend data are unrepresentative, the survey's conclusions weaken.

Editorial extensions

If this is right

  • A designer choosing an eNVM for a secure product can use the tables to see which primitives have published demonstrations on which memory, and which attack classes already have countermeasure literature.
  • Because the same properties create both entropy and leakage, eNVM-based PUFs and TRNGs should be assumed to need side-channel-hardened readout, not just good randomness metrics.
  • The seven attack classes give security researchers a checklist for evaluating a new eNVM technology: for a new memory, each empty cell in Table 2 is a candidate demonstration, not a safety claim.
  • The publication-trend analysis implies that security attention should follow the field's shift from flash toward RRAM and MRAM, which now receive the most research and also show the broadest documented attack surface.
  • As eNVMs move into caches and in-memory computing, the survey's denial-of-service, information-leakage, and thermal categories become directly relevant to AI accelerators and secure processors.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the dual-use framing is right, an eNVM cell engineered for high-entropy PUF or TRNG behavior may be more leakage-prone through power and timing channels; the paper documents both sides but does not state this as a design trade-off.
  • The survey's own caveat that absence of an attack does not imply immunity points to a concrete agenda: targeted fault-injection and thermal experiments on FeRAM, and probing studies on RRAM, are the rows with the largest room to move.
  • Extending the map to non-volatile caches suggests that power-cycling or cold-start attacks on cached plaintext become realistic once SRAM and DRAM are replaced by eNVMs; the paper notes the risk but does not develop countermeasures at the cache level.
  • The same leakage channels that enable side-channel attacks on RRAM matrix-vector multiplication also suggest covert channels inside processing-in-memory accelerators, since compute and memory share the same arrays and power grid.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 3 minor

Summary. This survey maps the security landscape of embedded non-volatile memories (eNVMs). It reviews five technologies — flash, PCM, MRAM, RRAM, and FeRAM — from an architectural viewpoint, discussing why each is vulnerable. It then surveys eNVM-based security primitives (PUFs, TRNGs, logic locking) and a broad attack taxonomy (side-channel, probing, fault injection, rowhammer, information leakage, denial of service, and thermal attacks), summarized in Tables 1 and 2. It closes with a Web of Science-based publication-trend analysis and a timeline of NVM milestones. The central claim is that the same properties that make eNVMs useful for security applications also expose them to a wide range of physical and logical attacks.

Significance. If the taxonomy is reliable, the paper provides a useful and reasonably broad reference for researchers entering the eNVM security area. It compiles a large body of work across multiple memory technologies and connects device-level vulnerabilities to system-level attacks, which is valuable for structuring future research. The paper's summary tables are a particularly helpful contribution, and the inclusion of less-covered topics such as rowhammer on RRAM and thermal attacks is timely. The main limitation is that the survey's value depends on each table cell being backed by a source that actually demonstrates the listed primitive or attack; the PCM thermal-attack entry is a concrete case where this condition fails.

major comments (4)
  1. [Section 4.7, Table 2] The Thermal—PCM cell cites reference [94], but [94] (Boybat et al., IEDM 2021) is a temperature-sensitivity study of analog in-memory computing that contains no adversary model, no attack procedure, and no security claim. Section 4.7 itself hedges by calling the finding 'a potential attack surface,' yet Table 2 converts that hedge into a documented thermal attack on PCM. Because Table 2 is one of the two central summary artifacts of the survey, this misclassification overstates PCM's demonstrated attack surface and should be corrected, either by removing the cell or by marking it as a potential, not demonstrated, vulnerability.
  2. [Section 4.7, Table 2] The text states that 'almost all types of eNVMs are susceptible' to thermal attacks, but the Thermal row of Table 2 lists only PCM, RRAM, and MRAM, with no entry for FeRAM or Flash. The table's disclaimer says absence indicates underexplored literature, not immunity, but the inconsistency between the blanket text claim and the row entries should be resolved to avoid confusing readers about which technologies have documented thermal attack studies.
  3. [Section 2.2] The background on PCM states that the phase change occurs 'at a relatively low temperature of around 600°C.' For GST alloys used in PCM, the amorphous-to-crystalline transition typically occurs around 150–200°C, while roughly 600°C is closer to the melting point. This physical imprecision in a foundational technology description is noticeable in a survey that aims to explain architectural vulnerabilities.
  4. [Section 5, Figure 6] The publication-trend analysis is presented without the Web of Science search query, database version, inclusion/exclusion criteria, or any normalization of raw counts. As a stated contribution of the paper, the trend claims are therefore not reproducible, and it is unclear whether the counts reflect all publications on each technology or a particular topical subset. The authors should add a methodology paragraph or temper the claims accordingly.
minor comments (3)
  1. [References] References [1] and [12] are the same work (Khan and Ghosh, Journal of Low Power Electronics and Applications, 2021) and should be merged to avoid duplicate numbering.
  2. [Figure 2] The figure caption and text are inconsistent: the caption lists (a) STT-MRAM, (b) RRAM, (c) FeRAM, but the body text refers to Figure 2(c) for RRAM, and the figure itself appears to contain a duplicated FeRAM subfigure. This should be cleaned up.
  3. [Section 2.2] There is a typo in 'GeSbT ealloys' that should read 'GeSbTe alloys.'

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the survey's claims rest on external literature, and the few self-citations are not load-bearing.

full rationale

This paper is a survey rather than a derivation chain. Its central claims—the five eNVM technologies, security primitives, and attack taxonomy in Tables 1 and 2—are explicitly presented as summaries of published studies, with each table cell tied to external references such as [15], [27], [47], [71], [77], [88], and [90]. The only self-citations are [2] (the authors' earlier ISVLSI paper, transparently described as the base being expanded), [68] (FORTIS, cited as background for logic locking), and [69] (Camskygate, cited as an example of skyrmion-based locking). None of these is used to justify a taxonomic cell or to replace an external experimental result; removing them would not change any entry in Tables 1 or 2 or any stated conclusion. The publication-trend analysis in Section 5 is descriptive Web of Science data, not a fitted parameter or a prediction, so it cannot be circular in the technical sense. The questionable Table 2 entry listing PCM as vulnerable to thermal attacks via [94] is a source-fidelity and correctness concern, because [94] is a temperature-sensitivity study of analog in-memory computing rather than an attack demonstration; but this is an over-credited source, not circularity, since the survey's output is not equivalent to its input by construction. No equation, fitted parameter, or load-bearing self-citation chain can be exhibited, so no circular step is identified.

Assumptions & free parameters 0 free parameters · 3 assumptions · 0 invented entities

The survey introduces no free parameters and no invented entities. Its conclusions rest on the accuracy of the cited papers and on the undocumented Web of Science counts in Figure 6. The main axioms are that the cited results are correctly described and that the bibliometric data are representative; neither is independently verified by the paper.

assumptions (3)
  • domain assumption Cited prior works accurately characterize eNVM vulnerabilities, security primitives, and attacks.
    The survey's content is entirely derived from references [1]-[102]; it does not independently verify any device or attack claims.
  • domain assumption The Web of Science counts in Figure 6 are a faithful measure of publication trends.
    No search query, inclusion criteria, or raw data are provided, so the trend line is not auditable.
  • domain assumption The background physics of the five memory technologies is correctly described.
    The paper presents material properties and operating principles as established facts, with the noted imprecision in the PCM transition temperature description.

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Cite this review

Pith. "Pith review of Understanding the Security Landscape of Embedded Non-Volatile Memories: A Comprehensive Survey." pith.science (2026). https://pith.science/paper/D27JGSMO

@misc{pith2026250517253,
  author       = {Pith},
  title        = {Pith review of: Understanding the Security Landscape of Embedded Non-Volatile Memories: A Comprehensive Survey},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/D27JGSMO}},
  note         = {Machine review of arXiv:2505.17253}
}
read the original abstract

The modern semiconductor industry requires memory solutions that can keep pace with the high-speed demands of high-performance computing. Embedded non-volatile memories (eNVMs) address these requirements by offering faster access to stored data at an improved computational throughput and efficiency. Furthermore, these technologies offer numerous appealing features, including limited area-energy-runtime budget and data retention capabilities. Among these, the data retention feature of eNVMs has garnered particular interest within the semiconductor community. Although this property allows eNVMs to retain data even in the absence of a continuous power supply, it also introduces some vulnerabilities, prompting security concerns. These concerns have sparked increased interest in examining the broader security implications associated with eNVM technologies. This paper examines the security aspects of eNVMs by discussing the reasons for vulnerabilities in specific memories from an architectural point of view. Additionally, this paper extensively reviews eNVM-based security primitives, such as physically unclonable functions and true random number generators, as well as techniques like logic obfuscation. The paper also explores a broad spectrum of security threats to eNVMs, including physical attacks such as side-channel attacks, fault injection, and probing, as well as logical threats like information leakage, denial-of-service, and thermal attacks. Finally, the paper presents a study of publication trends in the eNVM domain since the early 2000s, reflecting the rising momentum and research activity in this field.

Figures

Figures reproduced from arXiv: 2505.17253 by the authors.

Figure 1
Figure 1. Bitcell diagram of a (a) Flash Memory [5] and (b) PCM [6]. [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Bitcell diagram of a (a) STT-MRAM [12], (b) RRAM [12], (c) FeRAM [8]. [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 2
Figure 2. Schematic side view of an integrated reconfigurable optical (a) PCM-based PUF AM based authentication protocol. Here we have harnessed iiiiiihMRAM llbild Fig. 1. (a) Abst ll hi resistance, scalability, RRAM on/off ratio, iid RRAM dilibili [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figures from the paper (6 more)
Figure 3
Figure 3. Figure 3: PCM based rPUF. Limited control over the heating allows gyy p nergy barrier at room temperature (see Fig2(a))When beyond the scope of our prior conference g())pj FeRAM’s key features is its extremely l [PITH_FULL_IMAGE:figures/full_fig_p005_3.png]
Figure 8
Figure 8. Figure 8: Schematic circuit representation of a crossbar array. To select the active cell, +V/2 and −V/2 voltages are applied along the wordline and bitline at two edges of the array, whereas unselected lines are grounded. Voltage drops occur along the wirings (line resistance 2…
Figure 5
Figure 5. Figure 5: A logic locking block using MTJ [66] [PITH_FULL_IMAGE:figures/full_fig_p009_5.png]
Figure 3
Figure 3. Figure 3: FIGURE 3 [PITH_FULL_IMAGE:figures/full_fig_p009_3.png]
Figure 6
Figure 6. Figure 6: Annual publication trends for non-volatile memory from 2000 to 2024. [PITH_FULL_IMAGE:figures/full_fig_p013_6.png]
Figure 7
Figure 7. Figure 7: Key milestones in the evolution of NVM technologies. [PITH_FULL_IMAGE:figures/full_fig_p014_7.png]

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Reference graph

Works this paper leans on

102 extracted references · 80 canonical work pages

  1. [94]

    Temperature sensitivity of analog in-memory computing using phase-change memory

    Irem Boybat, Benedikt Kersting, S Ghazi Sarwat, X Timoneda, Robert L Bruce, Matthew BrightSky, Manuel Le Gallo, and Abu Sebastian. Temperature sensitivity of analog in-memory computing using phase-change memory. InIEEE International Electron Devices Meeting, pages 28–3, 2021

    work page 2021

  2. [12]

    Comprehensive Study of Security and Privacy of Emerging Non-V olatile Memories.Journal of low power electronics and applications, (4):36, 2021

    Mohammad Nasim Imtiaz Khan and Swaroop Ghosh. Comprehensive Study of Security and Privacy of Emerging Non-V olatile Memories.Journal of low power electronics and applications, (4):36, 2021

    2021

  3. [1]

    Comprehensive Study of Security and Privacy of Emerging Non-V olatile Memories.Journal of low power electronics and applications, 11(4):36, 2021

    Mohammad Nasim Imtiaz Khan and Swaroop Ghosh. Comprehensive Study of Security and Privacy of Emerging Non-V olatile Memories.Journal of low power electronics and applications, 11(4):36, 2021

    2021

  4. [2]

    Exploring Security Solutions and Vulnerabilities for Embedded Non-V olatile Memories

    Zakia Tamanna Tisha, Jeremy Muldavin, and Ujjwal Guin. Exploring Security Solutions and Vulnerabilities for Embedded Non-V olatile Memories. InIEEE Computer Society Annual Symposium on VLSI, pages 361–366, 2024

    2024

  5. [3]

    Power and Energy Perspectives of Nonvolatile Memory Technologies.Proceedings of the IEEE, (2):283–298, 2010

    Narbeh Derhacobian, Shane C Hollmer, Nad Gilbert, and Michael N Kozicki. Power and Energy Perspectives of Nonvolatile Memory Technologies.Proceedings of the IEEE, (2):283–298, 2010

    2010

  6. [4]

    Present and Future Non-V olatile Memories for Space.IEEE Transactions on nuclear science, 57(6):3016–3039, 2010

    Simone Gerardin and Alessandro Paccagnella. Present and Future Non-V olatile Memories for Space.IEEE Transactions on nuclear science, 57(6):3016–3039, 2010

    2010

  7. [5]

    Nonvolatile memories: Present and future challenges

    Elena Ioana Vatajelu, Hassen Aziza, and Cristian Zambelli. Nonvolatile memories: Present and future challenges. InInt. Design and Test Symposium, pages 61–66, 2014

    2014

  8. [6]

    Future Nonvolatile Memory Technologies: Challenges and Applications

    N Aswathy and NM Sivamangai. Future Nonvolatile Memory Technologies: Challenges and Applications. In International Conference on Advances in Computing, Communication, Embedded & Secure Systems, pages 308–312, 2021

    2021

Show all 102 references
  1. [7]

    Introduction to flash memory

    Roberto Bez, Emilio Camerlenghi, Alberto Modelli, and Angelo Visconti. Introduction to flash memory. Proceedings of the IEEE, (4):489–502, 2003

    2003

  2. [8]

    Overview of emerging nonvolatile memory technologies.Nanoscale research letters, pages 1–33, 2014

    Jagan Singh Meena, Simon Min Sze, Umesh Chand, and Tseung-Yuen Tseng. Overview of emerging nonvolatile memory technologies.Nanoscale research letters, pages 1–33, 2014

    2014

  3. [9]

    Overview of emerging semiconductor non-volatile memories.IEICE Electronics Express, (10):908–925, 2012

    Yoshihisa Fujisaki. Overview of emerging semiconductor non-volatile memories.IEICE Electronics Express, (10):908–925, 2012

    2012

  4. [10]

    Threat Models and Security of Phase-Change Memory

    Gang Wang. Threat Models and Security of Phase-Change Memory. In2019 IEEE International Conference on Consumer Electronics, pages 1–6, 2019. 15

    2019

  5. [11]

    Security and privacy threats to on-chip non-volatile memories and countermeasures

    Swaroop Ghosh, Mohammad Nasim Imtiaz Khan, Asmit De, and Jae-Won Jang. Security and privacy threats to on-chip non-volatile memories and countermeasures. In2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 1–6, 2016

    2016

  6. [13]

    Resistive Random Access Memory: A Review of Device Challenges.IETE Technical Review, (4):377–390, 2020

    Varshita Gupta, Shagun Kapur, Sneh Saurabh, and Anuj Grover. Resistive Random Access Memory: A Review of Device Challenges.IETE Technical Review, (4):377–390, 2020

    2020

  7. [14]

    Understanding vulnerabilities in ReRAM devices for trust in semiconductor designs

    Thomas Schultz and Rashmi Jha. Understanding vulnerabilities in ReRAM devices for trust in semiconductor designs. In2017 IEEE National Aerospace and Electronics Conference (NAECON), pages 338–342, 2017

    2017

  8. [15]

    Reconfigurable Physical Unclonable Functions - Enabling technology for tamper-resistant storage

    Klaus Kursawe, Ahmad-Reza Sadeghi, Dries Schellekens, Boris Skoric, and Pim Tuyls. Reconfigurable Physical Unclonable Functions - Enabling technology for tamper-resistant storage. In2009 IEEE International Workshop on Hardware-Oriented Security and Trust, pages 22–29, 2009

    2009

  9. [16]

    A novel geometry based MRAM PUF

    Jayita Das, Kevin Scott, Drew Burgett, Srinath Rajaram, and Sanjukta Bhanja. A novel geometry based MRAM PUF. InInt. Conference on Nanotechnology, pages 859–863, 2014

    2014

  10. [17]

    X-Point PUF: Exploiting Sneak Paths for a Strong Phys- ical Unclonable Function Design.IEEE Transactions on Circuits and Systems I: Regular Papers, 65(10):3459– 3468, 2018

    Rui Liu, Pai-Yu Chen, Xiaochen Peng, and Shimeng Yu. X-Point PUF: Exploiting Sneak Paths for a Strong Phys- ical Unclonable Function Design.IEEE Transactions on Circuits and Systems I: Regular Papers, 65(10):3459– 3468, 2018

    2018

  11. [18]

    Asari, Y

    K. Asari, Y . Mitsuyama, T. Onoye, I. Shirakawa, H. Hirano, T. Honda, T. Otsuki, T. Baba, and T. Meng. FeRAM circuit technology for system on a chip. InProceedings of the First NASA/DoD Workshop on Evolvable Hardware, pages 193–197, 1999

    1999

  12. [19]

    M. R. Mahmoodi, D. B. Strukov, and O. Kavehei. Experimental Demonstrations of Security Primitives With Nonvolatile Memories.Transactions on Electron Devices, (12):5050–5059, 2019

    2019

  13. [20]

    Extracting secret keys from integrated circuits.IEEE Transactions on Very Large Scale Integration Systems, (10):1200–1205, 2005

    Daihyun Lim, Jae W Lee, Blaise Gassend, G Edward Suh, Marten Van Dijk, and Srinivas Devadas. Extracting secret keys from integrated circuits.IEEE Transactions on Very Large Scale Integration Systems, (10):1200–1205, 2005

    2005

  14. [21]

    Memory-Based Combination PUFs for Device Authenti- cation in Embedded Systems.IEEE Transactions on Multi-Scale Computing Systems, (4):793–810, 2018

    Soubhagya Sutar, Arnab Raha, and Vijay Raghunathan. Memory-Based Combination PUFs for Device Authenti- cation in Embedded Systems.IEEE Transactions on Multi-Scale Computing Systems, (4):793–810, 2018

    2018

  15. [22]

    Physical Unclonable Functions for Device Authentication and Secret Key Generation

    G Edward Suh and Srinivas Devadas. Physical Unclonable Functions for Device Authentication and Secret Key Generation. InProceedings of the 44th annual design automation conference, pages 9–14, 2007

    2007

  16. [23]

    Utilizing the Variability of Resistive Random Access Memory to Implement Reconfigurable Physical Unclonable Functions.IEEE Electron Device Letters, (2):138–140, 2014

    An Chen. Utilizing the Variability of Resistive Random Access Memory to Implement Reconfigurable Physical Unclonable Functions.IEEE Electron Device Letters, (2):138–140, 2014

    2014

  17. [24]

    Memristor PUF—A Security Primitive: Theory and Experiment.IEEE Journal on Emerging and Selected Topics in Circuits and Systems, (2):222–229, 2015

    Anas Mazady, Md Tauhidur Rahman, Domenic Forte, and Mehdi Anwar. Memristor PUF—A Security Primitive: Theory and Experiment.IEEE Journal on Emerging and Selected Topics in Circuits and Systems, (2):222–229, 2015

    2015

  18. [25]

    STT MRAM-based PUFs

    Elena Ioana Vatajelu, Giorgio Di Natale, Marco Indaco, and Paolo Prinetto. STT MRAM-based PUFs. InDesign, Automation & Test in Eu. Conference & Exhibition, pages 872–875, 2015

    2015

  19. [26]

    MRAM PUF: A Novel Geometry Based Magnetic PUF With Integrated CMOS.IEEE Transactions on Nanotechnology, (3):436–443, 2015

    Jayita Das, Kevin Scott, Srinath Rajaram, Drew Burgett, and Sanjukta Bhanja. MRAM PUF: A Novel Geometry Based Magnetic PUF With Integrated CMOS.IEEE Transactions on Nanotechnology, (3):436–443, 2015

    2015

  20. [27]

    PCKGen: A Phase Change Memory based cryptographic key generator

    Le Zhang, Zhi Hui Kong, and Chip-Hong Chang. PCKGen: A Phase Change Memory based cryptographic key generator. InInternational Symposium on Circuits and Systems, pages 1444–1447, 2013

    2013

  21. [28]

    Phase Change Memory for Physical Unclonable Functions.Applications of Emerging Memory Technology: Beyond Storage, pages 59–91, 2020

    Nafisa Noor and Helena Silva. Phase Change Memory for Physical Unclonable Functions.Applications of Emerging Memory Technology: Beyond Storage, pages 59–91, 2020

    2020

  22. [29]

    Edward Suh, and Edwin C

    Yinglei Wang, Wing-kei Yu, Shuo Wu, Greg Malysa, G. Edward Suh, and Edwin C. Kan. Flash Memory for Ubiquitous Hardware Security Functions: True Random Number Generation and Device Fingerprints. In Symposium on Security & Privacy, pages 33–47, 2012

    2012

  23. [30]

    Extracting Device Fingerprints from Flash Memory by Exploiting Physical Variations

    Pravin Prabhu, Ameen Akel, Laura M Grupp, Wing-Kei S Yu, G Edward Suh, Edwin Kan, and Steven Swanson. Extracting Device Fingerprints from Flash Memory by Exploiting Physical Variations. InTrust and Trustworthy Computing: International Conference, pages 188–201. Springer, 2011

    2011

  24. [31]

    A PUF scheme using competing oxide rupture with bit error rate approaching zero

    Meng-Yi Wu, Tsao-Hsin Yang, Lun-Chun Chen, Chi-Chang Lin, Hao-Chun Hu, Fang-Ying Su, Chih-Min Wang, James Po-Hao Huang, Hsin-Ming Chen, Chris Chun-Hung Lu, et al. A PUF scheme using competing oxide rupture with bit error rate approaching zero. In2018 IEEE International Solid-S...

    2018

  25. [32]

    ChipSecure: A Reconfigurable Analog eFlash-Based PUF with Machine Learning Attack Resiliency in 55nm CMOS

    Mohammad Mahmoodi, Hussein Nili, Shabnam Larimian, Xinjie Guo, and Dmitri Strukov. ChipSecure: A Reconfigurable Analog eFlash-Based PUF with Machine Learning Attack Resiliency in 55nm CMOS. In Proceedings of the 56th Annual Design Automation Conference 2019, pages 1–6, 2019

    2019

  26. [33]

    An Aging-Resistant NAND Flash Memory Physical Unclonable Function.IEEE Transactions on Electron Devices, 67(3):937–943, 2020

    Sadman Sakib, Aleksandar Milenkovi´c, Md Tauhidur Rahman, and Biswajit Ray. An Aging-Resistant NAND Flash Memory Physical Unclonable Function.IEEE Transactions on Electron Devices, 67(3):937–943, 2020

    2020

  27. [34]

    Leakage-resilient memory- based physical unclonable function using phase change material

    Le Zhang, Chip-Hong Chang, Alessandro Cabrini, Guido Torelli, and Zhi Hui Kong. Leakage-resilient memory- based physical unclonable function using phase change material. In2014 International Carnahan Conference on Security Technology (ICCST), pages 1–6, 2014

    2014

  28. [35]

    Extracting Physically Unclonable Function From Spin Transfer Switching Characteristics in Magnetic Tunnel Junctions.IEEE Transactions on Magnetics, 50(11):1–4, 2014

    Takao Marukame, Tetsufumi Tanamoto, and Yuichiro Mitani. Extracting Physically Unclonable Function From Spin Transfer Switching Characteristics in Magnetic Tunnel Junctions.IEEE Transactions on Magnetics, 50(11):1–4, 2014

    2014

  29. [36]

    Emerging Physical Unclonable Functions With Nanotechnology.IEEE access, 4:61–80, 2017

    Yansong Gao, Damith C Ranasinghe, Said F Al-Sarawi, Omid Kavehei, and Derek Abbott. Emerging Physical Unclonable Functions With Nanotechnology.IEEE access, 4:61–80, 2017

    2017

  30. [37]

    Highly reliable memory-based Physical Unclonable Function using Spin-Transfer Torque MRAM

    Le Zhang, Xuanyao Fong, Chip-Hong Chang, Zhi Hui Kong, and Kaushik Roy. Highly reliable memory-based Physical Unclonable Function using Spin-Transfer Torque MRAM. InInt. symposium on circuits & systems, pages 2169–2172, 2014

    2014

  31. [38]

    Feasibility study of emerging non-volatile memory based physical unclonable functions

    Le Zhang, Xuanyao Fong, Chip-Hong Chang, Zhi Hui Kong, and Kaushik Roy. Feasibility study of emerging non-volatile memory based physical unclonable functions. InInt. Memory Workshop, pages 1–4, 2014

    2014

  32. [39]

    Security of emerging non-volatile memories: Attacks and defenses

    Kaveh Shamsi and Yier Jin. Security of emerging non-volatile memories: Attacks and defenses. InVLSI Test Symposium, pages 1–4, 2016

    2016

  33. [40]

    Exploiting resistive cross-point array for compact design of physical unclonable function

    Pai-Yu Chen, Runchen Fang, Rui Liu, Chaitali Chakrabarti, Yu Cao, and Shimeng Yu. Exploiting resistive cross-point array for compact design of physical unclonable function. InInt. Symposium on Hardware Oriented Security and Trust, pages 26–31, 2015

    2015

  34. [41]

    Memristor PUFs: A new generation of memory-based Physically Unclonable Functions

    Patrick Koeberl, Ünal Kocaba¸ s, and Ahmad-Reza Sadeghi. Memristor PUFs: A new generation of memory-based Physically Unclonable Functions. InDesign, Automation & Test in Eu. Conference, pages 428–431, 2013

    2013

  35. [42]

    Memristive crypto primitive for building highly secure physical unclonable functions.Scientific reports, 5(1):12785, 2015

    Yansong Gao, Damith C Ranasinghe, Said F Al-Sarawi, Omid Kavehei, and Derek Abbott. Memristive crypto primitive for building highly secure physical unclonable functions.Scientific reports, 5(1):12785, 2015

    2015

  36. [43]

    Performance analysis of a memristive crossbar PUF design

    Garrett S Rose and Chauncey A Meade. Performance analysis of a memristive crossbar PUF design. In Proceedings of the 52nd Annual Design Automation Conference, pages 1–6, 2015

    2015

  37. [44]

    A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source.IEEE Journal of Solid-State Circuits, pages 1641–1650, 2021

    Bohan Lin, Yachuan Pang, Bin Gao, Jianshi Tang, Dong Wu, Ting-Wei Chang, Wei-En Lin, Xiaoyu Sun, Shimeng Yu, Meng-Fan Chang, et al. A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source.IEEE Journal of Solid-State Circuits, pages 1641–1...

    2021

  38. [45]

    An overview of critical applications of resistive random access memory.Nanoscale Advances, 2024

    Furqan Zahoor, Arshid Nisar, Usman Isyaku Bature, Haider Abbas, Faisal Bashir, Anupam Chattopadhyay, Brajesh Kumar Kaushik, Ali Alzahrani, and Fawnizu Azmadi Hussin. An overview of critical applications of resistive random access memory.Nanoscale Advances, 2024

    2024

  39. [46]

    A review of emerging non-volatile memory (NVM) technologies and applications.Solid-State Electronics, pages 25–38, 2016

    An Chen. A review of emerging non-volatile memory (NVM) technologies and applications.Solid-State Electronics, pages 25–38, 2016

    2016

  40. [47]

    Self-Heating Phase-Change Memory-Array Demon- strator for True Random Number Generation.IEEE Transactions on Electron Devices, (5):2185–2192, 2017

    Enrico Piccinini, Rossella Brunetti, and Massimo Rudan. Self-Heating Phase-Change Memory-Array Demon- strator for True Random Number Generation.IEEE Transactions on Electron Devices, (5):2185–2192, 2017

    2017

  41. [48]

    A Calibration-Free In-Memory True Random Number Generator Using V oltage-Controlled MRAM

    Jiyue Yang, Di Wu, Albert Lee, Seyed Armin Razavi, Puneet Gupta, Kang L Wang, and Sudhakar Pamarti. A Calibration-Free In-Memory True Random Number Generator Using V oltage-Controlled MRAM. InIEEE 51st European Solid-State Device Research Conference, pages 115–118, 2021

    2021

  42. [49]

    A Contact- Resistive Random-Access-Memory-Based True Random Number Generator.Electron Device Letters, pages 1108–1110, 2012

    Chien-Yuan Huang, Wen Chao Shen, Yuan-Heng Tseng, Ya-Chin King, and Chrong-Jung Lin. A Contact- Resistive Random-Access-Memory-Based True Random Number Generator.Electron Device Letters, pages 1108–1110, 2012

    2012

  43. [50]

    A Survey on True Random Number Generators Based on Chaos.Discrete Dynamics in Nature and Society, pages 1–10, 2019

    Fei Yu, Lixiang Li, Qiang Tang, Shuo Cai, Yun Song, and Quan Xu. A Survey on True Random Number Generators Based on Chaos.Discrete Dynamics in Nature and Society, pages 1–10, 2019

    2019

  44. [51]

    Spin dice: A scalable truly random number generator based on spintronics.Applied Physics Express, (8):083001, 2014

    Akio Fukushima, Takayuki Seki, Kay Yakushiji, Hitoshi Kubota, Hiroshi Imamura, Shinji Yuasa, and Koji Ando. Spin dice: A scalable truly random number generator based on spintronics.Applied Physics Express, (8):083001, 2014

    2014

  45. [52]

    A spin orbit torque based true random number generator with real-time optimization

    Yang Liu, Zhaohao Wang, Zuwei Li, Xiaoxiao Wang, and Weisheng Zhao. A spin orbit torque based true random number generator with real-time optimization. In18th International Conference on Nanotechnology, pages 1–4, 2018. 17

    2018

  46. [53]

    A true random number generator based on parallel STT-MTJs

    Yuanzhuo Qu, Jie Han, Bruce F Cockburn, Witold Pedrycz, Yue Zhang, and Weisheng Zhao. A true random number generator based on parallel STT-MTJs. InDesign, Automation & Test in Eu. Conference & Exhibition, pages 606–609, 2017

    2017

  47. [54]

    True Random Number Generation Using Latency Variations of FRAM.IEEE Transactions on Very Large Scale Integration Systems, (1):14–23, 2020

    Md Imtiaz Rashid, Farah Ferdaus, BMS Bahar Talukder, Paul Henny, Aubrey N Beal, and Md Tauhidur Rahman. True Random Number Generation Using Latency Variations of FRAM.IEEE Transactions on Very Large Scale Integration Systems, (1):14–23, 2020

    2020

  48. [55]

    True Random Number Generation Using Read Noise of Flash Memory Cells.IEEE transactions on electron devices, (3):963–969, 2018

    Biswajit Ray and Aleksandar Milenkovi´c. True Random Number Generation Using Read Noise of Flash Memory Cells.IEEE transactions on electron devices, (3):963–969, 2018

    2018

  49. [56]

    Design of an STT-MTJ based true random number generator using digitally controlled probability-locked loop

    Satoshi Oosawa, Takayuki Konishi, Naoya Onizawa, and Takahiro Hanyu. Design of an STT-MTJ based true random number generator using digitally controlled probability-locked loop. In2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), pages 1–4, 2015

    2015

  50. [57]

    Generating true random numbers using on-chip complemen- tary polarizer spin-transfer torque magnetic tunnel junctions

    Xuanyao Fong, Mei-Chin Chen, and Kaushik Roy. Generating true random numbers using on-chip complemen- tary polarizer spin-transfer torque magnetic tunnel junctions. InDevice Research Conference, pages 103–104, 2014

    2014

  51. [58]

    Security primitives (PUF and TRNG) with STT-MRAM

    Elena Ioana Vatajelu, Giorgio Di Natale, and Paolo Prinetto. Security primitives (PUF and TRNG) with STT-MRAM. InIEEE 34th VLSI Test Symposium, pages 1–4, 2016

    2016

  52. [59]

    A Morphable Physically Unclonable Function and True Random Number Generator using a Commercial Magnetic Memory.Journal of Low Power Electronics and Applications, (1):5, 2021

    Mohammad Nasim Imtiaz Khan, Chak Yuen Cheng, Sung Hao Lin, Abdullah Ash-Saki, and Swaroop Ghosh. A Morphable Physically Unclonable Function and True Random Number Generator using a Commercial Magnetic Memory.Journal of Low Power Electronics and Applications, (1):5, 2021

    2021

  53. [60]

    True random number generator using current difference based on a fractional stochastic model in 40-nm embedded ReRAM

    Z Wei, Y Katoh, S Ogasahara, Y Yoshimoto, K Kawai, Y Ikeda, K Eriguchi, K Ohmori, and S Yoneda. True random number generator using current difference based on a fractional stochastic model in 40-nm embedded ReRAM. InInternational Electron Devices Meeting, pages 4–8, 2016

    2016

  54. [61]

    CSRO-Based Reconfigurable True Random Number Generator Using RRAM.IEEE Transactions on VLSI Systems, (12):2661–2670, 2018

    Rekha Govindaraj, Swaroop Ghosh, and Srinivas Katkoori. CSRO-Based Reconfigurable True Random Number Generator Using RRAM.IEEE Transactions on VLSI Systems, (12):2661–2670, 2018

    2018

  55. [62]

    A novel true random number generator based on a stochastic diffusive memristor

    Hao Jiang, Daniel Belkin, Sergey E Savel’ev, Siyan Lin, Zhongrui Wang, Yunning Li, Saumil Joshi, Rivu Midya, Can Li, Mingyi Rao, et al. A novel true random number generator based on a stochastic diffusive memristor. Nature communications, 8(1):882, 2017

    2017

  56. [63]

    A High-Speed and High-Reliability TRNG Based on Analog RRAM for IoT Security Application

    Bohan Lin, Bin Gao, Yachuan Pang, Peng Yao, Dong Wu, Hu He, Jianshi Tang, He Qian, and Huaqiang Wu. A High-Speed and High-Reliability TRNG Based on Analog RRAM for IoT Security Application. InIEEE International Electron Devices Meeting, pages 14–8, 2019

    2019

  57. [64]

    Application of Resistive Random Access Memory in Hardware Security: A Review.Advanced Electronic Materials, (12):2100536, 2021

    Gokulnath Rajendran, Writam Banerjee, Anupam Chattopadhyay, and Mohamed M Sabry Aly. Application of Resistive Random Access Memory in Hardware Security: A Review.Advanced Electronic Materials, (12):2100536, 2021

    2021

  58. [65]

    True Random Number Generation From Commodity NVM Chips.IEEE Transactions on Electron Devices, (3):888–894, 2020

    Supriya Chakraborty, Abhilash Garg, and Manan Suri. True Random Number Generation From Commodity NVM Chips.IEEE Transactions on Electron Devices, (3):888–894, 2020

    2020

  59. [66]

    Logic Locking Using Emerging 2T/3T Magnetic Tunnel Junctions for Hardware Security.IEEE Access, pages 102386–102395, 2022

    Divyanshu Divyanshu, Rajat Kumar, Danial Khan, Selma Amara, and Yehia Massoud. Logic Locking Using Emerging 2T/3T Magnetic Tunnel Junctions for Hardware Security.IEEE Access, pages 102386–102395, 2022

    2022

  60. [67]

    Physical Unclonable Functions Using Ferroelectric Tunnel Junctions.IEEE Electron Device Letters, (6):816–819, 2021

    Sihyun Kim, Kitae Lee, Min-Hye Oh, Jong-Ho Lee, Byung-Gook Park, and Daewoong Kwon. Physical Unclonable Functions Using Ferroelectric Tunnel Junctions.IEEE Electron Device Letters, (6):816–819, 2021

    2021

  61. [68]

    FORTIS: A Comprehensive Solution for Establishing Forward Trust for Protecting IPs and ICs.ACM Transactions on Design Automation of Electronic Systems (TODAES), 21(4):1–20, 2016

    Ujjwal Guin, Qihang Shi, Domenic Forte, and Mark M Tehranipoor. FORTIS: A Comprehensive Solution for Establishing Forward Trust for Protecting IPs and ICs.ACM Transactions on Design Automation of Electronic Systems (TODAES), 21(4):1–20, 2016

    2016

  62. [69]

    Camskygate: camouflaged skyrmion gates for protecting ics

    Yuqiao Zhang, Chunli Tang, Peng Li, and Ujjwal Guin. Camskygate: camouflaged skyrmion gates for protecting ics. InProceedings of the 59th ACM/IEEE Design Automation Conference, pages 757–762, 2022

    2022

  63. [70]

    Comprehensive Study of Side-Channel Attack on Emerging Non-V olatile Memories.Journal of Low Power Electronics and Applications, (4):38, 2021

    Mohammad Nasim Imtiaz Khan, Shivam Bhasin, Bo Liu, Alex Yuan, Anupam Chattopadhyay, and Swaroop Ghosh. Comprehensive Study of Side-Channel Attack on Emerging Non-V olatile Memories.Journal of Low Power Electronics and Applications, (4):38, 2021

    2021

  64. [71]

    Side-Channel Attack on STTRAM Based Cache for Cryptographic Application

    Mohammad Nasim Imtiaz Khan, Shivam Bhasin, Alex Yuan, Anupam Chattopadhyay, and Swaroop Ghosh. Side-Channel Attack on STTRAM Based Cache for Cryptographic Application. InInt. Conference on Computer Design, pages 33–40, 2017

    2017

  65. [72]

    Correlation power analysis attack against STT- MRAM based cyptosystems.Cryptology ePrint Archive, 2017

    Abhishek Chakraborty, Ankit Mondal, and Ankur Srivastava. Correlation power analysis attack against STT- MRAM based cyptosystems.Cryptology ePrint Archive, 2017. 18

    2017

  66. [73]

    SCARE: Side Channel Attack on In-Memory Computing for Reverse Engineering.Transactions on VLSI Systems, (12):2040–2051, 2021

    Sina Sayyah Ensan, Karthikeyan Nagarajan, Mohammad Nasim Imtiaz Khan, and Swaroop Ghosh. SCARE: Side Channel Attack on In-Memory Computing for Reverse Engineering.Transactions on VLSI Systems, (12):2040–2051, 2021

    2021

  67. [74]

    Seasoning effect based side channel attacks to AES implementation with Phase Change Memory

    Lei Xu, Weidong Shi, and Nicholas Desalvo. Seasoning effect based side channel attacks to AES implementation with Phase Change Memory. InProceedings of the Third Workshop on Hardware and Architectural Support for Security and Privacy, pages 1–8, 2014

    2014

  68. [75]

    Investigation of Side Channel Leakage of FeRAM Using Discrete Wavelet Transform

    Abyad Enan and Mohammed Imamul Hassan Bhuiyan. Investigation of Side Channel Leakage of FeRAM Using Discrete Wavelet Transform. InInternational Conference on Telecommunications and Photonics, pages 1–4, 2019

    2019

  69. [76]

    Emerging Nonvolatile Memories—An Assessment of Vulnerability to Probing Attacks

    Liton Kumar Biswas, M Shafkat, M Khan, Leonidas Lavdas, and Navid Asadizanjani. Emerging Nonvolatile Memories—An Assessment of Vulnerability to Probing Attacks. InISTFA, pages 217–224, 2022

    2022

  70. [77]

    Fault injection attacks on emerging non-volatile memory and countermeasures

    Mohammad Nasim Imtiaz Khan and Swaroop Ghosh. Fault injection attacks on emerging non-volatile memory and countermeasures. InProceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, pages 1–8, 2018

    2018

  71. [78]

    Evaluation of the Sensitivity of RRAM Cells to Optical Fault Injection Attacks

    Dmytro Petryk, Zoya Dyka, Eduardo Perez, Mamathamba Kalishettyhalli Mahadevaiaha, Ievgen Kabin, Christian Wenger, and Peter Langendörfer. Evaluation of the Sensitivity of RRAM Cells to Optical Fault Injection Attacks. In23rd Euromicro Conference on Digital System Design, pages...

    2020

  72. [79]

    Fault Attack Investigation on TaO x Resistive-RAM for Cyber Secure Application.IEEE Transactions on Electron Devices, 70(8):4170–4177, 2023

    Ankit Kumar, Robin Degraeve, Arthur Beckers, Andrea Fantini, Ingrid Verbauwhede, Dimitri Linten, and Gouri S Kar. Fault Attack Investigation on TaO x Resistive-RAM for Cyber Secure Application.IEEE Transactions on Electron Devices, 70(8):4170–4177, 2023

    2023

  73. [80]

    Flash Memory ‘Bumping’ Attacks

    Sergei Skorobogatov. Flash Memory ‘Bumping’ Attacks. InInternational Workshop on Cryptographic Hardware and Embedded Systems, pages 158–172. Springer, 2010

    2010

  74. [81]

    Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller

    Baptiste Colombier, Alain Menu, Jean-Max Dutertre, Paul-Alain Moëllic, Jean-Baptiste Rigaud, and Jean-Luc Danger. Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller. IACR Cryptology ePrint Archive, 2018:1042, 2018

    2018

  75. [82]

    Romain A. C. Viera, Jean-Max Dutertre, and Paul-Alain Moëllic. Permanent Laser Fault Injection into the Flash Memory of a Microcontroller. In2021 IEEE 19th International New Circuits and Systems Conference (NEWCAS), pages 1–4, 2021

    2021

  76. [83]

    Martin Schink, Andreas Wagner, Florian Oberhansl, Simon Köckeis, Erwin Strieder, et al. Unlock the Door to my Secrets, but don’t Forget to Glitch: A Comprehensive Analysis of Flash Erase Suppression Attacks.IACR Transactions on Cryptographic Hardware and Embedded Systems, 2024...

    2024

  77. [84]

    Experimental Study of Adversarial Magnetic Field Exposure Attacks on Toggle MRAM Chips.IEEE Transactions on Electron Devices, 69(3):1480–1485, 2022

    Subhadeep Chakraborty and Manan Suri. Experimental Study of Adversarial Magnetic Field Exposure Attacks on Toggle MRAM Chips.IEEE Transactions on Electron Devices, 69(3):1480–1485, 2022

    2022

  78. [85]

    Sousa, Gael Di Pendina, and Paul Canet

    Nadim Yazigy, Jean Postel-Pellerin, Valerio De Marca, Ricardo C. Sousa, Gael Di Pendina, and Paul Canet. Correlation between 1064 nm laser attack and thermal behavior in STT-MRAM.Microelectronics Reliability, 150:115167, 2023

    2023

  79. [86]

    Assessing Magnetic Attack on Commercial 40 nm pMTJ STT-MRAM

    Md Shoaib Ahmed, Biplab Ray, et al. Assessing Magnetic Attack on Commercial 40 nm pMTJ STT-MRAM. In IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE), 2024

    2024

  80. [87]

    Analysis of Row Hammer Attack on STTRAM

    Mohammad Nasim Imtiaz Khan and Swaroop Ghosh. Analysis of Row Hammer Attack on STTRAM. In International Conference on Computer Design, pages 75–82, 2018

    2018

  81. [88]

    NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories

    Felix Staudigl, Hazem Al Indari, Daniel Schön, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, and Rainer Leupers. NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. InDesign, Automation & Test in Europe Conference & Exhibition...

    2022

  82. [89]

    rowhammer

    Anil Kurmus, Nikolas Ioannou, Matthias Neugschwandtner, Nikolaos Papandreou, and Thomas Parnell. Is there a “rowhammer” for MLC NAND Flash SSDs? An analysis of filesystem attack vectors. InUSENIX Workshop on Offensive Technologies co-located with USENIX Security, 2017

    2017

  83. [90]

    Information Leakage Attacks on Emerging Non-V olatile Memory and Countermeasures

    Mohammad Nasim Imtiaz Khan and Swaroop Ghosh. Information Leakage Attacks on Emerging Non-V olatile Memory and Countermeasures. InProceedings of the International Symposium on Low Power Electronics and Design, pages 1–6, 2018

    2018

  84. [91]

    Are Crossbar Memories Secure? New Security Vulnerabilities in Crossbar Memories.IEEE Computer Architecture Letters, 18(2):174–177, 2019

    Vamsee Reddy Kommareddy, Baogang Zhang, Fan Yao, Rickard Ewetz, and Amro Awad. Are Crossbar Memories Secure? New Security Vulnerabilities in Crossbar Memories.IEEE Computer Architecture Letters, 18(2):174–177, 2019. 19

    2019

  85. [92]

    Security challenges of processing-in-memory systems

    Md Tanvir Arafin and Zhaojun Lu. Security challenges of processing-in-memory systems. InProceedings of the 2020 on Great Lakes Symposium on VLSI (GLSVLSI ’20), pages 229–234. ACM, September 2020

    2020

  86. [93]

    Security Vulnerabilities of Emerging Nonvolatile Main Memories and Countermeasures.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (1):2–15, 2014

    Sachhidh Kannan, Naghmeh Karimi, Ozgur Sinanoglu, and Ramesh Karri. Security Vulnerabilities of Emerging Nonvolatile Main Memories and Countermeasures.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (1):2–15, 2014

    2014

  87. [95]

    It’s Getting Hot in Here: Hardware Security Implications of Thermal Crosstalk on ReRAMs.IEEE Transactions on Reliability, 2024

    Felix Staudigl, Hazem Al Indari, Daniel Schön, Hsin-Yu Chen, Dominik Sisejkovic, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Amelie Hagelauer, and Rainer Leupers. It’s Getting Hot in Here: Hardware Security Implications of Thermal Crosstalk on ReRAMs.IEEE Transactions on Re...

    2024

  88. [96]

    Rowhammer for Spin Torque based Memory: Problem or not? InInternational Magnetics Conference, pages 1–1, 2018

    S Agarwal, H Dixit, D Datta, M Tran, D Houssameddine, D Shum, and F Benistant. Rowhammer for Spin Torque based Memory: Problem or not? InInternational Magnetics Conference, pages 1–1, 2018

    2018

  89. [97]

    Performance Impact of Magnetic and Thermal Attack on STTRAM and Low-Overhead Mitigation Techniques

    Jae-Won Jang and Swaroop Ghosh. Performance Impact of Magnetic and Thermal Attack on STTRAM and Low-Overhead Mitigation Techniques . InProceedings of the 2016 International Symposium on Low Power Electronics and Design, pages 136–141, 2016

    2016

  90. [98]

    An operating system level data migration scheme in hybrid DRAM-NVM memory architecture

    Reza Salkhordeh and Hossein Asadi. An operating system level data migration scheme in hybrid DRAM-NVM memory architecture. In2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 936–941, 2016

    2016

  91. [99]

    A compute-in-memory chip based on resistive random-access memory.Nature, 608(7923):504–512, 2022

    Weier Wan, Rajkumar Kubendran, Clemens Schaefer, Sukru Burc Eryilmaz, Wenqiang Zhang, Dabin Wu, Stephen Deiss, Priyanka Raina, He Qian, Bin Gao, et al. A compute-in-memory chip based on resistive random-access memory.Nature, 608(7923):504–512, 2022

    2022

  92. [100]

    NVMExplorer: A Framework for Cross-Stack Comparisons of Embedded Non-V olatile Memories.arXiv preprint arXiv:2109.01188, 2021

    Lillian Pentecost, Alexander Hankin, Marco Donato, Mark Hempstead, Gu-Yeon Wei, and David Brooks. NVMExplorer: A Framework for Cross-Stack Comparisons of Embedded Non-V olatile Memories.arXiv preprint arXiv:2109.01188, 2021

    2021 arXiv

  93. [101]

    Binary Neural Network with 16 Mb RRAM Macro Chip for Classification and Online Training

    Shimeng Yu, Zhiwei Li, Pai-Yu Chen, Huaqiang Wu, Bin Gao, Deli Wang, Wei Wu, and He Qian. Binary Neural Network with 16 Mb RRAM Macro Chip for Classification and Online Training. In2016 IEEE International Electron Devices Meeting (IEDM), pages 16–2, 2016

    2016

  94. [102]

    Endurance Management for Resistive Logic-In-Memory Computing Architectures

    Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, and Rolf Drechsler. Endurance Management for Resistive Logic-In-Memory Computing Architectures. InDesign, Automation & Test in Europe Conference & Exhibition (DATE), 2017, pages 1092–1097, 2017. 20

    2017

Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.