ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection

Dan Niu; Juxin Niu; Nan Guan; Xiangfeng Liu; Xi Wang; Zhe Jiang

REVIEW 4 major objections 4 minor 36 references

ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection

T0 review · 4 major / 4 minor · reviewed 2026-08-07 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗

Pith's one-line read ReChisel claims that an LLM agent reflecting on compiler and simulator feedback can raise Chisel code generation from roughly 26–45 percent to 73–85 percent Pass@1 across five models, matching state-of-the-art Verilog-generating agents.

desk verdict ReChisel's reflection loop is a plausible and useful contribution; the undisclosed CommonErrorKnowledge prompt provenance is the main thing I'd want clarified before trusting the headline numbers. read the letter →

arxiv 2505.19734 v1 pith:B22QDVZU submitted 2025-05-26 cs.AI cs.AR

Juxin Niu , Xiangfeng Liu , Dan Niu , Xi Wang , Zhe Jiang , Nan Guan This is my paper

classification cs.AIcs.AR

keywords ChiselLLMcodegenerationreflectionhardwaredescriptionlanguageagenticsystemVerilogRTL

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper aims to show that Chisel, a Scala-based hardware description language with far less public code than Verilog, can still be a viable target for LLM-based hardware generation if the LLM is wrapped in an agentic loop. The proposed system, ReChisel, iteratively generates Chisel code, compiles it to Verilog, runs a simulation, and feeds concrete compiler and simulation errors back to the LLM for revision. On a filtered set of 216 module-level cases drawn from three established Verilog benchmarks, this lifts Pass@1 from roughly 26–45 percent in zero-shot settings to 73–85 percent across five mainstream LLMs. The central point is that reflection on executable feedback can largely close the performance gap between Chisel and Verilog generation, even when the underlying language is scarce in training data.

What carries the argument

The load-bearing mechanism is the reflection loop composed of four roles: a Generator that writes Chisel code, a Compiler and Simulator that act as external tools converting Chisel to Verilog and executing the testbench, an Inspector that maintains a trace of all feedback and detects repeated failures, and a Reviewer that converts the trace into a structured revision plan. Two feedback types drive the loop: compiler feedback, which gives the error location, description, and suggested fix for syntax and static-analysis errors, and simulation feedback, which lists failed test points with input stimuli, expected output, and actual output. An escape mechanism detects non-progress loops by comparing the current error against previous trace entries; when the same location and same cause recur, the intervening iterations are discarded and a fresh revision plan is generated from the step before the loop. The prompts also embed CommonErrorKnowledge, a pre-organized set of common syntax errors and fix guidelines used as in-context learning to make reviewer feedback faster and more accurate.

What would settle it

A concrete check is to run ReChisel on the same 216 cases with the CommonErrorKnowledge section removed from the Reviewer prompt, and separately with a taxonomy built only from a held-out set of Chisel errors; if Pass@1 drops by more than a few points when that knowledge is removed, the reported gains depend on benchmark-derived hints rather than on the reflection loop alone.

Watch

Extended reading notes

Core claim

The paper's central claim is that an LLM-based agentic system with a reflection loop can make Chisel code generation competitive with state-of-the-art Verilog code generation systems. Concretely, ReChisel takes a natural-language specification and a testbench, asks an LLM to write Chisel code, compiles that code to Verilog through the standard Chisel/FIRRTL toolchain, and simulates the resulting Verilog against the testbench. When compilation or simulation fails, an Inspector maintains a trace of all previous attempts, a Reviewer analyzes the trace to produce a revision plan with error location, root cause, and fix, and the Generator produces a corrected version. The paper reports that on 216 filtered cases from VerilogEval, AutoChip's HDLBits, and RTLLM, ReChisel improves LLM success rates substantially, and for GPT-4o it even outperforms AutoChip, a comparable agentic system that generates Verilog directly, on Pass@5 and Pass@10. The authors frame this as evidence that Chisel is not inherently a poor target for LLM-driven hardware design once feedback-based refinement is available.

Load-bearing premise

The paper never states where the CommonErrorKnowledge injected into the Reviewer prompt came from; if it was harvested from the same evaluation benchmarks used for testing, the reported success rates include test-set leakage and the gains over zero-shot baselines would shrink on unseen specifications.

Editorial extensions

If this is right

If ReChisel's reported numbers hold, Chisel becomes a practical language for LLM-assisted RTL generation despite having roughly 1/20th the public code of Verilog.
Reflection on compiler and simulator feedback appears to be a transferable recipe for low-resource HDLs beyond Chisel, since the loop depends on executable feedback rather than language-specific training data.
The escape mechanism addresses a known failure mode of self-correcting LLM agents, specifically the tendency to cycle through the same ineffective fix; detecting and discarding such loops is a general technique applicable to other code-generation agents.
The near-parity with AutoChip on Verilog suggests that the bottleneck in LLM hardware design is not the language itself but the availability of feedback signals during generation.
Because ReChisel is open-sourced, the specific prompts, trace structures, and escape logic can be reproduced and adapted by others working on HDL generation.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The method is fundamentally dependent on the availability of a testbench for every specification; without executable tests, neither compilation-only feedback nor simulation feedback can drive the loop, so the reported gains may not transfer to open-ended spec-to-RTL tasks where testbenches are absent.
The paper does not state where the CommonErrorKnowledge used in the Reviewer prompts came from; if that error taxonomy and its fixes were derived from the same VerilogEval, HDLBits, or RTLLM cases used for evaluation, the reported gains would include test-set leakage, and a held-out evaluation could shrink them.
The escape mechanism's cycle detection is a heuristic judged by the LLM itself (same error location plus same cause), so its precision is not measured; counting how often the mechanism fires and whether discarded iterations ever contained useful fixes would clarify its real contribution.
The comparison with AutoChip is limited to three models and three benchmarks; an obvious extension is to test whether the same ReChisel loop, applied to Verilog generation instead of Chisel, would improve Verilog agents as well, which the paper does not do.

Share X Bluesky LinkedIn Reddit HN

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

ReChisel wraps an LLM in a reflection loop with compiler/simulator feedback, adds an escape mechanism for non-progress loops, and targets Chisel code generation. The gains are large and consistent: Pass@1 rises from roughly 26–45% to 73–85% across five models on a filtered 216-case module-level benchmark. The comparison with AutoChip on the same benchmarks is a fair way to test whether Chisel can become a viable LLM target, and the answer is a credible yes. The escape mechanism is the one genuinely new piece; I don't see it in AutoChip or Reflexion.

The central claim holds up about as well as the evidence allows. The baseline gap between Chisel and Verilog is real, the reflection loop is externally grounded (compiler and simulator feedback), and the improvement is monotone with iterations. The code and data are open-sourced, which helps.

Three soft spots, in proportion. First, the CommonErrorKnowledge in-context prompt. Section IV-B says the authors pre-organized causes and fix guidance and included it in the prompts, but they never say where that taxonomy came from. If it was mined from the same 216 test cases, part of the reported gain is prompt-level overfitting to the test distribution, not general Chisel ability. The examples in Table II look generic — misspellings, missing IO wrappers, type mismatches — so the risk is moderate, not fatal, but it's not zero. An ablation with and without that prompt would settle it, and none is reported. Second, the escape mechanism isn't ablated, so its contribution is unknown. Third, the statistical reporting is thin: no confidence intervals, no significance tests, and the filtering from the original benchmarks to 216 cases isn't quantified.

This paper deserves a serious referee. I'd send it to review with a request for three additions: an ablation of CommonErrorKnowledge, an ablation of the escape mechanism, and explicit disclosure of how the prompt content was constructed. If those come back clean, it's a solid addition to the LLM-for-HDL line. If the CommonErrorKnowledge was harvested from the test set, the reported gains will shrink on unseen specs, and the paper should be reframed as a benchmark-specific prompt-tuning result.

Referee Report

4 major / 4 minor

Summary. ReChisel is an LLM-based agentic system for automatic Chisel code generation. It couples a Generator, Inspector, Reviewer, and external Compiler/Simulator in an iterative reflection loop: compiler and simulation feedback is summarized into a trace, the Reviewer produces a revision plan, and an escape mechanism discards detected non-progress loops. The system is evaluated on 216 module-level cases filtered from VerilogEval's Spec-to-RTL, AutoChip's HDLBits, and RTLLM, using five LLMs. The reported results show large gains over zero-shot baselines, e.g., Claude 3.5 Sonnet Pass@1 rising from 33.33% to 84.98% at ten iterations, and performance comparable to AutoChip on Verilog generation. The paper also presents a baseline study comparing Chisel and Verilog generation capabilities.

Significance. If the headline result holds, ReChisel is a meaningful contribution: it is one of the first agentic systems targeting Chisel, it is open-sourced, and its reflection loop is externally grounded in compiler and simulator feedback rather than being a purely self-referential prompting scheme. The reported improvements are consistent across five models and three benchmarks, which strengthens the plausibility of the central claim. However, the significance depends on whether the CommonErrorKnowledge injected into the Reviewer prompt was constructed independently of the evaluation cases and whether the ablation evidence supports the claimed contributions of the escape mechanism. The paper also provides a useful baseline comparison of Chisel versus Verilog LLM code generation, even though this part is not the main contribution.

major comments (4)

[IV-B, Table II] The provenance of CommonErrorKnowledge is undisclosed and this is load-bearing for the reported gains. Section IV-B states that the authors 'pre-organized the causes and corresponding fix guidance for each error and included this information within the prompts,' but the paper never states whether this knowledge was derived from the same 216 evaluation cases used in Section V. If the error taxonomy and fixes were harvested from VerilogEval, HDLBits, and RTLLM, the Reviewer prompt contains information about the test distribution, and the reported Pass@1 gains (e.g., Claude 3.5 Sonnet from 33.33% to 84.98%) partly measure prompt-level leakage rather than the reflection loop alone. The paper needs either an explicit statement that CommonErrorKnowledge was constructed before and independently of the benchmark suite, or an ablation that removes it and a held-out evaluation on cases not used to build the taxonomy.
[IV-C and V-B] The escape mechanism is never ablated. The paper motivates the mechanism with the non-progress loop example in Fig. 4 and claims it enables the system to break out of cycles, but no experiment compares ReChisel with and without the escape mechanism. Since the mechanism is presented as a central component alongside reflection, its contribution to the final success rates should be quantified. Without such an ablation, it is unclear whether the gains come from the reflective loop alone or from the escape component, and the paper's attribution of the improvement to both mechanisms is not supported by the reported results.
[V-A, V-B, Table III] The reported success rates lack confidence intervals and significance testing. Each case is tested ten times, but the paper reports only point estimates, and several comparisons are close (e.g., Claude 3.5 Sonnet versus Haiku at Pass@1 and n=10: 84.98% versus 84.51%). Without per-case variance or bootstrap confidence intervals, the reader cannot assess whether differences between models or between ReChisel and AutoChip are meaningful. This is particularly relevant to the claim that ReChisel achieves performance 'comparable' to Verilog agentic systems, since the comparison in Table IV shows differences of a few percentage points.
[V-A] The filtering of the benchmark set is not characterized enough to rule out selection bias. The paper excludes cases that are incompatible with Chisel, have missing reference code, or are designed for debugging/completion, but it does not report how many cases were removed per benchmark or how the filtered subset compares with the original benchmarks on difficulty. If the filtering disproportionately removes hard cases, the absolute success rates on the 216-case set may overstate ReChisel's ability on full benchmark suites. Reporting per-benchmark filtered counts and baseline performance on both filtered and unfiltered sets would address this concern.

minor comments (4)

[V-B] The sentence 'Table I demonstrates the performance improvements achieved by ReChisel' appears to refer to Table III, since Table I reports baseline comparisons, not ReChisel performance. This should be corrected.
[Fig. 1] The stacked bar chart would benefit from a numeric breakdown per model and an explicit statement of whether the percentages are computed over all generated attempts or over a fixed number of samples; this would make the error-type analysis easier to interpret.
[IV-C] The description of the escape mechanism's cycle detection says the Inspector compares 'the current feedback' with trace entries and checks whether errors occur at the same location with identical causes, but the exact prompt or algorithm used to determine 'identical causes' is not specified; a short pseudocode or formal condition would improve reproducibility.
[V-A] The evaluation reports temperature and top-p as default configurations, but the specific default values are not listed; since Pass@k is computed from ten samples per case, stating the sampling configuration would make the results more reproducible.

Circularity Check

0 steps flagged · score 0.0 of 10

No demonstrated circularity: ReChisel's reflection loop is grounded in external compiler/simulator feedback; the undisclosed provenance of CommonErrorKnowledge is an evaluation-leakage risk, not a by-construction circular step.

full rationale

The central claim is that ReChisel improves Chisel code generation through iterative refinement using compiler and simulator feedback. The pass/fail signal is external to the method: the Chisel compiler checks syntactic/static correctness and the Verilog simulator compares against reference outputs. No equation in the paper defines any measured quantity in terms of the method's own inputs, and the reflection/escape loop is a standard agentic mechanism rather than a self-referential derivation. The only potentially concerning component is CommonErrorKnowledge (Section IV-B, Table II): the paper states that the authors 'pre-organized the causes and corresponding fix guidance for each error and included this information within the prompts,' but it does not disclose whether that error taxonomy was harvested from the same 216 filtered evaluation cases. If it were, the reported gains would partly reflect test-set leakage. However, the paper provides no textual evidence establishing that reduction, and the examples in Table II are general Chisel/Scala error categories (syntax mixing, signal typing, initialization, combinational loops) rather than case-specific answers. Under the requirement to demonstrate circularity by quotation and construction, this remains an experiment-design and provenance risk, not a demonstrated circular equivalence. No load-bearing self-citation is present: prior works with overlapping authors, such as ChatChisel and ChatCPU, are cited only as background and do not supply the paper's main mechanism or its evaluation criterion. The benchmarks and compilers are independent external checks, so the reported success rates are not forced by definitional identity with the method's inputs.

Assumptions & free parameters 2 free parameters · 4 assumptions · 0 invented entities

This is an empirical systems paper rather than a derivation, so the ledger contains no mathematical free parameters. The two hand-set evaluation constants, the representative-benchmark assumption, and the uncontaminated-prompt assumption are the main things the empirical claim rests on.

free parameters (2)

maximum_iterations = 10
The cap on reflection iterations is set to 10; the paper shows success rate rises with iteration count, so this choice directly bounds the reported pass rates.
num_samples_per_case = 10
Each of the 216 cases is sampled 10 times to compute Pass@k; this is a hand-chosen evaluation budget that affects the variance of the reported rates.

assumptions (4)

domain assumption The filtered 216-case benchmark is a representative sample of Chisel code generation difficulty.
Section V-A filters the original VerilogEval, HDLBits, and RTLLM sets to cases compatible with Chisel; the paper assumes this subset supports fair comparison with Verilog agents.
domain assumption The reference modules and testbenches in the benchmarks are correct.
The simulation stage compares DUT output against a reference module; the entire correctness signal depends on those references being right.
ad hoc to paper CommonErrorKnowledge used in the Reviewer prompt does not encode exact solutions to the evaluation cases.
Section IV-B injects pre-organized error causes and fixes into the prompts; if these were derived from the test cases, the evaluation is contaminated. The paper does not disclose the provenance.
domain assumption Chisel-to-Verilog compilation via FIRRTL preserves functional behavior.
Section II-B describes the compilation flow; ReChisel validates Chisel by simulating the compiled Verilog, assuming the transform is faithful.

how reviews work

0 comments

Cite this review

Pith. "Pith review of ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection." pith.science (2026). https://pith.science/paper/B22QDVZU

@misc{pith2026250519734,
  author       = {Pith},
  title        = {Pith review of: ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/B22QDVZU}},
  note         = {Machine review of arXiv:2505.19734}
}

read the original abstract

Coding with hardware description languages (HDLs) such as Verilog is a time-intensive and laborious task. With the rapid advancement of large language models (LLMs), there is increasing interest in applying LLMs to assist with HDL coding. Recent efforts have demonstrated the potential of LLMs in translating natural language to traditional HDL Verilog. Chisel, a next-generation HDL based on Scala, introduces higher-level abstractions, facilitating more concise, maintainable, and scalable hardware designs. However, the potential of using LLMs for Chisel code generation remains largely unexplored. This work proposes ReChisel, an LLM-based agentic system designed to enhance the effectiveness of Chisel code generation. ReChisel incorporates a reflection mechanism to iteratively refine the quality of generated code using feedback from compilation and simulation processes, and introduces an escape mechanism to break free from non-progress loops. Experiments demonstrate that ReChisel significantly improves the success rate of Chisel code generation, achieving performance comparable to state-of-the-art LLM-based agentic systems for Verilog code generation.

Figures

Figures reproduced from arXiv: 2505.19734 by the authors.

**Figure 3.** Example of compiler feedback and revision plan. [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗

**Figure 5.** Illustration of escape mechanism. error message indicating unsupported syntax in the switch block. Affected by this error, the reviewer focuses solely on correcting issues inside the switch block in subsequent attempts, ignoring the true location of the error which can only be captured from a global perspective. Additionally, the LLM has a limited context length, which means that as the number of iterations increase… view at source ↗

Figures from the paper (3 more)

**Figure 6.** Figure 6: Relationship between success rate and number of iterations for different LLMs. [PITH_FULL_IMAGE:figures/full_fig_p006_6.png]

**Figure 7.** Figure 7: Proportion of syntax and functional errors across iterations. [PITH_FULL_IMAGE:figures/full_fig_p006_7.png]

**Figure 8.** Figure 8: Case study on reflection. Green underlined codes represent [PITH_FULL_IMAGE:figures/full_fig_p006_8.png]

Discussion (0). Sign in to comment.

Reference graph

Works this paper leans on

36 extracted references · 15 canonical work pages

[1]

The rocket chip generator,

K. Asanovic, R. Avizienis, J. Bachrach, S. Beamer, D. Biancolin, C. Celio, H. Cook, D. Dabbelt, J. Hauser, A. Izraelevitzet al., “The rocket chip generator,”EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2016-17, vol. 4, pp. 6–2, 2016

work page 2016
[2]

Chisel: constructing hardware in a scala embedded language,

J. Bachrach, H. V o, B. Richards, Y . Lee, A. Waterman, R. Avi ˇzienis, J. Wawrzynek, and K. Asanovi ´c, “Chisel: constructing hardware in a scala embedded language,” inProceedings of the 49th Annual Design Automation Conference, 2012, pp. 1216–1225

work page 2012
[3]

Chip-chat: Chal- lenges and opportunities in conversational hardware design,

J. Blocklove, S. Garg, R. Karri, and H. Pearce, “Chip-chat: Chal- lenges and opportunities in conversational hardware design,” in2023 ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD). IEEE, 2023, pp. 1–6

2023
[4]

Chipgpt: How far are we from natural language hardware design,

K. Chang, Y . Wang, H. Ren, M. Wang, S. Liang, Y . Han, H. Li, and X. Li, “Chipgpt: How far are we from natural language hardware design,” arXiv preprint arXiv:2305.14019, 2023

arXiv 2023
[5]

Evaluating large language models trained on code,

M. Chen, J. Tworek, H. Jun, Q. Yuan, H. P. D. O. Pinto, J. Kaplan, H. Edwards, Y . Burda, N. Joseph, G. Brockmanet al., “Evaluating large language models trained on code,”arXiv preprint arXiv:2107.03374, 2021

arXiv 2021
[6]

Magma-si: A matrix accelerator generator,

M.-S. Contributors, “Magma-si: A matrix accelerator generator,” https: //github.com/merledu/magma-si, 2024, accessed: 2024-11-15

work page 2024
[7]

A survey on in-context learning,

Q. Dong, L. Li, D. Dai, C. Zheng, J. Ma, R. Li, H. Xia, J. Xu, Z. Wu, T. Liuet al., “A survey on in-context learning,”arXiv preprint arXiv:2301.00234, 2022

arXiv 2022
[8]

Gemmini: An agile systolic array generator enabling systematic evaluations of deep-learning architec- tures,

H. Genc, A. Haj-Ali, V . Iyer, A. Amid, H. Mao, J. Wright, C. Schmidt, J. Zhao, A. Ou, M. Banisteret al., “Gemmini: An agile systolic array generator enabling systematic evaluations of deep-learning architec- tures,”arXiv preprint arXiv:1911.09925, vol. 3, no. 25, pp. 15–17, 2019

arXiv 1911

Show all 36 references

[9]

Problem sets - hdlbits,

HDLBits, “Problem sets - hdlbits,” https://hdlbits.01xz.net/wiki/ Problem sets, accessed: 2024-11-11

2024
[10]

White paper-investigate the high-level hdl chisel,

F. Heilmann, C. Brugger, and N. Wehn, “White paper-investigate the high-level hdl chisel,”Kaiserslautern, Germany, 2013

2013
[11]

Verilogcoder: Autonomous verilog coding agents with graph-based planning and abstract syntax tree (ast)- based waveform tracing tool,

C.-T. Ho, H. Ren, and B. Khailany, “Verilogcoder: Autonomous verilog coding agents with graph-based planning and abstract syntax tree (ast)- based waveform tracing tool,”arXiv preprint arXiv:2408.08927, 2024

2024 arXiv
[12]

Reusability is firrtl ground: Hardware construction languages, compiler frameworks, and transformations,

A. Izraelevitz, J. Koenig, P. Li, R. Lin, A. Wang, A. Magyar, D. Kim, C. Schmidt, C. Markley, J. Lawson, and J. Bachrach, “Reusability is firrtl ground: Hardware construction languages, compiler frameworks, and transformations,” in2017 IEEE/ACM International Conference on Comp...

2017
[13]

A comparative study of chisel for fpga design,

P. Lennon and R. Gahan, “A comparative study of chisel for fpga design,” in2018 29th Irish Signals and Systems Conference (ISSC). IEEE, 2018, pp. 1–6

2018
[14]

Specification for the firrtl language,

P. S. Li, A. M. Izraelevitz, and J. Bachrach, “Specification for the firrtl language,” EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2016-9, Feb 2016. [Online]. Available: http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-9.html

2016
[15]

Verilogeval: Evaluating large language models for verilog code generation,

M. Liu, N. Pinckney, B. Khailany, and H. Ren, “Verilogeval: Evaluating large language models for verilog code generation,” in2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD). IEEE, 2023, pp. 1–8

2023
[16]

Rtl- coder: Fully open-source and efficient llm-assisted rtl code generation technique,

S. Liu, W. Fang, Y . Lu, J. Wang, Q. Zhang, H. Zhang, and Z. Xie, “Rtl- coder: Fully open-source and efficient llm-assisted rtl code generation technique,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024

2024
[17]

Openllm-rtl: Open dataset and benchmark for llm-aided design rtl generation(invited),

S. Liu, Y . Lu, W. Fang, M. Li, and Z. Xie, “Openllm-rtl: Open dataset and benchmark for llm-aided design rtl generation(invited),” in Proceedings of 2024 IEEE/ACM International Conference on Computer- Aided Design (ICCAD). ACM, 2024

2024
[18]

Chatchisel: Enabling agile hardware design with large language models,

T. Liu, Q. Tian, J. Ye, L. Fu, S. Su, J. Li, G.-W. Wan, L. Zhang, S.- Z. Wong, X. Wanget al., “Chatchisel: Enabling agile hardware design with large language models,” in2024 2nd International Symposium of Electronics Design Automation (ISEDA). IEEE, 2024, pp. 710–716

2024
[19]

Rtllm: An open-source benchmark for design rtl generation with large language model,

Y . Lu, S. Liu, Q. Zhang, and Z. Xie, “Rtllm: An open-source benchmark for design rtl generation with large language model,” in2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 2024, pp. 722–727

2024
[20]

Dave: Deriving automatically verilog from english,

H. Pearce, B. Tan, and R. Karri, “Dave: Deriving automatically verilog from english,” inProceedings of the 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020, pp. 27–32

2020
[21]

Revisiting verilogeval: Newer llms, in-context learning, and specification-to-rtl tasks,

N. Pinckney, C. Batten, M. Liu, H. Ren, and B. Khailany, “Revisiting verilogeval: Newer llms, in-context learning, and specification-to-rtl tasks,”arXiv preprint arXiv:2408.11053, 2024

2024 arXiv
[22]

Schoeberl,Digital design with chisel

M. Schoeberl,Digital design with chisel. Kindle Direct Publishing, 2019

2019
[23]

Re- flexion: Language agents with verbal reinforcement learning,

N. Shinn, F. Cassano, A. Gopinath, K. Narasimhan, and S. Yao, “Re- flexion: Language agents with verbal reinforcement learning,”Advances in Neural Information Processing Systems, vol. 36, 2024

2024
[24]

Benchmarking large language models for auto- mated verilog rtl code generation,

S. Thakur, B. Ahmad, Z. Fan, H. Pearce, B. Tan, R. Karri, B. Dolan- Gavitt, and S. Garg, “Benchmarking large language models for auto- mated verilog rtl code generation,” in2023 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2023, pp. 1–6

2023
[25]

Verigen: A large language model for verilog code generation,

S. Thakur, B. Ahmad, H. Pearce, B. Tan, B. Dolan-Gavitt, R. Karri, and S. Garg, “Verigen: A large language model for verilog code generation,” ACM Transactions on Design Automation of Electronic Systems, vol. 29, no. 3, pp. 1–31, 2024

2024
[26]

Au- tochip: Automating hdl generation using llm feedback,

S. Thakur, J. Blocklove, H. Pearce, B. Tan, S. Garg, and R. Karri, “Au- tochip: Automating hdl generation using llm feedback,” inProceedings of the 61st Design Automation Conference (DAC), San Francisco, CA, 2024

2024
[27]

Rtlfixer: Automatically fixing rtl syntax errors with large language model,

Y . Tsai, M. Liu, and H. Ren, “Rtlfixer: Automatically fixing rtl syntax errors with large language model,” inProceedings of the 61st ACM/IEEE Design Automation Conference, 2024, pp. 1–6

2024
[28]

Chatcpu: An agile cpu design & verification platform with llm,

X. Wang, G.-W. Wan, S.-Z. Wong, L. Zhang, T. Liu, Q. Tian, and J. Ye, “Chatcpu: An agile cpu design & verification platform with llm,” in61st ACM/IEEE Design Automation Conference (DAC’24), 2024, p. 6

2024
[29]

Chain-of-thought prompting elicits reasoning in large language models,

J. Wei, X. Wang, D. Schuurmans, M. Bosma, F. Xia, E. Chi, Q. V . Le, D. Zhouet al., “Chain-of-thought prompting elicits reasoning in large language models,”Advances in neural information processing systems, vol. 35, pp. 24 824–24 837, 2022

2022
[30]

Vgv: Verilog generation using visual capabilities of multi-modal large language models,

S.-Z. Wong, G.-W. Wan, D. Liu, and X. Wang, “Vgv: Verilog generation using visual capabilities of multi-modal large language models,” in2024 IEEE LLM Aided Design Workshop (LAD). IEEE, 2024, pp. 1–5

2024
[31]

Towards developing high performance risc-v processors using agile methodology,

Y . Xu, Z. Yu, D. Tang, G. Chen, L. Chen, L. Gou, Y . Jin, Q. Li, X. Li, Z. Liet al., “Towards developing high performance risc-v processors using agile methodology,” in2022 55th IEEE/ACM International Sym- posium on Microarchitecture (MICRO). IEEE, 2022, pp. 1178–1199

2022
[32]

React: Synergizing reasoning and acting in language models,

S. Yao, J. Zhao, D. Yu, N. Du, I. Shafran, K. Narasimhan, and Y . Cao, “React: Synergizing reasoning and acting in language models,”arXiv preprint arXiv:2210.03629, 2022

2022 arXiv
[33]

Hdldebugger: Streamlining hdl debugging with large language models,

X. Yao, H. Li, T. H. Chan, W. Xiao, M. Yuan, Y . Huang, L. Chen, and B. Yu, “Hdldebugger: Streamlining hdl debugging with large language models,”arXiv preprint arXiv:2403.11671, 2024

2024 arXiv
[34]

Rtlrewriter: Methodologies for large models aided rtl code optimization,

X. Yao, Y . Wang, X. Li, Y . Lian, R. Chen, L. Chen, M. Yuan, H. Xu, and B. Yu, “Rtlrewriter: Methodologies for large models aided rtl code optimization,”arXiv preprint arXiv:2409.11414, 2024

2024 arXiv
[35]

Mg-verilog: Multi- grained dataset towards enhanced llm-assisted verilog generation,

Y . Zhang, Z. Yu, Y . Fu, C. Wan, and Y . C. Lin, “Mg-verilog: Multi- grained dataset towards enhanced llm-assisted verilog generation,” in 2024 IEEE LLM Aided Design Workshop (LAD). IEEE, 2024, pp. 1–5

2024
[36]

Sonicboom: The 3rd generation berkeley out-of-order machine,

J. Zhao, B. Korpan, A. Gonzalez, and K. Asanovic, “Sonicboom: The 3rd generation berkeley out-of-order machine,” May 2020

2020

Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.

[1] [1]

The rocket chip generator,

K. Asanovic, R. Avizienis, J. Bachrach, S. Beamer, D. Biancolin, C. Celio, H. Cook, D. Dabbelt, J. Hauser, A. Izraelevitzet al., “The rocket chip generator,”EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2016-17, vol. 4, pp. 6–2, 2016

work page 2016

[2] [2]

Chisel: constructing hardware in a scala embedded language,

J. Bachrach, H. V o, B. Richards, Y . Lee, A. Waterman, R. Avi ˇzienis, J. Wawrzynek, and K. Asanovi ´c, “Chisel: constructing hardware in a scala embedded language,” inProceedings of the 49th Annual Design Automation Conference, 2012, pp. 1216–1225

work page 2012

[3] [3]

Chip-chat: Chal- lenges and opportunities in conversational hardware design,

J. Blocklove, S. Garg, R. Karri, and H. Pearce, “Chip-chat: Chal- lenges and opportunities in conversational hardware design,” in2023 ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD). IEEE, 2023, pp. 1–6

2023

[4] [4]

Chipgpt: How far are we from natural language hardware design,

K. Chang, Y . Wang, H. Ren, M. Wang, S. Liang, Y . Han, H. Li, and X. Li, “Chipgpt: How far are we from natural language hardware design,” arXiv preprint arXiv:2305.14019, 2023

arXiv 2023

[5] [5]

Evaluating large language models trained on code,

M. Chen, J. Tworek, H. Jun, Q. Yuan, H. P. D. O. Pinto, J. Kaplan, H. Edwards, Y . Burda, N. Joseph, G. Brockmanet al., “Evaluating large language models trained on code,”arXiv preprint arXiv:2107.03374, 2021

arXiv 2021

[6] [6]

Magma-si: A matrix accelerator generator,

M.-S. Contributors, “Magma-si: A matrix accelerator generator,” https: //github.com/merledu/magma-si, 2024, accessed: 2024-11-15

work page 2024

[7] [7]

A survey on in-context learning,

Q. Dong, L. Li, D. Dai, C. Zheng, J. Ma, R. Li, H. Xia, J. Xu, Z. Wu, T. Liuet al., “A survey on in-context learning,”arXiv preprint arXiv:2301.00234, 2022

arXiv 2022

[8] [8]

Gemmini: An agile systolic array generator enabling systematic evaluations of deep-learning architec- tures,

H. Genc, A. Haj-Ali, V . Iyer, A. Amid, H. Mao, J. Wright, C. Schmidt, J. Zhao, A. Ou, M. Banisteret al., “Gemmini: An agile systolic array generator enabling systematic evaluations of deep-learning architec- tures,”arXiv preprint arXiv:1911.09925, vol. 3, no. 25, pp. 15–17, 2019

arXiv 1911