Pith. sign in

REVIEW 4 major objections 4 minor 40 references

Solving Boolean Satisfiability Problems Using A Hypergraph-based Probabilistic Computer

T0 review · 4 major / 4 minor · reviewed 2026-08-07 · deepseek-v4-flash

Pith's one-line read A direct clause-to-hyperedge mapping makes the ground state of a probabilistic computer exactly the satisfying assignments of a 3-SAT formula, reaching 99% success on uf20-01 where a conventional solver reaches 1%.

desk verdict The energy mapping is correct but not new; the headline performance comparison is not yet interpretable because annealing parameters and the uf100-430 evidence are missing. read the letter →

arxiv 2505.22215 v2 pith:XSV4BHXQ submitted 2025-05-28 physics.comp-ph

classification physics.comp-ph
keywords Booleansatisfiability3-SAThypergraphprobabilisticcomputingp-bitsinvertiblelogicsimulatedannealingSTT-MRAM
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper argues that 3-SAT formulas can be solved more efficiently by a probabilistic computer when each clause is translated directly into one hyperedge, rather than decomposed into a network of pairwise invertible logic gates. The mapping encodes a positive literal $x_i$ as $(1-x_i)$ and a negated literal $\neg x_i$ as $x_i$, so the product of the three encoded literals in a clause is 1 exactly when that clause is false. Summing these products over all clauses gives an energy that is zero precisely for satisfying assignments, which means the Boltzmann-sampled system's ground state is the solution set. On the uf20-01 benchmark instance this reduces the vertex count from 112 to 20, shrinks the solution space from $2^{112}$ to $2^{20}$, and raises the success rate from 1% to 99%; the abstract reports about 77.6% average success on uf100-430 instances where the conventional solver gets 0%.

What carries the argument

The load-bearing construction is the clause-to-hyperedge energy map. Each clause $(\ell_1 \vee \ell_2 \vee \ell_3)$ is replaced by the product of its encoded literals $e_1 e_2 e_3$, with $e_i = 1-x_i$ for a positive literal and $e_i = x_i$ for a negated literal; the product is 1 only when all three literals are false. Summing these products yields $H_{\text{total}}$, a three-body Hamiltonian whose ground state at 0 is exactly the satisfying assignments. This object carries the argument because it converts SAT into energy minimization without logic synthesis, and when expanded it produces the cubic, quadratic, and linear coefficients that specify the hypergraph's hyperedges, pairwise interactions, and biases.

What would settle it

Re-run the conventional SUG solver on uf20-01 and uf100-430 with its own tuned annealing schedule, reporting $\alpha_0$ and $\beta$, and compare success rates and final energies with the reported 1%/0% and about 9.12. If an alternative schedule lifts the baseline toward the hypergraph solver's 99%/77.6% and near-0.24 energies, the claimed advantage is an artifact of schedule choice rather than of the direct mapping.

Watch

Extended reading notes

Core claim

The paper's central claim is that a 3-SAT formula in conjunctive normal form can be mapped losslessly to a hypergraph, with one vertex per variable and one hyperedge per clause. The literal encoding $x_i \to (1-x_i)$ and $\neg x_i \to x_i$ turns each clause into a product that equals 1 only when all three of its literals are false, so the total Hamiltonian $H_{\text{total}} = \sum_i H_i$ is nonnegative and vanishes exactly on satisfying assignments. This makes the ground state of the probabilistic system coincide with the solution set, while the conventional simple-undirected-graph (SUG) logic-synthesis approach creates an auxiliary vertex for each clause and stacks mismatched energy levels into a rugged landscape. The paper reports that on uf20-01 the hypergraph solver succeeds 99 times out of 100 trials with an average of 18.92 annealing cycles, versus 1% for the optimized SUG solver, and on uf100-430 it reports about 77.6% average success and average minimum energy near 0.24, against 0% and about 9.12 for the baseline.

Load-bearing premise

The headline performance comparison rests on the assumption that running both solvers under the same simulated-annealing schedule is a fair test, even though the baseline network has 112 vertices versus the hypergraph solver's 20 and the annealing parameters $\alpha_0$ and $\beta$ in Eq. (6) are not reported.

Editorial extensions

If this is right

  • On uf20-01 the hypergraph solver reaches a 99% success rate over 100 trials with an average convergence of 18.92 annealing cycles, versus 1% for the optimized SUG solver.
  • For uf100-430 instances the direct mapping cuts the vertex count from 631 to 100 and the edge count from roughly 2,423 to about 1,013, shrinking the explored space to the original variables only.
  • Because the total energy counts unsatisfied clauses, a configuration satisfies the formula exactly when $H_{\text{total}} = 0$, so the ground state of the annealed Boltzmann sampler is the solution set.
  • The same clause-to-hyperedge construction extends to k-SAT by replacing three-literal products with k-literal products, giving a scalable framework for higher-order satisfiability.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Since $H_{\text{total}}$ is literally the number of unsatisfied clauses, the same energy function also solves Max-SAT (and approximate Max-SAT under sampling), a consequence the paper does not state explicitly.
  • The near-uniform occupancy of the 28 satisfying assignments on the custom 8-variable instance hints that the hypergraph's Boltzmann distribution could be used for solution counting or near-uniform sampling, which the paper does not explore.
  • A fairer performance benchmark would tune each solver's annealing schedule separately and report time-to-solution; the reported 'identical conditions' comparison may understate the conventional solver's capability.
  • For hardware, the proposed CMOS AND-gate implementation of three-body interactions suggests a direct compiler from CNF formulas to p-bit circuits, but the 77.6% success rate on uf100-430 would need re-testing under device-to-device variability in the STT-MRAM p-bit sigmoid.
Share X Bluesky LinkedIn Reddit HN

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 4 minor

Summary. This paper proposes a hypergraph-based probabilistic computing solver for 3-SAT. Each clause is mapped to a product of encoded literals; summing these products yields a nonnegative integer energy whose zero level corresponds exactly to satisfying assignments. The authors implement this mapping in simulations using a sigmoidal STT-MRAM p-bit model, compare with an optimized SUG-based invertible-logic solver on a custom 8-variable instance and on SATLIB uf20-01, and claim a 99% versus 1% success rate. The abstract further claims substantial scalability gains on uf100-430 instances.

Significance. The direct-clause-to-hyperedge mapping is conceptually clean and parameter-free, and the energy-landscape analysis (fewer vertices, shallower landscape) is plausible. If the performance comparison is made fair and reproducible, the method could be a useful alternative to conventional p-bit SAT solvers and extends naturally to k-SAT. The strongest parts are the explicit zero-ground-state construction and the device-level p-bit characterization. The main weakness is that the headline numerical comparison is not yet interpretable because the annealing protocol is underspecified and the uf100-430 claims are absent from the body.

major comments (4)
  1. [Results D, Fig. 7(c), Eq. (6)] The central quantitative claim, a 99% versus 1% success rate, is presented as obtained under 'identical simulated annealing conditions,' but the schedule parameters alpha0 and beta in Eq. (6) are never reported. This omission is load-bearing because the two energy landscapes have very different scales: the SUG landscape in Fig. 5(a) spans about -48 to 39, while the hypergraph landscape in Fig. 5(d) spans only 0 to 5. A single annealing schedule cannot be simultaneously near-optimal for both landscapes unless it is specially normalized, and the same schedule can artificially freeze one solver or overheat the other. Please report the exact schedule, the number of trials for each solver, and a sensitivity analysis over at least a few alpha0 and beta values.
  2. [Abstract and Results] The abstract's uf100-430 scalability claims (631 to 100 vertices, about 77.6% success, average minimum energy 0.24 versus 9.12, edge count reduction) do not appear anywhere in the body or methods. This is the headline scalability result and cannot be checked for the same schedule-sensitivity issues. The authors should either add a complete uf100-430 benchmarking subsection with the experimental setup and per-instance data or remove the claim from the abstract.
  3. [Results D, Fig. 7(d)] The summary table in Fig. 7(d), which is used to support robustness across multiple uf20-91 instances, is not legible in the supplied text and the numerical entries are not reproduced. Please provide the per-instance counts, success rates, and trial numbers as a proper table, either in the main text or in a supplement.
  4. [Results A, Fig. 2, and Fig. 7(c)] The paper compares solution-space sizes of 2^112 and 2^20, but these count network configurations, not SAT variable assignments. The SUG contains 91 auxiliary nodes and one clamped node in addition to the 20 Boolean variables, so the extra states are not degrees of freedom of the SAT instance. The reduction in vertex count is a real advantage, but the 'theoretically minimal solution space' claim should be phrased as a reduction in network configuration space rather than in the SAT problem's solution space.
minor comments (4)
  1. [Methods, Eq. (5)] The denominator in Eq. (5) should be a sum over all state configurations; the typeset expression is ambiguous. Please check the parentheses and braces.
  2. [Results D] The heading 'uf20-91 problems' is imprecise: SATLIB uf20-91 is a family of instances with 20 variables and 91 clauses, and the specific instance studied is uf20-01. Please use consistent nomenclature.
  3. [Results C] The description of the sigmoidal fitting curve says the cell has a 50% probability of outputting 0 or 1 at V=0; it would be clearer to state explicitly how the measured sigmoid is converted into the sampling probability used in the simulations.
  4. [References] Reference [23] is a duplicate of reference [3]; please remove one.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the hypergraph energy is a definitional penalty encoding and simulated success rates are measured against independent SAT ground truth.

full rationale

Walking the derivation chain: Eqs. (2)-(4) define each clause energy H_i as the product of encoded literals, which equals 1 exactly when that clause is false, so H_total counts unsatisfied clauses. The statement that H_total = 0 iff the formula is satisfied is therefore true by the construction of H, but this is the intended design of an energy encoding rather than a prediction derived from fitted data. No parameter is fit to a subset of SAT outcomes and then renamed as a prediction; the success rates in Figs. 6 and 7 are empirical simulation frequencies of reaching H = 0 on known SATLIB instances, checked against objective satisfiability. Refs. [27] and [29] are self-citations for many-body invertible logic, but the direct 3-SAT-to-hypergraph energy construction is derived in Eqs. (2)-(4) and explicitly inspired by external direct-mapping work [32]; no load-bearing theorem is imported solely from the authors' prior papers. The benchmark comparison under 'identical simulated annealing conditions' with unreported alpha0 and beta is a fairness and reproducibility concern about the quantitative performance margin, not a circularity, because the hypergraph solver's success is not forced by construction: reaching H = 0 still requires stochastic search over assignments. The abstract's uf100-430 result is absent from the body and cannot be checked, but absence of evidence is not an equivalence between input and output. Overall, the central mapping claim is a standard penalty construction and the reported numbers are externally grounded, so no significant circularity is present.

Assumptions & free parameters 2 free parameters · 5 assumptions · 0 invented entities

The mapping itself introduces no fitted parameters: the energy coefficients are expanded from the clause products in Eq. (3). The listed parameters enter the simulation of the device and the annealing schedule, and the axioms are the standard modeling assumptions of p-bit Boltzmann sampling.

free parameters (2)
  • STT-MRAM sigmoidal activation parameters = Not stated in text
    The sigmoidal fit in Fig. 3(c) is used as the p-bit activation function in system-level simulations; the fit coefficients are not given, making the device model irreproducible.
  • Simulated annealing schedule parameters alpha0 and beta = Not stated in text
    Eq. (6) defines the annealing schedule, but the initial value and rate are not reported, yet they directly affect success rates and convergence cycles.
assumptions (5)
  • domain assumption Boltzmann distribution governs the steady-state probabilities of the p-bit network.
    The solver dynamics are assumed to sample according to Eq. (5) with the given energy function, which is a standard statistical-mechanics assumption for p-bit hardware.
  • domain assumption Literal encoding: positive literal xi maps to (1-xi) and negative literal not-xi maps to xi.
    This encoding in Eq. (2) is a design choice that makes each clause's product equal to 1 exactly when the clause is false.
  • standard math The ground state of H_total = 0 is reached if and only if the 3-SAT formula is satisfied.
    This follows algebraically because each clause product is a nonnegative integer and their sum is zero exactly when every clause product is zero.
  • domain assumption STT-MRAM p-bit output probability follows a sigmoidal voltage response.
    The experimentally fitted sigmoid is used as the activation function in simulations, assuming it accurately represents device stochasticity.
  • domain assumption A CMOS AND gate can implement three-body interactions for binary outputs.
    The paper proposes this as a hardware implementation of hyperedges, but it is only a schematic suggestion and is not demonstrated in a working solver.

how reviews work

0 comments
Cite this review

Pith. "Pith review of Solving Boolean Satisfiability Problems Using A Hypergraph-based Probabilistic Computer." pith.science (2026). https://pith.science/paper/XSV4BHXQ

@misc{pith2026250522215,
  author       = {Pith},
  title        = {Pith review of: Solving Boolean Satisfiability Problems Using A Hypergraph-based Probabilistic Computer},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/XSV4BHXQ}},
  note         = {Machine review of arXiv:2505.22215}
}
read the original abstract

Boolean Satisfiability (SAT) problems are critical in fields such as artificial intelligence and cryptography, where efficient solutions are essential. Conventional probabilistic solvers often encounter scalability issues due to complex logic synthesis steps. In this work, we present a novel approach for solving the 3-SAT Boolean satisfiability problem using hypergraph-based probabilistic computers obtained through direct mapping. This method directly translates 3-SAT logical expressions into hypergraph structures, thereby circumventing conventional logic decomposition and synthesis procedures, and offering a more streamlined solver architecture. For representative uf100-430 instances, the proposed approach reduces the node count from 631 to 100 and the edge count from ~2,423 to ~1,013. Under identical simulated annealing conditions, the conventional simple undirected graph (SUG)-based solver achieves a 0% success rate across the tested instances, whereas the hypergraph-based solver attains an average success rate of ~77.6%. In addition, the hypergraph-based method reaches an average minimum energy of ~0.24, close to the theoretical ground state, while the SUG-based architecture remains trapped at substantially higher energy levels (~9.12 on average). The direct hypergraph mapping can further be extended to k-SAT formulations, providing a scalable framework for more complex satisfiability problems in probabilistic computing.

Figures

Figures reproduced from arXiv: 2505.22215 by the authors.

Figure 2
Figure 2. (a) Example small-scale 3-SAT problem with 5 literals and 3 clauses. (b) Hypergraph representation of the 3- SAT problem after direct mapping. Hyperedges are illustrated by three colored regions: red, yellow and blue, respectively. Pairwise interactions between vertices are depicted by black lines. The strength of hyperedges and pairwise interactions are indicated by the numbers adjacent to the regions and lines. Lo… view at source ↗
Figure 3
Figure 3. (a) Cross-sectional TEM image of a Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) structure. The labeled layers include the Top Electrode (TE), MgO barrier, CoFeB free and fixed layers, Co/Pt multilayers, Ru spacer, and Bottom Electrode (BE). (b) Voltage-dependent switching behavior of the STT-MRAM. (c) Output probability versus voltage characteristics of the magnetic tunnel junction, presenting exper… view at source ↗
Figure 4
Figure 4. (a) Custom-defined 3-SAT problem utilized for evaluating solver performance, with clauses interconnected through logical conjunction. (b) Graphical representation and (c) node-interaction distribution of a conventional 3-SAT solver constructed using the logic synthesis method based on optimized SUGs. (d) Direct hypergraph-based mapping for the same 3-SAT problem. For better visualization, hyperedges for the 12 claus… view at source ↗
Figures from the paper (3 more)
Figure 5
Figure 5. Figure 5: Energy landscapes of 3-SAT solvers based on (a) the logic synthesis approach and (b) the hypergraph with direct mapping. Hamiltonian distributions of these two solvers based on (c) the logic synthesis approach and (d) the hypergraph with direct mapping. variables (Fig.…
Figure 6
Figure 6. Figure 6: Probability distributions of the solvers based on(a) the logic synthesis approach and (b) the hypergraph with direct mapping. Further simulated experiments comparing the two solvers revealed distinct probability distributions for the given 8-literal and 12-clause 3-SAT…
Figure 7
Figure 7. Figure 7: 100 simulated experiments were conducted on the uf20-01 3-SAT instance from the SATLIB benchmark using the hypergraph-based solver under simulated annealing. (a) The evolution of the 20-vertex state configurations [x1, x2, x3, …, x20] over annealing cycles. (b) corresp…

Discussion (0). Sign in to comment.

Reference graph

Works this paper leans on

40 extracted references · 36 canonical work pages

  1. [1]

    Singh, N. S. et al. CMOS plus stochastic nanomagnets enabling heterogeneous computers for probabilistic inference and learning. Nat. Commun. 15, 2685 (2024)

  2. [2]

    Chowdhury, S. et al. A full-stack view of probabilistic computing with p-bits: devices, architectures and algorithms. IEEE J. Explor . Solid-State Comput. Devices Circuits 1–1 (2023) doi:10.1109/JXCDC.2023.3256981

  3. [4]

    Daniel, J. et al. Experimental demonstration of an on-chip p-bit core based on stochastic magnetic tunnel junctions and 2D MoS2 transistors. Nat. Commun. 15, 4098 (2024)

  4. [5]

    Cai, B. et al. Unconventional computing based on magnetic tunnel junction. Appl. Phys. A 129, 236 (2023)

  5. [6]

    Finocchio, G. et al. Roadmap for unconventional computing with nanotechnology. Nano Futur. 8, 012001 (2024)

  6. [7]

    & Datta, S

    Kaiser, J. & Datta, S. Probabilistic computing with p-bits. Appl. Phys. Lett. 119, 150503 (2021)

  7. [8]

    Cai, F. et al. Power-efficient combinatorial optimization using intrinsic noise in memristor Hopfield neural networks. Nat. Electron. 3, 409–418 (2020)

  8. [9]

    Mohseni, N., McMahon, P. L. & Byrnes, T. Ising machines as hardware solvers of combinatorial optimization problems. Nat. Rev. Phys. 4, 363–379 (2022)

Show all 40 references
  1. [10]

    & Salahuddin, S

    Patel, S., Canoza, P. & Salahuddin, S. Logically synthesized and hardware-accelerated restricted Boltzmann machines for combinatorial optimization and integer factorization. Nat. Electron. 5, 92–101 (2022)

  2. [11]

    & Camsari, K

    Lee, K., Chowdhury, S. & Camsari, K. Y . Noise-augmented Chaotic Ising Machines for Combinatorial Optimization and Sampling. Preprint at http://arxiv.org/abs/2408.04744 (2024)

  3. [12]

    Y ., Sutton, B

    Camsari, K. Y ., Sutton, B. M. & Datta, S. p-bits for probabilistic spin logic. Appl. Phys. Rev. 6, 011305 (2019)

  4. [13]

    Y ., Faria, R., Sutton, B

    Camsari, K. Y ., Faria, R., Sutton, B. M. & Datta, S. Stochastic p-bits for invertible logic. Phys. Rev. X 7, 031014 (2017)

  5. [14]

    Z., Sutton, B

    Pervaiz, A. Z., Sutton, B. M., Ghantasala, L. A. & Camsari, K. Y . Weighted $ p $-Bits for FPGA Implementation of Probabilistic Circuits. IEEE Trans. Neural Netw. Learn. Syst. 30, 1920–1926 (2018)

  6. [15]

    Z., Ghantasala, L

    Pervaiz, A. Z., Ghantasala, L. A., Camsari, K. Y . & Datta, S. Hardware emulation of stochastic p-bits for invertible logic. Sci. Rep. 7, 10994 (2017)

  7. [16]

    Bybee, C. et al. Efficient optimization with higher-order ising machines. Nat. Commun. 14, 6033 (2023)

  8. [17]

    & Roy, K

    Shim, Y ., Jaiswal, A. & Roy, K. Ising computation based combinatorial optimization using spin- Hall effect (SHE) induced stochastic magnetization reversal. J. Appl. Phys. 121, 193902 (2017)

  9. [18]

    Kim, J. et al. Fully CMOS‐Based p‐Bits with a Bistable Resistor for Probabilistic Computing. Adv. Funct. Mater. 34, 2307935 (2024)

  10. [19]

    Vardi, M. Y . Boolean satisfiability: theory and engineering. Commun. ACM 57, 5–5 (2014)

  11. [20]

    L., Majercik, S

    Littman, M. L., Majercik, S. M. & Pitassi, T. Stochastic Boolean Satisfiability. J. Autom. Reason. 27, 251–296 (2001)

  12. [21]

    Marques-Silva, J. P. & Sakallah, K. A. Boolean satisfiability in electronic design automation. in Proceedings of the 37th conference on Design automation - DAC ’00 675–680 (ACM Press, Los Angeles, California, United States, 2000). doi:10.1145/337292.337611

  13. [22]

    & Zaikin, O

    Semenov, A. & Zaikin, O. Algorithm for finding partitionings of hard variants of boolean satisfiability problem with application to inversion of some cryptographic functions. SpringerPlus 5, 554 (2016)

  14. [23]

    Aadit, N. A. et al. Massively parallel probabilistic computing with sparse Ising machines. Nat. Electron. 5, 460–468 (2022)

  15. [24]

    Aadit, N. A. et al. Computing with invertible logic: Combinatorial optimization with probabilistic bits. in 2021 IEEE International Electron Devices Meeting (IEDM) 40–3 (IEEE, 2021)

  16. [25]

    Grimaldi, A. et al. Spintronics-compatible Approach to Solving Maximum-Satisfiability Problems with Probabilistic Computing, Invertible Logic, and Parallel Tempering. Phys. Rev. Appl. 17, 024052 (2022)

  17. [26]

    Onizawa, N. et al. A Design Framework for Invertible Logic. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 40, 655–665 (2021)

  18. [27]

    & Liang, G

    He, Y ., Luo, S., Fang, C. & Liang, G. Direct design of ground-state probabilistic logic using many-body interactions for probabilistic computing. Sci. Rep. 14, 15076 (2024)

  19. [28]

    Pedretti, G. et al. Solving Boolean satisfiability problems with resistive content addressable memories. Npj Unconv. Comput. 2, 7 (2025)

  20. [29]

    & Liang, G

    He, Y ., Fang, C., Luo, S. & Liang, G. Many-Body Effects-Based Invertible Logic with a Simple Energy Landscape and High Accuracy. IEEE J. Explor. Solid-State Comput. Devices Circuits 1–1 (2023) doi:10.1109/JXCDC.2023.3320230

  21. [30]

    Bashar, M. K. & Shukla, N. Designing Ising machines with higher order spin interactions and their application in solving combinatorial optimization. Sci. Rep. 13, 9558 (2023)

  22. [31]

    K., Mallick, A., Ghosh, A

    Bashar, M. K., Mallick, A., Ghosh, A. W. & Shukla, N. Dynamical System-Based Computational Models for Solving Combinatorial Optimization on Hypergraphs. IEEE J. Explor. Solid-State Comput. Devices Circuits 9, 21–28 (2023)

  23. [32]

    Su, Y ., Kim, T. T.-H. & Kim, B. A Reconfigurable CMOS Ising Machine With Three-Body Spin Interactions for Solving Boolean Satisfiability With Direct Mapping. IEEE Solid-State Circuits Lett. 6, 221–224 (2023)

  24. [33]

    Grimaldi, A., Raimondo, E., Giordano, A., Çamsarı, K. Y . & Finocchio, G. A Comparison of Energy Minimization Algorithms for Solving Max-Sat Problem with Probabilistic Ising Machines. in 2023 IEEE 23rd International Conference on Nanotechnology (NANO) 698–702 (IEEE, Jeju City,...

  25. [34]

    C., Onizawa, N., Meyer, B

    Smithson, S. C., Onizawa, N., Meyer, B. H., Gross, W. J. & Hanyu, T. Efficient CMOS invertible logic using stochastic computing. IEEE Trans. Circuits Syst. Regul. Pap. 66, 2263– 2274 (2019)

  26. [35]

    Y ., Salahuddin, S

    Camsari, K. Y ., Salahuddin, S. & Datta, S. Implementing p-bits With Embedded MTJ. IEEE Electron Device Lett. 38, 1767–1770 (2017)

  27. [36]

    Safranski, C. et al. Demonstration of Nanosecond Operation in Stochastic Magnetic Tunnel Junctions. Nano Lett. 21, 2040–2045 (2021)

  28. [37]

    Woo, K. S. et al. Probabilistic computing using Cu0.1Te0.9/HfO2/Pt diffusive memristors. Nat. Commun. 13, 5762 (2022)

  29. [38]

    Wang, K. et al. Threshold switching memristor-based stochastic neurons for probabilistic computing. Mater. Horiz. 8, 619–629 (2021)

  30. [39]

    A., Mohseni, M

    Aadit, N. A., Mohseni, M. & Camsari, K. Y . Accelerating Adaptive Parallel Tempering with FPGA-based p-bits. in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 1–2 (IEEE, Kyoto, Japan, 2023). doi:10.23919/VLSITechnologyandCir57934.2023.10185207

  31. [40]

    & Liang, G

    Luo, S., He, Y ., Cai, B., Gong, X. & Liang, G. Probabilistic-Bits Based on Ferroelectric Field- Effect Transistors for Probabilistic Computing. IEEE Electron Device Lett. 44, 1356–1359 (2023)

  32. [41]

    Wu, M.-H. et al. Compact Probabilistic Poisson Neuron Based on Back-Hopping Oscillation in STT-MRAM for All-Spin Deep Spiking Neural Network. in 2020 IEEE Symposium on VLSI Technology 1–2 (IEEE, Honolulu, HI, USA, 2020). doi:10.1109/VLSITechnology18217.2020.9265033

Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.