Pith. sign in

REVIEW 4 major objections 7 minor 36 references

CrossNAS: A Cross-Layer Neural Architecture Search Framework for PIM Systems

T0 review · 4 major / 7 minor · reviewed 2026-08-07 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗

Pith's one-line read CrossNAS claims that jointly searching neural architecture, quantization, and processing-in-memory circuit parameters with a single-path one-shot supernet and an evolutionary algorithm beats prior PIM-oriented NAS methods in both accuracy…

desk verdict CrossNAS is a plausible and clearly written engineering contribution, but its headline accuracy numbers are selected on the test set, so the empirical claims are not yet validated. read the letter →

arxiv 2505.22868 v1 pith:UURCC3MW submitted 2025-05-28 cs.ET cs.ARcs.LG

Md Hasibul Amin , Mohammadreza Mohammadi , Jason D. Bakos , Ramtin Zand This is my paper
classification cs.ETcs.ARcs.LG
keywords processing-in-memoryneuralarchitecturesearchweightsharingsingle-pathone-shotevolutionaryalgorithmmixed-precisionquantizationcrossbarenergy-delayproduct
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Processing-in-memory (PIM) hardware performs computation inside memory arrays, which can save power and latency but makes model deployment sensitive to circuit-level choices. The paper proposes CrossNAS, a neural architecture search framework that explores one cross-layer search space covering neural block types, channel counts, layer-wise weight and activation bit widths, crossbar size, and ADC/DAC precision. Its central claim is that this combined search finds models that are more accurate and more energy-efficient than earlier PIM-oriented NAS methods without longer search: on CIFAR-10 it reports 91.27% accuracy with a 0.28 mJ·ms energy-delay product in about six hours, versus 89.2% accuracy and 1.67 mJ·ms for the best prior accuracy-optimized approach. A sympathetic reader would care because the result suggests that searching hardware and network together, rather than tuning one after the other, is the right way to design for analog accelerators.

What carries the argument

The load-bearing mechanism is the two-stage single-path one-shot supernet: an over-parameterized network in which each position may take any block type, channel count, or bit precision from the search space, trained by uniformly sampling one architecture per step so every subnet's weights are optimized in expectation. Subnet candidates inherit these weights during search, which removes retraining from the inner loop; the multi-objective fitness function above is what couples network choice to hardware cost. The cross-layer search space itself—three block types, 1–8 blocks, 32–128 channels, 5/7/9-bit weights and activations, crossbar sizes 32–256, 4/6/8/10-bit ADC, and 1/2-bit DAC—is the object that makes the co-design claim concrete: it is the first PIM NAS space in this line of work to vary block type and channel count along with circuit-level parameters.

What would settle it

Retrain a sample of subnets from a completed CrossNAS search—including the reported best and several mid-ranked ones—from scratch to convergence, then compare their final accuracies with the inherited-weight scores used during search. If the ordering changes materially, or if a mid-ranked subnet beats the selected model, the search's ranking premise is violated and the reported advantage is not attributable to the search itself.

Watch

Extended reading notes

Core claim

The discovery, on the paper's own terms, is that the single-path one-shot weight-sharing recipe—train one over-parameterized supernet, then evaluate subnets with inherited weights—transfers cleanly from digital neural architecture search to PIM co-design. The framework first trains a supernet whose blocks can be any of three convolutional building blocks at sampled depths, channel counts, and layer positions; an evolutionary algorithm then ranks subnets with a fitness function $\mathrm{FF}=w_{\mathrm{acc}}\cdot \mathrm{accuracy}-(1-w_{\mathrm{acc}})\cdot \mathrm{EDP}_{\mathrm{norm}}$, using a PIM simulator for energy and latency. The best architecture is turned into a mixed-precision quantization supernet, and a second evolutionary pass co-selects per-layer weight and activation bit widths together with crossbar size and ADC/DAC resolutions. Because subnets inherit weights instead of being retrained, the search runs in hours; because the fitness function includes an energy-delay term, the selected architectures expose a systematic accuracy–EDP trade-off. The headline empirical result is that CrossNAS outperforms earlier PIM NAS frameworks on CIFAR-10 in both objectives.

Load-bearing premise

The whole method assumes that the accuracy a candidate gets from borrowed supernet weights, without any retraining, ranks candidates the same way fully trained accuracy would.

Editorial extensions

If this is right

  • If inherited-weight ranking holds up, PIM co-design no longer needs per-candidate training; the same supernet can be searched for many different accuracy–EDP trade-offs by changing $w_{\mathrm{acc}}$ and re-running only the evolutionary pass.
  • The fitness function's trade-off curve gives designers a concrete way to target a hardware budget: a high $w_{\mathrm{acc}}$ yields about 91% accuracy at roughly six times lower EDP than the previous accuracy-optimized baseline, while $w_{\mathrm{acc}}=0.8$ yields about 88% accuracy at roughly a quarter of that EDP.
  • Selected models show structural regularities—early downsampling blocks and larger crossbars with 8-bit ADCs are preferred under EDP optimization—that could be used as heuristics or priors for future PIM-aware network design.
  • On CIFAR-100, the accuracy-optimized configuration improves on two standard network baselines but falls short of a deeper residual network; the paper attributes this to the 128-channel cap in its search space.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Editorial inference: the same two-stage supernet recipe could be applied to other emerging memory technologies if the simulator exposed device-level knobs such as conductance variation, retention, or endurance; nothing in the method is tied to one specific device model.
  • Editorial inference: the paper does not report a rank-correlation check between inherited-weight accuracy and fully trained accuracy, so fully retraining the top few and a few mid-ranked candidates from a completed search would test whether the approximate scores are trustworthy.
  • Editorial inference: the observed preference for 256-by-256 crossbars under EDP optimization may reflect that larger crossbars amortize peripheral ADC/DAC costs; testing on a different tile topology would show whether that preference is a general design rule or a simulator-specific outcome.
Share X Bluesky LinkedIn Reddit HN

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 7 minor

Summary. The paper proposes CrossNAS, a neural architecture search framework for processing-in-memory (PIM) systems. CrossNAS combines single-path one-shot weight sharing with evolutionary search over a cross-layer space spanning neural network block types (VGG, MVGG, RES), number of blocks (1–8), output channels (32/64/128), weight and activation bit widths (5/7/9), crossbar size (32–256), and ADC/DAC precision. The search is guided by a fitness function that balances accuracy (estimated from inherited supernet weights) against a normalized energy-delay product (EDP) computed with the MNSIM 2.0 simulator. The authors report accuracy and EDP improvements over prior PIM-oriented NAS methods and standard CNNs on CIFAR-10 and CIFAR-100, with search times of 5–6 hours.

Significance. If the empirical results were properly validated, the contribution would be significant: applying single-path one-shot NAS to PIM co-exploration with a richer search space than prior work, and demonstrating an accuracy–EDP trade-off on two benchmarks. The paper's main strength is the breadth of the search space and the clear exposition of the two-stage search procedure. However, the empirical validation as presented is compromised by test-set leakage in the search loop, lack of repeated trials, and a post-hoc search-space modification for CIFAR-100. These issues make the reported superiority over prior methods not credibly substantiated. The framework itself is plausible, but the load-bearing empirical claims need substantial revision before the paper can be accepted.

major comments (4)
  1. [Algorithm 1; §3.1–3.3; Tables 2–4] The reported accuracies are selected on the test set, not merely evaluated on it. Algorithm 1 takes 'test data' as input and line 3 computes the fitness function from the test set; Eq. (3) explicitly maximizes FF_test, and Section 3.2 states that subnet accuracy is assessed by inference on the inherited weights. After the search, Tables 2–4 report accuracy on the same CIFAR-10/CIFAR-100 test sets. This is test-set leakage: the evolutionary search uses test accuracy to rank candidates, so the reported numbers reflect selection on the test set and are not unbiased estimates of generalization. A held-out validation split must be used during search, with the test set used only once for final evaluation. This flaw is load-bearing because it invalidates the headline comparison to Gibbon, NACIM, UAE, and NAS4RRAM.
  2. [§4.2, Tables 2–4] The evolutionary search is stochastic, but the paper reports a single run per configuration with no seed averaging, variance, or confidence intervals. For example, the 91.27% versus 89.2% accuracy difference over Gibbon in Table 2 could be within run-to-run noise given the random initialization and mutation/crossover operations. Please report results over at least 3–5 independent search runs (or, if the search is deterministic, state so explicitly and justify).
  3. [§4.4, Table 1, Fig. 6] The CIFAR-100 experiments introduce a post-hoc modification not present in the declared search space: 'a stride of 2 is used in the first 3×3 and 1×1 conv layers of the RES block when optimizing the models for CIFAR-100' (Section 4.4). Table 1 lists only block type, number of blocks, and channel count as architectural search dimensions; stride is not among them. If stride is part of the design space, it should be included in Table 1 and searched; if it is a manual intervention, it changes the search space and makes the CIFAR-100 results not directly comparable to the CIFAR-10 results or to prior methods. This is a load-bearing inconsistency because it calls into question the claim that CrossNAS automatically discovers optimal architectures for CIFAR-100.
  4. [§3.1 (Eq. (2)), §3.2] The entire search relies on the assumption that subnet accuracies computed from inherited supernet weights reliably rank candidate architectures and quantization schemes. Section 3.2 states that 'the accuracy of each subnet—obtained using the inherited supernet weights—offers a reliable estimate,' but no empirical evidence is provided for this ranking property in the proposed cross-layer space (heterogeneous block types, depths, channels, and mixed precisions). The paper should report the Spearman rank correlation between inherited-weight accuracy and accuracy after a short fine-tuning (or full training) for a random sample of subnets from the search space. Without such a correlation check, the evolutionary selection may be guided by a noisy proxy and the reported final accuracies are not a reliable basis for the claims.
minor comments (7)
  1. [§3.3, Eq. (4)] The term EDP_norm in Eq. (4) is not defined; please specify how EDP is normalized across candidates (e.g., min-max over the population).
  2. [Algorithm 1] The loop condition uses the variable cyc, but cyc is not initialized in the input list or in the initialization step; Section 4.2 states 10 cycles, so please set it explicitly in the algorithm or refer to the text.
  3. [§4.2] The evolutionary search settings (population size, number of cycles) are reported for the NN architecture search, but the corresponding settings for the quantization and PIM configuration search are not reported; please provide them.
  4. [Fig. 6] The network diagrams in Figure 6 are difficult to read at the current resolution; consider listing the selected configurations (block types, channels, bit widths, PIM parameters) in a table.
  5. [§2] In Section 2, 'MNISIM 2.0' should be 'MNSIM 2.0' to match the simulator name used elsewhere.
  6. [§3.1] The sentence 'By the end of training, the supernet acts as an approximate model, representing the weights of fully-trained subnet architectures' is stronger than what is demonstrated; suggest softening to 'approximating' or 'empirically approximating'.
  7. [Table 2] For NACIM and UAE, the latency and EDP columns are empty; state whether these values are taken from the original papers or re-evaluated with MNSIM 2.0.

Circularity Check

1 steps flagged · score 6.0 of 10

Test-set leakage in the search loop: Algorithm 1 receives 'test data' as input and Eq. (3) maximizes FF_test, so the accuracies reported in Tables 2–4 are selected on the test set rather than independently benchmarked.

  1. fitted input called prediction [Section 3.1, Eq. (3); Algorithm 1 (Section 3.2); Tables 2–4 (Section 4.3–4.4)]
    "a* = argmax_{a in A} FF_test N(a, W_SUP(a)) ... Since each fitness function (FF_test) utilized in this work includes accuracy as a key metric, we assess accuracy through inference using weights inherited from the supernet. Algorithm 1 Input: supernet weights (W_SUP), training data (train), test data (test), population (P), ... FF_{i-1} <= Calculate_FF(W_SUP, train, test, P_{i-1})"

    The evolutionary search's fitness is computed on the test set: Algorithm 1 takes 'test data' as an explicit input and calls Calculate_FF(..., test, ...) every cycle, and Eq. (3) selects the architecture maximizing FF_test. The topK candidates are updated by these test-set fitness scores. Tables 2–4 then report accuracy on the same CIFAR-10/CIFAR-100 test sets, e.g., 91.27% for w_acc=0.99. That number is not an independent evaluation of a model chosen on a held-out validation set; it is the value the search was directly maximizing (followed by one final fine-tune). The comparison to Gibbon, NACIM, UAE, and NAS4RRAM therefore confounds generalization with selection on the test set, making the headline accuracy statistically forced by the search procedure itself.

full rationale

The derivation from supernet training to architecture selection is not circular in the self-definitional sense: the supernet is trained on training data with eq. (2), and the weight-sharing proxy is a stated assumption about ranking quality, not a quantity defined by the output. No load-bearing self-citation chain or uniqueness theorem is invoked; the authors' prior work appears only as background, and MNSIM 2.0 is an external simulator. The significant circularity is in the benchmark claim: Algorithm 1 explicitly consumes test data, Eq. (3) maximizes FF_test, and the same test sets are later reported as the achieved accuracy in Tables 2–4. Because the evolutionary search selects the final architecture on the test set, the reported accuracy is the optimization objective itself, not an unbiased estimate of it. This makes the central comparison to prior methods statistically forced and reduces the headline accuracy 'prediction' to a test-set fit. Other concerns, such as the reliability of inherited-weight accuracy estimates or the post-hoc stride-2 change for CIFAR-100, are correctness risks rather than circularity. Overall, partial circularity is present and concentrated in the evaluation protocol.

Assumptions & free parameters 3 free parameters · 4 assumptions · 0 invented entities

The central claim rests on simulator fidelity, the predictive power of inherited supernet weights, and user-set fitness weights. No new physical entities are introduced.

free parameters (3)
  • Maximum output channels per block = 128
    Hand-chosen search space limit that bounds model capacity; it is the stated reason for the 2.75% accuracy drop behind ResNet18 on CIFAR-100 (Section 4.4).
  • Stride of first conv layers in RES block (CIFAR-100) = 2
    Post-hoc modification introduced only for CIFAR-100 runs to shrink feature maps and improve EDP; not in the original search space (Section 4.4).
  • Fitness weight w_acc = 0.99 and 0.8
    User-set scalar controlling the accuracy/EDP trade-off; the two reported models and all comparisons depend on these values (Section 3.2, eq. (4)).
assumptions (4)
  • domain assumption MNSIM 2.0 gives accurate behavior-level estimates of PIM accuracy, energy, and latency.
    All PIM hardware metrics are taken from this simulator (Sections 2 and 4.1); the energy and EDP comparisons are only as valid as the simulator.
  • domain assumption Inherited supernet weights are sufficiently predictive of fully-trained subnet accuracy to rank candidates.
    The evolutionary search scores subnets using inherited weights without retraining (Section 3.2); no validation of this assumption for the cross-layer space is presented.
  • ad hoc to paper Using the test set to guide the search is acceptable.
    Algorithm 1 includes test data in the fitness evaluation, which violates standard validation-set practice and biases the reported accuracy.
  • domain assumption The non-uniform quantization scheme with moving-average scaling is an effective and fair quantization approach.
    Taken from [27] and applied without comparing against other quantization methods (Section 3.3).

how reviews work

0 comments
Cite this review

Pith. "Pith review of CrossNAS: A Cross-Layer Neural Architecture Search Framework for PIM Systems." pith.science (2026). https://pith.science/paper/UURCC3MW

@misc{pith2026250522868,
  author       = {Pith},
  title        = {Pith review of: CrossNAS: A Cross-Layer Neural Architecture Search Framework for PIM Systems},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/UURCC3MW}},
  note         = {Machine review of arXiv:2505.22868}
}
read the original abstract

In this paper, we propose the CrossNAS framework, an automated approach for exploring a vast, multidimensional search space that spans various design abstraction layers-circuits, architecture, and systems-to optimize the deployment of machine learning workloads on analog processing-in-memory (PIM) systems. CrossNAS leverages the single-path one-shot weight-sharing strategy combined with the evolutionary search for the first time in the context of PIM system mapping and optimization. CrossNAS sets a new benchmark for PIM neural architecture search (NAS), outperforming previous methods in both accuracy and energy efficiency while maintaining comparable or shorter search times.

Figures

Figures reproduced from arXiv: 2505.22868 by the authors.

Figure 1
Figure 1. The CrossNAS method explores a multi￾dimensional search space across multiple design abstraction layers—circuit, architecture, and system levels—using a custom multi-objective search and optimization process. reinforcement learning and LSTM controller, respectively, but they explore only VGG-like models, which limits their performance. NAS4RRAM [31] also provides a similar framework for ResNet￾like architectures. NA… view at source ↗
Figure 2
Figure 2. (a) The analog PIM architecture with multiple banks including several interconnected tiles. (b) The PIM tile consists [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Optimization flow for the CrossNAS framework. [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figures from the paper (2 more)
Figure 5
Figure 5. Figure 5: CrossNAS search results on CIFAR-10 dataset com [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 6
Figure 6. Figure 6: Block types along with channel numbers ( [PITH_FULL_IMAGE:figures/full_fig_p006_6.png]

Discussion (0). Sign in to comment.

Reference graph

Works this paper leans on

36 extracted references · 19 canonical work pages

  1. [1]

    Md Hasibul Amin, Mohammed Elbtity, and Ramtin Zand. 2022. Interconnect Parasitics and Partitioning in Fully-Analog In-Memory Computing Architectures. In2022 IEEE International Symposium on Circuits and Systems (ISCAS). 389–393. doi:10.1109/ISCAS48785.2022.9937884

    arXiv 2022

  2. [2]

    Elbtity, and Ramtin Zand

    Md Hasibul Amin, Mohammed E. Elbtity, and Ramtin Zand. 2022. Xbar- Partitioning: A Practical Way for Parasitics and Noise Tolerance in Analog IMC Circuits.IEEE Journal on Emerging and Selected Topics in Circuits and Systems12, 4 (2022), 867–877. doi:10.1109/JETCAS.2022.3222966

    arXiv 2022

  3. [3]

    Md Hasibul Amin, Mohammadreza Mohammadi, and Ramtin Zand. 2024. Multi- Objective Neural Architecture Search for In-Memory Computing. In2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 343–348. doi:10.1109/ ISVLSI61997.2024.00069

    arXiv 2024

  4. [4]

    Stanley Williams, Paolo Faraboschi, Wen-mei W Hwu, John Paul Stra- chan, Kaushik Roy, and Dejan S

    Aayush Ankit, Izzat El Hajj, Sai Rahul Chalamalasetti, Geoffrey Ndu, Martin Foltin, R. Stanley Williams, Paolo Faraboschi, Wen-mei W Hwu, John Paul Stra- chan, Kaushik Roy, and Dejan S. Milojicic. 2019. PUMA: A Programmable Ultra- Efficient Memristor-Based Accelerator for Machine Learning Inference. InPro- ceedings of the Twenty-Fourth International Confe...

    arXiv 2019

  5. [5]

    Gabriel Bender, Pieter-Jan Kindermans, Barret Zoph, Vijay Vasudevan, and Quoc Le. 2018. Understanding and Simplifying One-Shot Architecture Search. In Proceedings of the 35th International Conference on Machine Learning (Proceedings of Machine Learning Research, Vol. 80), Jennifer Dy and Andreas Krause (Eds.). PMLR, 550–559. https://proceedings.mlr.press/...

    work page 2018

  6. [6]

    Hadjer Benmeziane, Corey Lammie, Irem Boybat, Malte Rasch, Manuel Le Gallo, Hsinyu Tsai, Ramachandran Muralidhar, Smail Niar, Ouarnoughi Hamza, Vijay Narayanan, Abu Sebastian, and Kaoutar El Maghraoui. 2023. AnalogNAS: A Neural Network Design Framework for Accurate Inference with Analog In- Memory Computing. In2023 IEEE International Conference on Edge Co...

    arXiv 2023

  7. [7]

    Han Cai, Ligeng Zhu, and Song Han. 2019. ProxylessNAS: Direct Neural Ar- chitecture Search on Target Task and Hardware. arXiv:1812.00332 [cs.LG] https://arxiv.org/abs/1812.00332

    arXiv 2019

  8. [8]

    Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang, and Yuan Xie. 2016. PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory. InProceedings of the 43rd International Symposium on Computer Architecture(Seoul, Republic of Korea)(ISCA ’16). 27–39

    work page 2016

Show all 36 references
  1. [9]

    Mohammed Elbtity, Abhishek Singh, Brendan Reidy, Xiaochen Guo, and Ramtin Zand. 2021. An In-Memory Analog Computing Co-Processor for Energy-Efficient CNN Inference on Mobile Devices. In2021 IEEE Computer Society Annual Sympo- sium on VLSI (ISVLSI). 188–193. doi:10.1109/ISVLSI5...

    2021 arXiv

  2. [10]

    Elbtity, Brendan Reidy, Md Hasibul Amin, and Ramtin Zand

    Mohammed E. Elbtity, Brendan Reidy, Md Hasibul Amin, and Ramtin Zand. 2023. Heterogeneous Integration of In-Memory Analog Computing Architectures with Tensor Processing Units. InProceedings of the Great Lakes Symposium on VLSI 2023(Knoxville, TN, USA)(GLSVLSI ’23). Association...

    2023

  3. [11]

    Zichao Guo, Xiangyu Zhang, Haoyuan Mu, Wen Heng, Zechun Liu, Yichen Wei, and Jian Sun. 2020. Single Path One-Shot Neural Architecture Search with Uniform Sampling. InComputer Vision – ECCV 2020, Andrea Vedaldi, Horst Bischof, Thomas Brox, and Jan-Michael Frahm (Eds.). Springer...

    2020

  4. [12]

    Kaiming He, Xiangyu Zhang, Shaoqing Ren, and Jian Sun. 2016. Deep Residual Learning for Image Recognition. In2016 IEEE Conference on Computer Vision and Pattern Recognition (CVPR). 770–778. doi:10.1109/CVPR.2016.90

    2016 doi

  5. [13]

    Grafals, Noraica Davila, Catherine Graves, Sity Lam, Ning Ge, Jianhua Joshua Yang, and R

    Miao Hu, John Paul Strachan, Zhiyong Li, Emmanuelle M. Grafals, Noraica Davila, Catherine Graves, Sity Lam, Ning Ge, Jianhua Joshua Yang, and R. Stanley Williams. 2016. Dot-product engine for neuromorphic computing: Program- ming 1T1M crossbar to accelerate matrix-vector multi...

    2016 doi

  6. [14]

    Weiwen Jiang, Qiuwen Lou, Zheyu Yan, Lei Yang, Jingtong Hu, Xiaobo Sharon Hu, and Yiyu Shi. 2021. Device-Circuit-Architecture Co-Exploration for Computing- in-Memory Neural Accelerators.IEEE Trans. Comput.70, 4 (2021), 595–605. doi:10.1109/TC.2020.2991575

    2021

  7. [15]

    Kulkarni, and Tony Tae-Hyoung Kim

    Donghyuk Kim, Chengshuo Yu, Shanshan Xie, Yuzong Chen, Joo-Young Kim, Bongjin Kim, Jaydeep P. Kulkarni, and Tony Tae-Hyoung Kim. 2022. An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learn- ing.IEEE Journal on Emerging and Selected Topics i...

    2022

  8. [16]

    Sungho Kim, Hee-Dong Kim, and Sung-Jin Choi. 2019. impact of Synaptic Device Variations on Classification Accuracy in a Binarized neural network.Scientific reports9, 1 (2019), 1–7

    2019

  9. [17]

    Kingma and Jimmy Ba

    Diederik P. Kingma and Jimmy Ba. 2017. Adam: A Method for Stochastic Opti- mization. arXiv:1412.6980 [cs.LG] https://arxiv.org/abs/1412.6980

    2017 arXiv

  10. [18]

    2009.Learning multiple layers of features from tiny images

    Alex Krizhevsky and Geoffrey Hinton. 2009.Learning multiple layers of features from tiny images. Technical Report 0. University of Toronto, Toronto, Ontario. https://www.cs.toronto.edu/~kriz/learning-features-2009-TR.pdf

    2009

  11. [19]

    Alex Krizhevsky, Ilya Sutskever, and Geoffrey E Hinton. 2012. ImageNet Clas- sification with Deep Convolutional Neural Networks. InAdvances in Neural Information Processing Systems, F. Pereira, C.J. Burges, L. Bottou, and K.Q. Wein- berger (Eds.), Vol. 25. Curran Associates, I...

    2012

  12. [20]

    Manuel Le Gallo, Abu Sebastian, Roland Mathis, Matteo Manica, Heiner Giefers, Tomas Tuma, Costas Bekas, Alessandro Curioni, and Evangelos Eleftheriou. 2018. Mixed-precision in-memory computing.Nature Electronics1, 4 (2018), 246–253

    2018

  13. [21]

    Shubham Negi, Indranil Chakraborty, Aayush Ankit, and Kaushik Roy. 2022. NAX: neural architecture and memristive xbar based accelerator co-design. In Proceedings of the 59th ACM/IEEE Design Automation Conference(San Francisco, California)(DAC ’22). Association for Computing Ma...

    2022

  14. [22]

    Hieu Pham, Melody Guan, Barret Zoph, Quoc Le, and Jeff Dean. 2018. Efficient Neural Architecture Search via Parameters Sharing. InProceedings of the 35th International Conference on Machine Learning (Proceedings of Machine Learning Research, Vol. 80), Jennifer Dy and Andreas K...

    2018

  15. [23]

    Sebastian Ruder. 2017. An overview of gradient descent optimization algorithms. arXiv:1609.04747 [cs.LG] https://arxiv.org/abs/1609.04747

    2017 arXiv

  16. [24]

    Stanley Williams, and Vivek Srikumar

    Ali Shafiee, Anirban Nag, Naveen Muralimanohar, Rajeev Balasubramonian, John Paul Strachan, Miao Hu, R. Stanley Williams, and Vivek Srikumar. 2016. ISAAC: A Convolutional Neural Network Accelerator with in-Situ Analog Arith- metic in Crossbars(ISCA ’16). IEEE Press, 14–26. doi...

    2016 doi

  17. [25]

    Karen Simonyan and Andrew Zisserman. 2015. Very Deep Convolutional Net- works for Large-Scale Image Recognition. InInternational Conference on Learning Representations

    2015

  18. [26]

    Dimitrios Stamoulis, Ruizhou Ding, Di Wang, Dimitrios Lymberopoulos, Bodhi Priyantha, Jie Liu, and Diana Marculescu. 2020. Single-Path NAS: Designing Hardware-Efficient ConvNets in Less Than 4 Hours. InMachine Learning and Knowledge Discovery in Databases, Ulf Brefeld, Elisa F...

    2020

  19. [27]

    Hanbo Sun, Zhenhua Zhu, Yi Cai, Xiaoming Chen, Yu Wang, and Huazhong Yang

  20. [28]

    Hanbo Sun, Zhenhua Zhu, Chenyu Wang, Xuefei Ning, Guohao Dai, Huazhong Yang, and Yu Wang. 2023. Gibbon: An Efficient Co-Exploration Framework of NN Model and Processing-In-Memory Architecture.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems42, 11 (...

    2023

  21. [29]

    Bichen Wu, Xiaoliang Dai, Peizhao Zhang, Yanghan Wang, Fei Sun, Yiming Wu, Yuandong Tian, Peter Vajda, Yangqing Jia, and Kurt Keutzer. 2019. FBNet: Hardware-Aware Efficient ConvNet Design via Differentiable Neural Architecture Search. In2019 IEEE/CVF Conference on Computer Vis...

    2019

  22. [30]

    Zheyu Yan, Da-Cheng Juan, Xiaobo Sharon Hu, and Yiyu Shi. 2021. Uncertainty Modeling of Emerging Device based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Search. In2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC). 859–864

    2021

  23. [31]

    Zhihang Yuan, Jingze Liu, Xingchen Li, Longhao Yan, Haoxiang Chen, Bingzhe Wu, Yuchao Yang, and Guangyu Sun. 2021. NAS4RRAM: neural network architec- ture search for inference on RRAM-based accelerators.Science China Information Sciences64, 6 (10 May 2021), 160407. doi:10.1007...

    2021 doi

  24. [32]

    Ramtin Zand, Arman Roohi, and Ronald F DeMara. 2018. Fundamentals, modeling, and application of magnetic tunnel junctions. InNanoscale Devices. CRC Press, 337–368

    2018

  25. [33]

    Xinbang Zhang, Zehao Huang, Naiyan Wang, Shiming Xiang, and Chunhong Pan. 2021. You Only Search Once: Single Shot Neural Architecture Search via Direct Sparse Optimization .IEEE Transactions on Pattern Analysis & Machine Intelligence43, 09 (Sept. 2021), 2891–2904. doi:10.1109/...

    2021

  26. [34]

    Zhenhua Zhu, Hanbo Sun, Tongxin Xie, Yu Zhu, Guohao Dai, Lixue Xia, Dimin Niu, Xiaoming Chen, Xiaobo Sharon Hu, Yu Cao, Yuan Xie, Huazhong Yang, and Yu Wang. 2023. MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In- Memory Architectures.IEEE Transactions on Computer-A...

    2023

  27. [2020]

    In2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)

    An Energy-Efficient Quantized and Regularized Training Framework For Processing-In-Memory Accelerators. In2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC). 325–330. doi:10.1109/ASP-DAC47756.2020. 9045192

    2020

  28. [4089]

    doi:10.1109/TCAD.2023.3262201

    2023

Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.