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REVIEW 3 major objections 5 minor 135 references

QiMeng: Fully Automated Hardware and Software Design for Processor Chip

T0 review · 3 major / 5 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read QiMeng proposes a three-layer LLM system that would fully automate processor chip design, with hardware and software agents built on a domain-specific Large Processor Chip Model.

desk verdict Roadmap paper with real component pedigree; the fully-automated central claim is not yet supported and the cross-stage training step is unvalidated, but this deserves refereeing as a position paper. read the letter →

arxiv 2506.05007 v1 pith:72XNKLVY submitted 2025-06-05 cs.AR cs.LG

Rui Zhang , Yuanbo Wen , Shuyao Cheng , Di Huang , Shaohui Peng , Jiaming Guo , Pengwei Jin , Jiacheng Zhao
show 12 more authors
Tianrui Ma Yaoyu Zhu Yifan Hao Yongwei Zhao Shengwen Liang Ying Wang Xing Hu Zidong Du Huimin Cui Ling Li Qi Guo Yunji Chen
This is my paper
classification cs.ARcs.LG
keywords automatedprocessorchipdesignlargelanguagemodelshardware-softwareco-designdomain-specificLLMHDLgenerationcompilertool-chaintensorprogramtranscompilationhigh-performancelibrary
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

QiMeng is a proposal for a three-layer system that would automate processor chip design end to end, from a natural-language specification to working hardware and its foundational software stack. The bottom layer is a domain-specific Large Processor Chip Model (LPCM), a multimodal language model designed to ingest both text and graph-structured design knowledge. The middle layer adds a Hardware Design Agent and a Software Design Agent, each combining an inner verification-and-repair loop for functional correctness with an outer search loop for performance. The paper's evidence comes from components that are already built and applied individually, including two automatically designed CPUs, an HDL code generator, an OS configuration tuner, a tensor-program transcompiler, and LLM-generated high-performance libraries. The full QiMeng system, with LPCM trained on cross-stage aligned data, is presented as a roadmap whose first phase is still in progress.

What carries the argument

The load-bearing object is the Large Processor Chip Model (LPCM), a domain-specific multimodal LLM that understands and generates both text and graph representations such as abstract syntax trees, data-flow graphs, and control-flow graphs. Around LPCM, the two agents run dual feedback loops: an inner correctness loop that verifies generated hardware or software and repairs errors, and an outer performance loop that searches a tree of design or optimization choices and prunes low-performing branches. For hardware, the central correctness mechanism is the Binary Speculation Diagram (BSD), a graph representation of combinational circuits whose functional accuracy grows monotonically with each verification-and-repair cycle and asymptotically approaches 100 percent. For training, the key machinery is a cross-stage collaborative design database built by cascading single-stage automated design models, which is then used for chain-of-thought imitation learning to give LPCM cross-stage design reasoning.

What would settle it

Train the cascaded single-stage models on stage-specific data, run them end to end on a small processor specification, and check whether the resulting chain of HDL, netlists, and layouts passes functional verification against the original specification; if the cascaded outputs cannot be aligned into verified multi-stage traces, the cross-stage database that LPCM depends on does not exist.

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Extended reading notes

Core claim

The paper's central claim is that a domain-specific, graph-aware large language model, LPCM, can serve as the shared reasoning core for both hardware design and software design, and that dual-loop feedback agents built on it are the right mechanism for full automation. The paper identifies four obstacles to LLM-based chip design: the gap between graph-structured design knowledge and sequential text, domain data scarcity, the need for near-perfect correctness, and an enormous solution space. Its proposed answers are a multimodal text-graph architecture, cross-stage collaborative training that cascades independently trained single-stage models to synthesize aligned multi-stage data, correctness feedback through automated functional verification and repair, and performance feedback through hierarchical search with pruning. The paper further claims that completed components already show significant advantages: QiMeng-CPU-v1 and QiMeng-CPU-v2 reached industrial scale and performance comparable to commercial CPUs, CodeV achieves strong Verilog generation results among open models, and AutoOS, QiMeng-Xpiler, QiMeng-GEMM, and QiMeng-TensorOp match or exceed hand-tuned baselines across multiple processor platforms.

Load-bearing premise

The system holds together only if separately trained single-stage design models can be cascaded into coherent multi-stage design traces that are aligned and correct enough to train LPCM's cross-stage reasoning, and no experiment in this paper tests that cascade.

Editorial extensions

If this is right

  • If LPCM works as specified, the Hardware Design Agent could go from a functional specification to a physical layout without human engineering, unifying logic, circuit, and physical design in one automated flow.
  • The Software Design Agent could produce OS configurations, compiler backends, tensor-program translations, and high-performance libraries for new processors, reducing the combinatorial cost of adapting software to fragmented instruction sets such as RISC-V.
  • Automated front-end design using BSD-based verification and repair has already produced a 32-bit RISC-V CPU with about four million gates in five hours, suggesting the correctness loop can scale beyond the thousand-gate circuits of earlier work.
  • The same verification-repair loop can push functional correctness of generated modules asymptotically toward 100 percent, addressing the probabilistic-output weakness of LLMs without requiring zero initial accuracy.
  • Following the three-phase roadmap, the top-down phase of building applications would generate domain data, the bottom-up phase would retrain agents on an improved LPCM, and the iteration phase would make the system self-evolving.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A natural testable extension is to run the cascaded single-stage models on a small instruction set and check whether the generated HDL, netlists, and layouts align and pass functional verification; this would directly probe whether the cross-stage database that LPCM depends on actually exists.
  • If the cascade works, the same data-synthesis trick could transfer to other hardware-adjacent domains with scarce cross-stage data, such as FPGA accelerators, analog circuits, or system-on-chip integration, an extension the paper does not state.
  • The paper's self-evolution phase implies that the system's own generated designs would become training data, which raises a question about feedback-loop quality that the paper leaves open: whether errors in earlier stages would compound or be corrected by the verification loops.
  • One could also benchmark LPCM's graph-generation fidelity directly by comparing generated circuit diagrams and layouts against verified HDL output, providing an alignment metric that the paper does not yet report for full chains.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. This paper proposes QiMeng, a three-layer system for fully automated hardware and software design of processor chips: a bottom-layer domain-specific Large Processor Chip Model (LPCM), a middle-layer Hardware Design Agent and Software Design Agent, and a top-layer set of applications. The LPCM is designed as a multimodal model that handles graph-structured data, is trained on cross-stage aligned data generated by cascaded single-stage design models, and performs feedback-driven inference with functional correctness and performance feedback loops. The agents combine these capabilities with symbolic verification and search-based optimization. The paper reports several completed components, including QiMeng-CPU-v1/v2 for automated front-end design, CodeV and CodeV-R1 for HDL generation, AutoOS for OS configuration optimization, compiler tool-chain generation, QiMeng-Xpiler for tensor program transcompilation, and QiMeng-GEMM, QiMeng-TensorOp, and QiMeng-Attention for high-performance library generation. The manuscript explicitly states that the work is still in the first phase of a three-phase roadmap, that the current components operate without LPCM, and that integration of these components and training of LPCM are future work.

Significance. If realized as described, QiMeng would be a major step toward automated hardware-software co-design, addressing a long-standing open problem. The completed components are individually significant and have appeared in prior publications: QiMeng-CPU-v1 is a fully automatically designed 32-bit RISC-V CPU, QiMeng-CPU-v2 is an automated superscalar CPU, and the software components show strong performance on their respective benchmarks. The paper is notably honest about its current phase, clearly articulating the top-down, bottom-up, and iteration roadmap and explicitly flagging that the integrated system does not yet exist. The main scientific value at this stage is the articulation of a structured research program with strong component-level building blocks, rather than a validated system. The cross-stage alignment problem for LPCM training is a genuine and well-identified open problem, but no evidence is provided that the proposed cascade can solve it.

major comments (3)
  1. [Section III-B (Cross-stage Collaborative Training)] The cascade of independently trained single-stage models is the only proposed mechanism for generating the cross-stage aligned data needed to train LPCM, but the paper gives no mechanism or experiment showing that the cascaded outputs are mutually consistent. For example, a compiler backend generated for an ISA may not match the RTL generated for that ISA, and an OS configuration need not correspond to the microarchitecture being designed; without a consistency constraint or a joint training signal, errors compound and the resulting (input, CoT, output) triplets would contain invalid design reasoning. This gap is load-bearing because CoT imitation learning in this section is what gives LPCM its claimed hierarchical design capability. I suggest adding a proof-of-concept cascade, for instance specification-to-RTL-to-netlist or ISA-to-compiler-backend, with alignment metrics and an evaluation showing that LPCM trained on the resulting traces improves downstream design on held-out tasks.
  2. [Abstract, Section I, Section II, Section V-A] The central claim of a fully automated system is not supported by an integrated implementation. Section II states that 'The current work is still in the first phase of the three-phase approach,' Section V-A explicitly notes that QiMeng-CPU-v1 and QiMeng-CPU-v2 'currently operate without utilizing LPCM,' and Section V-B describes CodeV as a component rather than as part of a working agent driven by a trained LPCM. No experiment exercises QiMeng end-to-end, so the paper's contribution is currently a roadmap with independently validated components, not a demonstrated system. The title and abstract should be reframed accordingly, or an end-to-end case study should be added.
  3. [Section V (Applications) and Tables I-VIII] The quantitative evidence for the completed components consists largely of results cited from the authors' prior papers: Table II is taken from CodeV, Table III from CodeV-R1, Table IV from AutoOS, Table V from QiMeng-Xpiler, and Tables VI-VIII from QiMeng-GEMM, QiMeng-TensorOp, and QiMeng-Attention. The manuscript provides no measurement methodology, reproducibility information, or new evaluation for these results in this paper. If the contribution is the QiMeng architecture, these tables serve as prior work and the paper should concentrate on the integration; if component-level advances are claimed, new experiments are required to support them.
minor comments (5)
  1. [Section V-E, Table IV, Table VI] There are several typos: 'tanscompiler' in Section V-E, 'OAPTIMIZATION' in the title of Table IV, and 'GPUUTILIZES' in the caption of Table VI.
  2. [Figure 5] The y-axis of Figure 5 is not labeled and the performance metric and its units are not specified; the reader cannot determine whether the comparison is in Dhrystone MIPS, DMIPS, or some other measure.
  3. [Throughout] The capitalization of the CPU design names is inconsistent: Table I uses 'QiMeng-CPU-V1' and 'QiMeng-CPU-V2' while the text uses 'QiMeng-CPU-v1' and 'QiMeng-CPU-v2'; please standardize.
  4. [References [12] and [83]] Reference [12] (Large Processor Chip Model) and reference [83] (QiMeng-TensorOp) appear to share the same arXiv identifier 2505.06302; one of these references likely has an incorrect ID.
  5. [Section II and Section V-A] Section II describes the first phase as 'developing various applications based on the LPCM, which is initialized with a general-purpose LLM,' but Section V-A states that the CPU designs operate without LPCM; please clarify what role, if any, the LPCM or a general-purpose LLM plays in the completed applications.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity; the system is an unvalidated roadmap whose completed components are externally benchmarked, so the central claim is overreaching but not circular.

full rationale

QiMeng is a roadmap/system paper. Its central claim is that a fully automated hardware/software design system can be built around a domain-specific LPCM. The proposed training/inference chain (single-stage models → cascaded cross-stage data → LPCM → agents → applications) is a forward bootstrapping loop: LPCM starts as a general-purpose LLM, and the cascade's outputs are independent of the trained LPCM, so no step reduces to its own output. The completed components (QiMeng-CPU-v1/v2, CodeV, AutoOS, QiMeng-Xpiler, QiMeng-GEMM, QiMeng-TensorOp) are validated by external tape-outs and standard benchmarks (Dhrystone, VerilogEval, RTLLM, UnixBench, OpenBLAS/cuBLAS), with results cited from prior papers; self-citations of this kind are genuine evidence under the independence rule. The paper explicitly states the current work is still in the first phase and that QiMeng-CPU-v1/v2 'currently operate without utilizing LPCM', and future work must 'automatically generate extensive domain-specialized data to train LPCM'. This makes the integrated fully-automated claim incomplete/overstated, but not circular: the LPCM bootstrapping loop is a proposed future feedback process, not a derivation that assumes what it predicts. No fitted parameter is renamed as a prediction, and no uniqueness theorem is imported from the authors' prior work.

Assumptions & free parameters 0 free parameters · 5 assumptions · 3 invented entities

The paper is a system proposal, so the ledger captures the core assumptions behind the proposed LPCM training and inference, and the key entities that are hypothesized but not yet validated. No free parameters are fit in this paper; quantitative results are inherited from cited prior work.

assumptions (5)
  • domain assumption Multimodal architecture with GNN encoding preserves graph topology and aligns graph embeddings with text via contrastive learning, enabling LPCM to understand graph-based design data.
    Invoked in Section III-A as the solution to the knowledge representation gap, but no validation is provided in this paper.
  • domain assumption Cascaded single-stage design models can generate cross-stage aligned data sufficient to train LPCM for hierarchical reasoning.
    Described in Section III-B as the answer to data scarcity; no experiment demonstrates that the cascaded synthesis produces coherent multi-stage designs.
  • domain assumption The verification-repair loop monotonically increases functional accuracy and asymptotically approaches 100% correctness.
    Used in Section III-C1 and V-A to justify automated correctness; convergence is stated as a property but not proven in this paper.
  • ad hoc to paper The three-phase roadmap (top-down, bottom-up, iteration) will lead to a self-evolving system capable of full automation.
    Section II outlines this roadmap as the path to full automation; it is an aspirational plan with no supporting evidence in the paper.
  • domain assumption The solution space for a 32-bit CPU is 10^(10^540), motivating hierarchical decomposition.
    Mentioned in the introduction and Section III-C2 without a derivation; used as a premise for the need for performance feedback pruning.
invented entities (3)
  • Large Processor Chip Model (LPCM)
    purpose: Domain-specific multimodal LLM that understands and generates text and graph representations for processor chip design.
    Proposed as the foundational model of QiMeng; not trained or evaluated in this paper.
  • Hardware Design Agent
    purpose: Automates hardware design from functional specifications to physical layout via dual-loop verification and performance feedback.
    Described in Section IV-A; only component pieces (from prior work) exist, not the full agent.
  • Software Design Agent
    purpose: Automates software adaptation and performance optimization for processors via dual-loop feedback.
    Described in Section IV-B; only component pieces (from prior work) exist, not the full agent.

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Pith. "Pith review of QiMeng: Fully Automated Hardware and Software Design for Processor Chip." pith.science (2026). https://pith.science/paper/72XNKLVY

@misc{pith2026250605007,
  author       = {Pith},
  title        = {Pith review of: QiMeng: Fully Automated Hardware and Software Design for Processor Chip},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/72XNKLVY}},
  note         = {Machine review of arXiv:2506.05007}
}
read the original abstract

Processor chip design technology serves as a key frontier driving breakthroughs in computer science and related fields. With the rapid advancement of information technology, conventional design paradigms face three major challenges: the physical constraints of fabrication technologies, the escalating demands for design resources, and the increasing diversity of ecosystems. Automated processor chip design has emerged as a transformative solution to address these challenges. While recent breakthroughs in Artificial Intelligence (AI), particularly Large Language Models (LLMs) techniques, have opened new possibilities for fully automated processor chip design, substantial challenges remain in establishing domain-specific LLMs for processor chip design. In this paper, we propose QiMeng, a novel system for fully automated hardware and software design of processor chips. QiMeng comprises three hierarchical layers. In the bottom-layer, we construct a domain-specific Large Processor Chip Model (LPCM) that introduces novel designs in architecture, training, and inference, to address key challenges such as knowledge representation gap, data scarcity, correctness assurance, and enormous solution space. In the middle-layer, leveraging the LPCM's knowledge representation and inference capabilities, we develop the Hardware Design Agent and the Software Design Agent to automate the design of hardware and software for processor chips. Currently, several components of QiMeng have been completed and successfully applied in various top-layer applications, demonstrating significant advantages and providing a feasible solution for efficient, fully automated hardware/software design of processor chips. Future research will focus on integrating all components and performing iterative top-down and bottom-up design processes to establish a comprehensive QiMeng system.

Figures

Figures reproduced from arXiv: 2506.05007 by the authors.

Figure 1
Figure 1. Overview. QiMeng consists of three layers, a domain-specialized [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Left: Multimodal architecture of LPCM capable of understanding, representing, and generating both text and graph data. Right: Feedback-driven [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figure 3
Figure 3. Structure of Hardware Design Agent which features a dual-loop feedback mechanism: an outer module decomposition feedback loop based on [PITH_FULL_IMAGE:figures/full_fig_p008_3.png] view at source ↗
Figures from the paper (2 more)
Figure 4
Figure 4. Figure 4: Structure of Software Design Agent which uses a dual-loop feedback mechanism: the outer loop focusing on performance optimization feedback [PITH_FULL_IMAGE:figures/full_fig_p009_4.png]
Figure 5
Figure 5. Figure 5: Performance of QiMeng-CPU series (blue) compared with human [PITH_FULL_IMAGE:figures/full_fig_p010_5.png]

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Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.