There's Waldo: PCB Tamper Forensic Analysis using Explainable AI on Impedance Signatures

Fatemeh Ganji; Maryam Saadat Safa; Seyedmohammad Nouraniboosjin; Shahin Tajik

REVIEW 4 major objections 6 minor 22 references

There's Waldo: PCB Tamper Forensic Analysis using Explainable AI on Impedance Signatures

T0 review · 4 major / 6 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read This paper claims that a random forest trained on the reflection signature of a PCB's power delivery network can detect tampering, name the modified component, and identify which parasitic characteristic changed, with 96.7% accuracy and…

desk verdict A credible simulation-only proof of concept for component-level tamper classification, undermined by an unimplemented DTW alignment and no measured-board validation. read the letter →

arxiv 2506.05734 v1 pith:CPEY5PC4 submitted 2025-06-06 cs.CR

Maryam Saadat Safa , Seyedmohammad Nouraniboosjin , Fatemeh Ganji , Shahin Tajik This is my paper

classification cs.CR

keywords PCBtamperforensicspowerdeliverynetworkS-parametersrandomforestclassifierSHAPexplainabilityimpedancesignaturehardwaredetection

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper asks whether the two-dimensional impedance signature of a PCB's power delivery network can be reverse-engineered for forensics, not just detection. It answers that a random forest classifier trained on simulated |S11| traces can distinguish eleven classes—genuine boards and ten tamper types defined by which component and which parasitic parameter (ESL, ESR, or parasitic capacitance) was altered—at 96.7% accuracy. SHAP values then show which frequency points drive each decision, and those frequencies align with the physical resonance behavior of the affected components. If the simulation-to-measurement transfer holds, a verifier could pinpoint the compromised component from a single non-invasive measurement, avoiding costly visual inspection.

What carries the argument

The central object is the $|S_{11}|$ reflection coefficient of the PDN, sampled at 5,000 frequency points from 1 MHz to 1 GHz, related to port impedance by $Z_{\mathrm{DUT}} = Z_0(1+S_{11})/(1-S_{11})$. The argument is carried by a random forest classifier (11 classes, 5-fold cross-validation, per-fold accuracy from 96.33% to 96.83%) whose decisions are explained by TreeSHAP additive per-frequency contributions. The physical mechanism that makes the classification interpretable is that each component class moves a characteristic resonance: capacitance and ESL shifts move resonance frequencies, ESR and resistance change amplitudes, and the most influential SHAP features line up with these resonances. The paper avoids PCA because its transformed features cannot be mapped back to individual frequencies, which would destroy the explainability needed for forensics.

What would settle it

Measure |S11| from 1 MHz to 1 GHz on a physical PCB with a vector network analyzer, apply a known tamper (for example, replace a capacitor or add series inductance), remeasure, and run the trained random forest; if the predicted tamper class does not match the actual change with accuracy comparable to 96.7%, the simulation-to-measurement transfer fails.

Watch

Extended reading notes

Core claim

The central discovery is that a |S11| magnitude trace measured at the PDN port carries enough information to localize a tamper event to a specific component. The paper's dataset models manufacturing variation by perturbing component values and parasitics, then simulates ten tamper classes: each is a specific capacitor or resistor whose value was multiplied by 10, 100, or 1000 and whose parasitic inductance, series resistance, or parasitic capacitance was varied by 20%. A random forest trained on these traces reaches 96.7% accuracy, and the SHAP explanation identifies the frequency components that matter for each class—for example, the fundamental resonance near 470 MHz and local resonances near 395, 662, and 712 MHz that correspond to specific capacitor families. The conclusion draws the forensic claim: accurate classification of different tamper types and precise localization of tamper events from the signature alone.

Load-bearing premise

The load-bearing premise is that simulated |S11| traces faithfully represent physically tampered boards, since the 96.7% accuracy and every SHAP explanation are produced and tested entirely within simulation, and the proposed alignment of measured to simulated signatures is never implemented or validated.

Editorial extensions

If this is right

A verifier can distinguish a genuine board from boards with one of ten tamper types, and for each tamper type can name both the component (which capacitor or resistor) and the parasitic characteristic that was changed.
The SHAP-identified frequency points give a physical fingerprint: influential frequencies cluster at the fundamental resonance and at component-specific local resonances, so the explanation is a checkable electromagnetic prediction rather than a black-box artifact.
Unknown modifications not present in training can still be flagged as non-genuine, although the model cannot name the exact change.
Because the method labels the tamper type, it reduces the need for time-consuming manual visual inspection to find the modified component.
The same training pipeline is claimed to apply to component insertion or removal, not only replacement.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

Beyond the paper: the SHAP frequency attributions could be inverted into a physical tamper diagnosis—a shift in resonance frequency suggests an inductance or capacitance change, while an amplitude change at low frequency suggests a resistance change—turning the classifier into an automated failure-analysis tool.
The reported 96.7% accuracy is an upper bound on real-world performance: training and testing both draw from the same simulation campaign, so the decisive next test is measured |S11| traces from physically tampered boards.
If the dynamic time warping alignment step described in the threat model is implemented and validated, the approach could work against a golden-free measured baseline, making it practical for boards whose design files are unavailable.
The same random-forest-plus-SHAP recipe could transfer to chip-level PDN impedance sensing, where on-chip impedance measurement already exists, if simulated chip signatures generalize to silicon.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Short take: the genuinely new thing here is classifying which component type and parasitic characteristic changed from |S11|, not just detecting that something changed. The SHAP features line up with resonance frequencies you would expect from the physics, which is a nice cross-check. But the paper sells a forensic tool when the evidence is a simulator. The DTW alignment between measured golden and simulated traces—the piece that would make the transfer plausible—is described in the threat model (Sec. III-A) and never implemented. There is no measured trace anywhere, no code or data release, and no baseline comparison. So the 96.7% accuracy is a statement about separating synthetic perturbation classes in Ansys SIwave, not about real tampered boards. The conclusion's "precise localization" is also overclaimed: Table I labels classes by part number, not physical instance, and the PDN has multiple C0402 caps, so the model cannot say which specific capacitor was altered.

Credit where due: the simulation setup is described in enough detail to reproduce, the 5-fold CV is consistent, and the SHAP-to-resonance mapping (Table III vs. Section IV-C) is physically sensible, even if qualitative. They also admit that unknown tamper types can be detected but not classified, which is honest. The core classification result is likely sound for the simulated setting.

Soft spots are proportionate: this is a real proof of concept, not a fake result. The main weakness is the unvalidated simulation-to-measurement bridge. If they implement the DTW alignment and test on even one real board, the claims would become much more convincing. Without that, readers should treat the forensic claims as aspirational.

Who this is for: people working on non-invasive PCB verification, supply chain security, and XAI for physical signatures. I would not cite it yet because I would wait for measured validation. I would, however, send it to a serious referee at a venue like TIFS or HOST. The idea is novel and the problem is important; a conditional accept with an experimental validation requirement is the right outcome. It deserves referee time, not a desk reject.

Referee Report

4 major / 6 minor

Summary. The paper presents a simulation-based study of PCB tamper forensics using |S11| impedance signatures of a power delivery network. The authors generate a dataset in Ansys SIwave by perturbing component values and parasitics for one PCB design, train a random forest classifier with five-fold cross-validation (96.7% accuracy) to distinguish one genuine class and ten tamper classes defined by component part number and modified parasitic, and use SHAP values to identify which frequency features drive each class decision. The paper claims that this enables reverse-engineering of impedance signatures to determine which component has been compromised and to localize tamper events.

Significance. The core idea is timely and potentially useful: if a classifier trained on simulated signatures transferred to measurements, non-invasive forensic triage would be possible without physical golden or tampered samples. The paper's strengths are a clearly described threat model, a nontrivial simulation setup (242-component PCB, 5000 frequency points), explicit modeling of manufacturing variation, and the use of SHAP to provide per-class frequency attributions. The main weakness is that the entire empirical pipeline is simulation-only; the DTW alignment that is supposed to connect simulated signatures to measured ones (Section III-A) is never implemented, and no measured traces are reported. Consequently, the headline accuracy and the SHAP explanations currently describe the simulator's response to synthetic parameter perturbations, not the response of a physical PCB to tampering. The 'localization' claim is also stronger than the class labels support.

major comments (4)

[Section III-A and Section V] The threat model describes a DTW-based alignment of measured golden signatures to simulated signatures before training, but this step is never implemented or validated; no measured |S11| trace appears anywhere in the paper. As a result, the 96.7% accuracy in Table II and the SHAP attributions in Table III and Fig. 4 cannot be taken as evidence about real tamper forensics, and the claims in Section IV-B and Section VI that the method identifies compromised components and localizes tamper events are unsupported. Please add experimental validation on at least one physical PCB (golden and tampered), including the DTW alignment, or explicitly reposition the paper as a simulation feasibility study.
[Section IV-B, Table I, and Section VI] The class labels are keyed to component part numbers and parasitic types, not to physical instances. The 1V8 PDN contains multiple instances of C0402-CAP-ASM-1 (and likely other part numbers), so a prediction of, say, class 1 indicates that some C0402-CAP-ASM-1 has an altered ESL, not which specific capacitor on the board was tampered. The conclusion's phrase 'precise localization of tamper events' is therefore an overstatement. Either add instance-level classes or at least acknowledge that localization is limited to component type, and revise the claims accordingly.
[Section V-C and Table II] The paper reports no comparison with simpler baselines. On a synthetic dataset generated by perturbing known parameters, a k-nearest-neighbor classifier on the raw spectra, a logistic regression on selected resonance frequencies, or an SVM may achieve comparable accuracy, which would undermine the claim that the RF/SHAP combination is necessary for forensic analysis. Please add baseline comparisons and, for the XAI component, a quantitative comparison of SHAP attributions against ground-truth physical parameter changes, for example by simulating single-component perturbations and measuring feature importance.
[Section IV-B] The choice of ±10% (genuine) and ±20% (tampered) parasitic variations, and the use of 10x, 100x, and 1000x component multipliers, are ad hoc, and no sensitivity analysis is reported. The separability of the classes and hence the 96.7% accuracy may be an artifact of these ranges. Please report results for varied variation magnitudes and noise levels.

minor comments (6)

[Abstract and Section III-A] The manuscript contains typographical errors such as 'the classifier In' in the abstract and 'treat model' in Section III-A; please proofread the text.
[Table I] The genuine class 0 is shown in five rows with the same class ID; clarify that all genuine variants collapse into a single label, and specify how many physical instances of each part number exist on the PDN.
[Section V-D] The SHAP analysis uses 50 background samples, but the choice is justified only by a statement that 100 and 200 gave 'the same' results; report a quantitative comparison, such as feature rank correlation, to support this claim.
[Section III-B] The claim that random forests 'provide interpretability' is imprecise; random forests are not directly interpretable, and the paper relies on SHAP for explanation. Please rephrase.
[Figure 3] The two subfigures are referenced but the axes are not described in the caption; add axis labels and a legend so the claimed resonance shifts are visible.
[References] Reference [6] is cited as a 2024 IPFA paper; if it is a preprint or has been published in the meantime, update the citation with the full bibliographic details.

Circularity Check

0 steps flagged · score 1.0 of 10

No significant circularity: the RF/SHAP pipeline is an internal supervised benchmark on simulated |S11| traces; the unvalidated simulation-to-measurement transfer is an external-validity gap, not a derivation reduction.

full rationale

The claimed derivation chain is: simulate tamper scenarios in Ansys SIwave, label traces by component part number and parasitic modification (Table I), train a random forest on these traces, and compute SHAP values to attribute classifications to frequency features. No step exhibits a constructional equivalence between an input and a predicted output: the classifier is not fitted to a target result and then renamed as a prediction; the SHAP values are, by definition, explanations of the trained model, which is the intended use of XAI rather than a circular derivation of physical cause. The statement 'By detecting each class, we can determine what has occurred on the PCB and identify which component has been compromised' (Section IV-B) simply maps classifier outputs back to the class labels that were defined by the simulation scenarios; this is benchmark semantics, not a logically forced reduction. The principal weakness is the unvalidated DTW alignment described in the threat model (Section III-A), which would connect simulated signatures to measured VNA data but is never implemented or evaluated, so the 96.7% accuracy (Table II) and SHAP attributions may not transfer to physical PCBs. That is a domain-shift or external-validity concern, not a circularity. Existing self-citations (e.g., [5], [6]) support background claims about impedance-based tamper detection and DTW-based golden-free verification, but none is load-bearing for the central RF/SHAP result, and no uniqueness theorem is invoked to forbid alternative methods. The paper therefore does not derive its predictions from its own definitions, and the score is low.

Assumptions & free parameters 4 free parameters · 3 assumptions · 0 invented entities

The central claim rests on hand-chosen simulation parameters (variation ranges and tamper multipliers) and on the domain assumption that simulated S11 traces represent physical tampering. No new physical entities are introduced. The load-bearing transferability from simulation to measurement is assumed, not validated.

free parameters (4)

Genuine variation range = ±10% of component values and parasitics
Section IV-B: hand chosen to model manufacturing process variations; the simulated genuine class spread depends on these values.
Tampered parasitic variation range = ±20% of parasitics
Section IV-B: hand chosen for all tampered classes; affects separation between classes.
Tamper magnitude multipliers = 10, 100, and 1000 times original value
Section IV-B and Table I: hand chosen multipliers applied to capacitor values and resistor values; classification is over these discrete levels.
SHAP background sample count = 50 per class
Section V-D: default TreeSHAP sample size; authors state 100 and 200 gave identical results, so not load-bearing.

assumptions (3)

domain assumption Any tampering with a PCB or IC package changes the equivalent impedance of the power delivery network.
Background and Section III-A; this is the physical premise inherited from cited prior work [1]-[5].
domain assumption Ansys SIwave/HFSS simulations accurately reproduce the |S11| signatures of the physical PCB.
Section IV-A; the full training and test pipeline uses simulated traces, with no comparison to measured traces.
ad hoc to paper The ten tamper classes (component and parasitic type) cover the tamper events of forensic interest.
Section IV-B and Table I; classes are defined by the authors and exclude insertion, removal, and value changes outside the chosen multipliers; the paper admits unknown classes cannot be localized.

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Cite this review

Pith. "Pith review of There's Waldo: PCB Tamper Forensic Analysis using Explainable AI on Impedance Signatures." pith.science (2026). https://pith.science/paper/CPEY5PC4

@misc{pith2026250605734,
  author       = {Pith},
  title        = {Pith review of: There's Waldo: PCB Tamper Forensic Analysis using Explainable AI on Impedance Signatures},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/CPEY5PC4}},
  note         = {Machine review of arXiv:2506.05734}
}

read the original abstract

The security of printed circuit boards (PCBs) has become increasingly vital as supply chain vulnerabilities, including tampering, present significant risks to electronic systems. While detecting tampering on a PCB is the first step for verification, forensics is also needed to identify the modified component. One non-invasive and reliable PCB tamper detection technique with global coverage is the impedance characterization of a PCB's power delivery network (PDN). However, it is an open question whether one can use the two-dimensional impedance signatures for forensics purposes. In this work, we introduce a novel PCB forensics approach using explainable AI (XAI) on impedance signatures. Through extensive experiments, we replicate various PCB tamper events, generating a dataset used to develop an XAI algorithm capable of not only detecting tampering but also explaining why the algorithm makes a decision about whether a tamper event has happened. At the core of our XAI algorithm is a random forest classifier with an accuracy of 96.7%, sufficient to explain the algorithm's decisions. To understand the behavior of the classifier in the decision-making process, we utilized SHAP values as an XAI tool to determine which frequency component influences the classifier's decision for a particular class the most. This approach enhances detection capabilities as well as advancing the verifier's ability to reverse-engineer and analyze two-dimensional impedance signatures for forensics.

Figures

Figures reproduced from arXiv: 2506.05734 by the authors.

**Figure 2.** (a) Simulated design file of the PCB under test in [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗

**Figure 3.** (a) S-parameter traces corresponding to C0603-CAP-ASM-T-ESL class. (b) S-parameter traces corresponding to C0805-CAP-ASM-T-ESL class. process. In contrast, the C0603-CAP-ASM, despite having the same capacitance values, influences frequencies higher than the fundamental resonance frequency, due to its smaller physical dimensions compared to the C0805-CAP-ASM capacitors as shown in [PITH_FULL_IMAGE:figures/full_fig_p… view at source ↗

Figures from the paper (1 more)

**Figure 4.** Figure 4: SHAP values: Each dot represents a sample, with its position on the x-axis indicating the impact of a particular signature [PITH_FULL_IMAGE:figures/full_fig_p006_4.png]

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Reference graph

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Reviewed August 7, 2026 · model on record in the stance chip above.

[1] [1]

Scatterverif: Verification of electronic boards using reflection response of power distribution network,

T. Mosavirik, F. Ganji, P. Schaumont, and S. Tajik, “Scatterverif: Verification of electronic boards using reflection response of power distribution network,”ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 18, no. 4, pp. 1–24, 2022

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F. T. Werner, M. Prvulovic, and A. Zaji ´c, “Detection of recycled ICs using backscattering side-channel analysis,”IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 9, pp. 1244–1255, 2022

work page 2022

[3] [3]

PDNpulse: Sensing PCB anomaly with the intrinsic power delivery network,

H. Zhu, H. Shan, D. Sullivan, X. Guo, Y . Jin, and X. Zhang, “PDNpulse: Sensing PCB anomaly with the intrinsic power delivery network,” IEEE Transactions on Information Forensics and Security, vol. 18, pp. 3590–3605, 2023

work page 2023

[4] [4]

Counterfeit chip detection using scattering parameter analysis,

M. S. Safa, T. Mosavirik, and S. Tajik, “Counterfeit chip detection using scattering parameter analysis,” in2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), IEEE, 2023

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Impedanceverif: On-chip impedance sensing for system-level tampering detection,

T. Mosavirik, P. Schaumont, and S. Tajik, “Impedanceverif: On-chip impedance sensing for system-level tampering detection,”IACR Transactions on Cryptographic Hardware and Embedded Systems, pp. 301–325, 2023

work page 2023

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Parasitic circus: On the feasibility of golden free pcb verification,

M. Saadat Safa, P. Schaumont, and S. Tajik, “Parasitic circus: On the feasibility of golden free pcb verification,”IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2024

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James, D

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