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REVIEW 4 major objections 6 minor 34 references

FuncGNN: Learning Functional Semantics of Logic Circuits with Graph Neural Networks

T0 review · 4 major / 6 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read FuncGNN claims a lightweight GNN can match or beat heavier circuit models on two logic-level tasks while using roughly half the training time and about a third less GPU memory.

desk verdict Solid empirical architecture for AIG circuit representation; the TTDP and efficiency results hold up, but the SPP headline is within seed noise and needs multi-seed evidence. read the letter →

arxiv 2506.06787 v1 pith:HZS2ABDF submitted 2025-06-07 cs.LG cs.AR

Qiyun Zhao This is my paper
classification cs.LGcs.AR
keywords And-InverterGraphsgraphneuralnetworkscircuitrepresentationlearningsignalprobabilitypredictiontruth-tabledistanceglobalcontextnormalizationelectronicdesignautomationstructuralheterogeneity
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

FuncGNN is a graph neural network designed to represent And-Inverter Graphs (AIGs), the compact Boolean-circuit format used in synthesis and verification. The paper argues that existing AIG representation models either use expensive attention mechanisms or lose global logic context during local message passing, and that both problems worsen with the structural heterogeneity of real circuits. To fix this, FuncGNN combines three lightweight mechanisms: hybrid local aggregation that alternates GraphSAGE and GINConv layers, a gate-aware normalization that conditions feature scaling on each circuit's AND-to-NOT edge ratio, and a dense multi-layer integration that concatenates all intermediate node features before prediction. On signal probability prediction and truth-table distance prediction, the paper reports lower MAE than prior state-of-the-art models while cutting average training time by about 50.6% and GPU memory by about 32.8%. This matters because accurate, cheap circuit embeddings could make EDA tasks such as logic synthesis, equivalence checking, and property prediction faster and more scalable.

What carries the argument

The load-bearing mechanism is a three-component architecture on an AIG graph whose node features are one-hot encodings, whose edges carry a sign (+1 for AND, –1 for NOT), and whose single global prior is the circuit's AND-to-NOT edge ratio r. The Hybrid Feature Aggregation Component alternates GraphSAGE-style mean aggregation (with self-loops and a skip connection) with GINConv enhancement (an MLP applied to neighbor sums) to blend stable local patterns with expressive nonlinear structure. The Global Context Normalization Component takes standard GraphNorm and makes its per-feature scale and shift depend linearly on r through two small linear layers, adapting every normalization step to the circuit-wide gate distribution. The Multi-Layer Integration Component concatenates the outputs of all L layers and projects them through a learnable linear fusion, so shallow local features and deep global features are combined before an MLP readout. Together these components let the model absorb global logic context without attention's quadratic cost.

What would settle it

Recompute the SPP labels for the test subcircuits using exhaustive simulation where feasible and substantially larger random-vector samples elsewhere, then retrain FuncGNN and PolarGate(L=9) with identical splits and hyperparameters; if the SPP MAE gap is not positive, the paper's central accuracy-claim is unsupported. Similarly, a held-out TTDP re-run with a different node-pair sampling scheme would test whether the 18.71% improvement persists.

Watch

Extended reading notes

Core claim

On the paper's own terms, the central discovery is that a carefully wired message-passing GNN—without attention or transformers—can match and exceed the functional-representation quality of much heavier models on AIGs, provided it mixes two complementary aggregation operators, feeds each circuit's AND-to-NOT gate ratio into a conditional normalization layer, and preserves the outputs of every layer through a dense fusion. Concretely, FuncGNN reaches SPP MAE 0.0095 versus 0.0097 for the strongest baseline PolarGate(L=9) and TTDP MAE 0.1847 versus 0.2272, while cutting average training time by 50.65% and GPU memory by 32.83%. Ablations attribute most of the gain to the hybrid aggregation and multi-layer integration, with the ratio-conditioned normalization providing a smaller but consistent boost. The paper thereby claims that global structural priors can be injected cheaply through normalization rather than through attention.

Load-bearing premise

The results depend on the simulated signal probabilities being accurate enough to separate MAE values that differ by only 0.0002; 100,000 random input vectors give a Monte Carlo standard error of roughly 0.0016 for a node with signal probability 0.5, so the headline SPP gain is close to the size of the label noise.

Editorial extensions

If this is right

  • If FuncGNN's claims hold, EDA representation learning can use lightweight message-passing instead of transformers on AIGs, lowering the hardware barrier for large circuits.
  • The gate-ratio conditioning adds essentially one scalar per circuit, so the same normalization trick can be dropped into other GNN circuit models without changing their core architecture.
  • Because MAE keeps falling as depth grows from L=1 to L=9, the dense integration component suggests over-squashing is practically mitigable by feature concatenation alone.
  • The reported training-time and memory reductions make the method more attractive for very large FPGA and ASIC netlists where the heaviest attention baseline uses over 63 GB of GPU memory.
  • The extreme 5%-5%-90% data split result suggests the model can learn useful circuit representations from very few labeled examples.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The paper's two tasks both concern functional semantics, so the same architecture could plausibly transfer to gate-level delay, power, or testability prediction, where structural heterogeneity is equally pronounced, though the paper does not run those experiments.
  • The normalization prior uses only the AND-to-NOT ratio; richer global statistics such as depth distribution or reconvergence counts could be tested as alternative conditioning inputs and might further narrow the gap with attention-based models.
  • Because the SPP improvement over PolarGate(L=9) is only 0.0002 in MAE while ground-truth labels come from 100,000-vector Monte Carlo simulation, an independent re-evaluation with exact or much larger simulation would clarify how much of the claimed 2.06% gain is real versus label noise.
  • The dense concatenation grows the fused feature dimension linearly with depth, so on very deep networks a learned gating or pooling over layers may preserve the benefit at lower memory cost.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 6 minor

Summary. FuncGNN is a GNN architecture for learning representations of And-Inverter Graphs (AIGs). It combines GraphSAGE-style and GINConv-style aggregation into a hybrid feature aggregation component, a gate-aware normalization component that conditions per-feature scaling on the circuit's AND-to-NOT edge ratio, and a multi-layer integration component that concatenates intermediate layer outputs before readout. The paper evaluates the model on signal probability prediction (SPP) and truth-table distance prediction (TTDP) using subcircuits from EPFL, ITC99, IWLS, and Opencores, reporting that FuncGNN lowers SPP MAE from 0.0097 to 0.0095 and TTDP MAE from 0.2272 to 0.1847 relative to PolarGate(L=9), while reducing average training time by about 50.6% and GPU memory by about 32.8%. Additional experiments study training stability across ten seeds, performance across layer counts, and component ablations.

Significance. The proposed architecture is a reasonable and timely attempt to improve GNN-based AIG representation by combining local and global information without attention, and the resource-efficiency gains are substantial if reproducible. The dataset scale (roughly ten thousand subcircuits across four benchmark families), the ablation study, the stability analysis, and the stated release of code and data are strengths. However, the headline SPP improvement is too small relative to the reported label noise and seed variance to support the claim of consistent outperformance; the TTDP improvement (18.71%) and efficiency gains are more credible. If the SPP comparison is buttressed with paired uncertainty quantification, the paper would be a useful contribution to circuit representation learning.

major comments (4)
  1. [Section 5.1, Table 2] The claimed SPP improvement over PolarGate(L=9) is 0.0097 to 0.0095, i.e., a 0.0002 MAE gap. Section 4.2.1 states that ground-truth signal probabilities are obtained by logic simulation with up to 100,000 random input vectors; for a node with true probability 0.5, the Monte Carlo standard error is sqrt(0.25/100000) approximately 0.0016, which is roughly eight times the reported gap. Because different models may fit simulation noise differently, the observed SPP difference is not statistically established. Please report paired comparisons with confidence intervals, or use exact (or much higher-resolution) signal probability labels so that label noise is well below the claimed effect.
  2. [Section 5.3, Figure 4] The paper's own stability analysis shows that FuncGNN's SPP interquartile range across ten seeds is 0.000175 and its whisker span is 0.0004, which exceeds the 0.0002 MAE gap in Table 2, yet Table 2 reports a single MAE value without seed information. To support the claim that FuncGNN consistently outperforms all baselines, the main results should report means and standard deviations or confidence intervals, ideally using the same ten-seed protocol for all baselines with paired seeding so that comparisons account for shared data-split variance.
  3. [Equation (8)] Equation (8) states h_v^{(k+1)} = (1 + epsilon) h_v^{(k)} sum_{u in N(v)} h_u^{(k)}, which is missing the addition operator between the self-contribution and the neighbor sum. As written, the formula is dimensionally inconsistent and does not match the standard GINConv update described in the text. Please correct the equation and verify the exact implementation used in the code.
  4. [Equation (10)] The dynamic scaling and bias definition gamma_dyn = W1 * gamma * r + b1 * gamma and beta_dyn = W2 * beta * r + b2 * beta is ambiguous: it is unclear whether r enters as a scalar multiplier of gamma, whether the operation is a Hadamard product, how W1 and W2 are shaped, and what the dimensions of b1 and b2 are. Since this conditional normalization is a central contribution, please define the tensor shapes and the exact computation (for example, a FiLM-style layer with an MLP on r) so that the architecture is reproducible.
minor comments (6)
  1. [Section 4.2.1 / Table 1] The text says the dataset comprises 9,933 valid subcircuits, but the four benchmark counts in Table 1 (828 + 7,560 + 1,281 + 1,155) sum to 10,824. Please reconcile the total and define what makes a subcircuit invalid.
  2. [Equation (3)] Equation (3) uses the symbol '~' where an assignment or update is intended, and the accompanying text contains a grammatical error ('FuncGNN add a self-loop'). Please use a consistent update notation.
  3. [Equation (4)] In Equation (4) the text introduces a corrupted symbol for the edge sign and later refers to s(e_vj); please standardize the notation for AND/NOT edge signs and ensure it matches the definition s in {-1,+1}^E from Equation (1).
  4. [Equation (6)] Equation (6) refers to 'Norm' as the enhanced conditional normalization operation before Section 3.3 defines it; please add a forward reference or use a placeholder name.
  5. [Section 4.3] The initial node features are described as one-hot encodings based on node indices; because node ordering may vary across circuits, it is unclear how this representation is canonical. Please clarify the encoding or provide an ablation using structure-based initial features.
  6. [Section 5.5, Table 4] The ablation results are reported as single MAE values with no seed information or variance; given the small differences between some variants (for example, 0.0107 versus 0.0095 SPP MAE), please report repeated runs or paired comparisons.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: FuncGNN's performance claims are empirical comparisons against external baselines, and no prediction or derived quantity reduces to its own inputs.

full rationale

Walking the paper's derivation chain: the model inputs are AIG-derived features (node feature matrix, edge sign tensor, and the AND-to-NOT ratio), while the target labels are obtained independently by logic simulation for SPP and by truth-table Hamming distances for TTDP. The AND-to-NOT ratio is a structural attribute of each circuit, not a quantity derived from the prediction targets, and it is not fitted to the reported MAE values. The reported improvements (2.06% for SPP, 18.71% for TTDP) are arithmetic comparisons of MAE values in Tables 2 and 3 against external published baselines, with no equation in the paper that defines a predicted quantity in terms of the same labels or metrics it claims to estimate. There is no self-citation chain used to justify the architecture or to forbid alternative designs; the cited related works (DeepGate, DeepGate2, PolarGate, HOGA, etc.) are external baselines, and the only author-affiliated item is the code repository. The ablation study compares variants of the model against the full model, which is a standard empirical sensitivity check rather than a circular derivation. The statistical concern raised over the 0.0002 SPP MAE gap is a correctness or uncertainty-quantification issue about label noise and seed variation, not an instance of circular reasoning under the defined patterns. Therefore no circularity is present.

Assumptions & free parameters 5 free parameters · 5 assumptions · 0 invented entities

The paper's results depend on several unstated or weakly justified modeling and measurement choices: the reliability of simulation-derived labels, the choice of one-hot node-index features, the sufficiency of the AND-to-NOT ratio as a global conditioning statistic, and the representativeness of the 5% training split. These are empirical assumptions rather than mathematical axioms, but each is load-bearing for the reported gains.

free parameters (5)
  • Learnable GIN mixing coefficient epsilon = not reported (learned)
    Eq. 8 uses (1+epsilon) to weight each node's own feature; the learned value is never reported, so the final model is not fully specified.
  • Dynamic normalization coefficients W1, b1, W2, b2 = not reported (learned)
    Eq. 10 maps the AND-to-NOT ratio to per-feature gamma and beta; these parameters are central to Component 2 and are fit to data.
  • Fusion projection W_fuse, b_fuse = not reported (learned)
    Eq. 13 linearly re-weights concatenated layer outputs; values are fit to data but not reported.
  • Readout MLP weights and biases = not reported (learned)
    Eq. 14 maps fused features to signal probability; trained weights are not reported.
  • Training hyperparameters = L=3, hidden=256, dropout=0.1, lr=1e-3, weight_decay=1e-4, batch=128, patience=100
    Chosen by hand in Section 4.3; no tuning study is reported, and performance may depend on these choices.
assumptions (5)
  • domain assumption AIGs produced by ABC preserve the functional behavior of the original circuits.
    Section 3.1 converts all circuits to AIG format with ABC; if this conversion loses function, the learned semantics are not the original circuit's.
  • domain assumption Signal probabilities and truth-table distances computed with up to 100,000 random input vectors are accurate enough for training and evaluation.
    Section 4.2.1; Monte Carlo sampling error for a node with p=0.5 is roughly 0.0016, larger than the 0.0002 SPP margin reported in Table 2.
  • ad hoc to paper One-hot encodings based on node indices are a usable initial representation that generalizes across circuits with different node orderings and sizes.
    Section 4.3 states this initialization without rationale or analysis of how index vocabularies are shared across graphs.
  • ad hoc to paper The AND-to-NOT edge ratio is a sufficient global summary of each circuit for conditioning normalization.
    Section 3.3 asserts this global prior improves representation; no ablation compares it to alternative graph-level statistics such as size, depth, or joint statistics.
  • domain assumption The 0.05/0.05/0.9 split gives a fair, representative evaluation of generalization to scarce-label deployment.
    Section 4.3 uses an extreme split; the paper does not analyze potential leakage between subcircuits drawn from the same benchmark design.

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Cite this review

Pith. "Pith review of FuncGNN: Learning Functional Semantics of Logic Circuits with Graph Neural Networks." pith.science (2026). https://pith.science/paper/HZS2ABDF

@misc{pith2026250606787,
  author       = {Pith},
  title        = {Pith review of: FuncGNN: Learning Functional Semantics of Logic Circuits with Graph Neural Networks},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/HZS2ABDF}},
  note         = {Machine review of arXiv:2506.06787}
}
read the original abstract

As integrated circuit scale grows and design complexity rises, effective circuit representation helps support logic synthesis, formal verification, and other automated processes in electronic design automation. And-Inverter Graphs (AIGs), as a compact and canonical structure, are widely adopted for representing Boolean logic in these workflows. However, the increasing complexity and integration density of modern circuits introduce structural heterogeneity and global logic information loss in AIGs, posing significant challenges to accurate circuit modeling. To address these issues, we propose FuncGNN, which integrates hybrid feature aggregation to extract multi-granularity topological patterns, thereby mitigating structural heterogeneity and enhancing logic circuit representations. FuncGNN further introduces gate-aware normalization that adapts to circuit-specific gate distributions, improving robustness to structural heterogeneity. Finally, FuncGNN employs multi-layer integration to merge intermediate features across layers, effectively synthesizing local and global semantic information for comprehensive logic representations. Experimental results on two logic-level analysis tasks (i.e., signal probability prediction and truth-table distance prediction) demonstrate that FuncGNN outperforms existing state-of-the-art methods, achieving improvements of 2.06% and 18.71%, respectively, while reducing training time by approximately 50.6% and GPU memory usage by about 32.8%.

Figures

Figures reproduced from arXiv: 2506.06787 by the authors.

Figure 1
Figure 1. The overall framework of FuncGNN 2.2 Message-Passing Methods Message-passing models emphasize local propagation and structural coherence through lightweight architectures. PolarGate [18] introduced polarity embeddings and differentiable logic operators to enrich the message flow. While effective in certain tasks, it has difficulty generalizing across diverse AIG topologies. GAMORA [29] proposed a multi-task framewor… view at source ↗
Figure 2
Figure 2. The framework of Hybrid Feature Aggregation Component [PITH_FULL_IMAGE:figures/full_fig_p006_2.png] view at source ↗
Figure 3
Figure 3. NOT Proportion Distribution Histogram [PITH_FULL_IMAGE:figures/full_fig_p011_3.png] view at source ↗
Figures from the paper (2 more)
Figure 4
Figure 4. Figure 4: Stability analysis on SPP and TTDP tasks. [PITH_FULL_IMAGE:figures/full_fig_p017_4.png]
Figure 5
Figure 5. Figure 5: Comparison of different layers on SPP and TTDP tasks. [PITH_FULL_IMAGE:figures/full_fig_p017_5.png]

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Reference graph

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Reviewed August 7, 2026 · model on record in the stance chip above.