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REVIEW 2 major objections 5 minor 27 references

FeNN: A RISC-V vector processor for Spiking Neural Network acceleration

T0 review · 2 major / 5 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read FeNN, a 32-lane RISC-V vector processor implemented on an FPGA, simulates a spiking-neural-network classifier faster than an embedded GPU and the Loihi neuromorphic system while using roughly half the energy.

desk verdict A solid, reproducible FPGA SNN accelerator whose direct comparisons hold up; the Loihi headline outruns the evidence and needs a matched baseline or softer wording. read the letter →

arxiv 2506.11760 v1 pith:RP4CVTSO submitted 2025-06-13 cs.NE cs.AIcs.AR

Zainab Aizaz , James C. Knight , Thomas Nowotny This is my paper · ORCID
classification cs.NEcs.AIcs.AR
keywords spikingneuralnetworksFPGAaccelerationRISC-Vvectorprocessorstochasticroundingfixed-pointarithmeticneuromorphichardwareadaptiveleakyintegrate-and-fireSHDclassification
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims that a programmable FPGA-based vector processor can beat both an embedded GPU and a leading neuromorphic chip at simulating a spiking neural network on a real classification task. The processor, FeNN, is a 32-lane RISC-V vector co-processor that uses 16-bit fixed-point arithmetic; the paper argues that with stochastic rounding and saturating arithmetic this low precision is enough to match 32-bit floating-point accuracy for adaptive-LIF neuron dynamics. On the Spiking Heidelberg Digits classification task, a single FeNN core is reported to run faster per timestep than an embedded GPU and a similar RSNN running on Loihi, at about half the GPU's total inference energy. If the comparison holds, FeNN is evidence that general-purpose programmable vector processing, not fixed-function neuromorphic hardware, can capture SNN efficiency benefits while remaining easy to integrate with ordinary computers.

What carries the argument

The load-bearing mechanism is a 16-bit fixed-point vector pipeline with stochastic rounding and saturation. FeNN's 32 lanes operate on vectors of 16-bit values with a minimal instruction set (vector add/subtract/multiply, vector load/store, scalar-vector moves, random-number generation, comparison masks, and masked select), and its local memories are wide enough to hold an entire vector in one cycle. Stochastic rounding is realized by folding an N-bit random value into the DSP multiply-accumulate so that the fixed-point right shift rounds with unbiased error, following the MAC formulation of rounding; saturation is applied on additions and subtractions so that overflow clamps rather than wraps. Together these keep the adaptive threshold variable and membrane voltage of ALIF neurons from degrading to zero or exploding, which is what lets the accelerator use 16-bit arithmetic without losing accuracy.

What would settle it

Run the exact same trained ALIF RSNN, with identical weights, neuron parameters, spike encoding, and model size, on FeNN, on the embedded GPU, and on Loihi, measuring per-timestep latency and total inference energy. If Loihi's per-timestep time on the identical model is at or below FeNN's, the claimed speed advantage over neuromorphic hardware fails.

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Extended reading notes

Core claim

The central discovery the paper pursues is that the low arithmetic intensity of SNN simulation can be exploited by a soft vector processor rather than by custom neuromorphic silicon. FeNN pairs a small RISC-V scalar core with a tightly coupled 32-lane SIMD vector unit that operates entirely on 16-bit fixed-point vectors. Two numerical details make this work: stochastic rounding, implemented by adding random bits inside the DSP multiply-accumulate before the fixed-point shift, removes the bias of truncation; and saturation prevents state variables from wrapping around when inputs exceed their calibrated range. With these, FeNN reproduces ALIF neuron dynamics with NRMSE close to a 64-bit floating-point reference, and a trained 256-hidden-neuron RSNN reaches 79.50 ± 0.44% test accuracy on SHD, statistically indistinguishable from 79.6% achieved in 32-bit floating point. The paper further reports that a single FeNN core simulates each timestep in less time than an embedded GPU and than the comparable Loihi implementation, using about half the energy of the GPU.

Load-bearing premise

The headline speed advantage over Loihi rests on the assumption that the cited Loihi result used a comparably sized and tuned network with the same spike encoding; the paper compares against a 'similar' RSNN, not the identical model, so an apples-to-apples re-run could shrink or reverse the gap.

Editorial extensions

If this is right

  • A single FeNN core can simulate an SNN classifier faster per timestep than the embedded GPU evaluated and than the comparable Loihi implementation.
  • The same FeNN run uses about half the energy of the embedded GPU for full SHD inference, and about a third of the embedded CPU's energy.
  • 16-bit fixed-point arithmetic with stochastic rounding and saturation is numerically sufficient for this adaptive-LIF RSNN, matching 32-bit floating-point accuracy.
  • Because FeNN is a programmable vector processor rather than fixed-function logic, new SNN models can be deployed by writing RISC-V instructions without re-synthesizing the FPGA.
  • The reported low per-lane hardware utilisation suggests the design can scale to larger multi-core FPGA implementations.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The same stochastic-rounding-plus-saturation recipe could apply to other iterative low-precision solvers, such as ODE integration or sparse graph algorithms, where fixed-point underflow or overflow corrupts long-running simulations.
  • The paper's per-synaptic-event energy of 8 nJ sits above the latest neuromorphic ASICs, so FeNN's real value proposition is likely programmability and host integration rather than raw energy efficiency.
  • The speed comparison against Loihi relies on a published baseline for a 'similar' RSNN rather than the identical model; a direct head-to-head with the same weights, encoding, and model size would be the decisive test.
  • If the planned DMA and multi-core scaling succeed, the bottleneck should shift from instruction issue to memory bandwidth, implying the current speedups are most pronounced for models that fit entirely in on-chip memory.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

2 major / 5 minor

Summary. The paper presents FeNN, a RISC-V-based vector soft processor implemented on an FPGA and tightly coupled to a CV32E40X scalar core, intended for low-arithmetic-intensity spiking neural network (SNN) simulation. The authors describe the architecture, a stochastic rounding and saturation scheme for 16-bit fixed-point arithmetic, and an on-chip random number generator. They validate the numerical approach on ALIF neuron simulations and then deploy a 256-hidden-neuron ALIF RSNN classifier on the Spiking Heidelberg Digits (SHD) dataset, reporting 79.50±0.44% test accuracy, close to a 32-bit floating-point GeNN reference. They compare FeNN's per-timestep simulation time and energy against a Jetson Orin Nano running GeNN and against a 'similar' RSNN on Intel Loihi reported in Rao et al. The headline claim is that a single FeNN core simulates an SNN classifier faster than both an embedded GPU and Loihi, at roughly half the energy of the GPU.

Significance. If the comparison were fully supported, FeNN would be a meaningful demonstration that a programmable, FPGA-based soft vector processor can match or beat an embedded GPU and a neuromorphic ASIC on a realistic SNN classification task, while retaining programmability and integration with standard host systems. The paper has several concrete strengths: the FeNN-versus-Jetson comparison is measured directly on the same SHD model; the numerical accuracy experiments with stochastic rounding and saturation are quantitative and include error metrics; the design details (instruction set, pipeline, RNG, memory organization) are described in enough depth to be reproducible; and the authors state that code and a bitstream are available. The main weakness is that the 'faster than Loihi' half of the headline is not supported by a matched experiment, which materially weakens the strongest claim.

major comments (2)
  1. [III-D, Fig. 4B; Abstract] The abstract and conclusion claim that a single FeNN core can simulate an SNN classifier faster than both an embedded GPU and Loihi. The GPU half of this claim is supported by a direct measurement of the same SHD model using GeNN on a Jetson Orin Nano. The Loihi half is not: it relies on the time reported by Rao et al. [22] for a 'similar ALIF-based RSNN classifier', with no evidence that the network size, spike encoding, synaptic event count, or Loihi hardware mapping match the FeNN workload. Without a matched workload, the speed advantage over Loihi is unverified; if the Rao et al. network is smaller or produces fewer synaptic events, the comparison could be reversed. Please either run the identical model on Loihi or revise the headline claim to state what the data actually show (for example, 'faster than the embedded GPU and comparable to a similar Loihi implementation').
  2. [III-C, Section III-D] The numerical-precision claim is central to the paper, yet the statement that FeNN's SHD accuracy (79.50±0.44%) is an 'insignificant difference' from the 32-bit float GeNN accuracy (79.6%) is not backed by a statistical test, and the paper does not report how many independent runs the GeNN number represents. Please provide the number of runs for both systems and give a confidence interval or a significance test for the accuracy difference; without this, the equivalence of the fixed-point and floating-point implementations is asserted rather than demonstrated.
minor comments (5)
  1. [Fig. 3 caption] The caption for Figure 3 contains a long run of corrupted '/uni00000013/...' text that obscures the intended caption and appears to be an encoding artifact; this should be fixed before publication.
  2. [Section III, repository URL] The repository URL is typeset as 'https://github.com/neworderofjamie/riscv ise' with a space and appears truncated; please provide the complete, working URL.
  3. [Table I] Table I reports per-lane LUT and FF counts for SNAVA, GaBAN, and FeNN, but the designs differ in vector width, clock frequency, and supported instruction sets. Without an explanation of how these factors are normalized or why the per-lane comparison is fair, the resource-efficiency conclusion is hard to interpret.
  4. [Introduction, Section III-D] The introduction states that FeNN runs 'twice as fast as the same model running on an embedded GPU', while Figure 4B plots per-timestep time. Please clarify whether the 2× figure refers to total wall-clock inference time, per-timestep latency, or simulation throughput, and ensure the terminology is consistent throughout.
  5. [Section III-E] The energy comparison is measured at the mains socket with a consumer power meter and OCR, and 'simulation energy' is obtained by removing idle power and data-copy time. Please specify how the idle power was measured for each board, whether the two systems ran comparable OS and display stacks during the experiment, and what fraction of total energy the removed components account for, since the energy-per-synaptic-event numbers are sensitive to these choices.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: the central claims are empirical benchmark measurements and independent numerical validations, not derivations from fitted inputs.

full rationale

The paper's core claims are measured outcomes: FeNN's SHD classification accuracy is compared against the external SHD test set and a 32-bit floating-point GeNN reference, the stochastic-rounding bit-error distributions are compared with those of Hopkins et al., ALIF fixed-point behavior is compared with 64-bit floating-point simulations on FeNN itself, and the speed and energy results are direct timing and mains-power measurements on the Kria KV260 and Jetson Orin Nano. No parameter is fitted to produce the headline speed or energy numbers. The Loihi comparison relies on an external published baseline for a 'similar' network rather than a same-model run, which is a benchmarking-fairness limitation but not a circular step, since the cited result is not derived from FeNN and the paper does not rename or redefine it as its own prediction. The only author-linked component is the use of GeNN as the GPU baseline; this is a standard, externally visible simulator and the comparison is an empirical measurement, so citing one's own simulator does not make the claim equivalent to its inputs. The manuscript is self-contained against external benchmarks, so the circularity score is 0.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

No parameters are fitted to the headline result. The ALIF constants and S0.15 arithmetic format are design and domain choices inherited from earlier ALIF and stochastic-rounding work, not quantities tuned to make FeNN look fast. The measurable claims are direct hardware benchmarks against an external dataset and a published baseline, so the circularity burden is low.

assumptions (4)
  • domain assumption ALIF dynamics in Equations (1)-(3) with alpha=exp(-1/20), beta=0.0174, rho=exp(-1/2000), and Vth=0.6 describe the benchmark model and match the floating-point reference.
    Section II-D; the accuracy and numerics comparisons presuppose that this neuron model is the correct target and that stochastic rounding and saturation do not change model semantics.
  • domain assumption The Spiking Heidelberg Digits test set and a trained 256-neuron recurrent ALIF network form a representative SNN classification benchmark.
    Section III-D; the benchmark validity of SHD and the trained network is assumed, not derived.
  • domain assumption Xoroshiro32++ produces random bits of sufficient quality for stochastic rounding and Poisson sampling.
    Section II-B2; the stochastic rounding mechanism relies on the generated random bits having mean near 0.5 and adequate distribution quality at 16-bit precision.
  • domain assumption Wall-socket power measurements, integrated and with idle/initialization removed, give a fair relative comparison of inference energy.
    Section III-E; the energy comparison assumes the mains-socket accounting captures the relevant differences between FeNN and the Jetson systems.

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Cite this review

Pith. "Pith review of FeNN: A RISC-V vector processor for Spiking Neural Network acceleration." pith.science (2026). https://pith.science/paper/RP4CVTSO

@misc{pith2026250611760,
  author       = {Pith},
  title        = {Pith review of: FeNN: A RISC-V vector processor for Spiking Neural Network acceleration},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/RP4CVTSO}},
  note         = {Machine review of arXiv:2506.11760}
}
read the original abstract

Spiking Neural Networks (SNNs) have the potential to drastically reduce the energy requirements of AI systems. However, mainstream accelerators like GPUs and TPUs are designed for the high arithmetic intensity of standard ANNs so are not well-suited to SNN simulation. FPGAs are well-suited to applications with low arithmetic intensity as they have high off-chip memory bandwidth and large amounts of on-chip memory. Here, we present a novel RISC-V-based soft vector processor (FeNN), tailored to simulating SNNs on FPGAs. Unlike most dedicated neuromorphic hardware, FeNN is fully programmable and designed to be integrated with applications running on standard computers from the edge to the cloud. We demonstrate that, by using stochastic rounding and saturation, FeNN can achieve high numerical precision with low hardware utilisation and that a single FeNN core can simulate an SNN classifier faster than both an embedded GPU and the Loihi neuromorphic system.

Figures

Figures reproduced from arXiv: 2506.11760 by the authors.

Figure 1
Figure 1. Block diagram of FeNN, tightly coupled to CV32E40X RISC-V core. [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. (A) Histogram of 3200 Poisson variates sampled from distribution with λ = 5, generated on FeNN. Horizontal lines indicate Probability Mass Function of distribution. (B) Histograms showing the bit error distribution of 21 760 random S0.15 multiplication operations with (top) round-to-zero (middle) round-to-nearest and (bottom) stochastic rounding (after Hopkins et al. [6]). read from memory are written back to the re… view at source ↗
Figure 3
Figure 3. ALIF neuron simulations (A) ALIF stimulated with two periods of Poisson spiking input, separated by a period of low background rate, simulated using 64 bit floating point (B) Detail from the shaded area in A) comparing 16 bit fixed point (solid lines) against 64 bit floating point (dashed lines) using standard round-to-zero (top) and stochastic rounding (bottom). (C) ALIF stimulated by Poisson spiking input with inc… view at source ↗
Figures from the paper (1 more)
Figure 4
Figure 4. Figure 4: SHD inference running on FeNN (A) Raster plot of input and hidden neuron activity during one example. (B) Comparison of average time (over the whole test set) taken to simulate a single SNN timestep on FeNN with Jetson Orin Nano using GeNN (batch size=1) [21] and simil…

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Reference graph

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