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Intrinsic Annealing in a Hybrid Memristor-Magnetic Tunnel Junction Ising Machine

T0 review · 4 major / 4 minor · reviewed 2026-08-15 · deepseek-v4-flash

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Pith's one-line read A single voltage ramp anneals a hybrid nanodevice Ising machine

desk verdict A credible first hybrid memristor-SMTJ Ising machine with a genuinely new intrinsic-annealing idea, but the annealing claim needs a baseline and a distribution check before it is fully secured. read the letter →

arxiv 2506.14676 v1 pith:3JSHUJDS submitted 2025-06-17 cs.ET

Mohammed Akib Iftakher , Hugo Levices , Kamel-Eddine Harabi , Adrien Renaudineau , Mathieu-Coumba Faye , Corentin Bouchard , Florian Disdier , Bernard Viala
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Elisa Vianello Philippe Talatchian Kevin Garello Damien Querlioz Louis Hutin
This is my paper · ORCID
classification cs.ET
keywords IsingmachinememristorcrossbarstochasticmagnetictunneljunctionintrinsicannealingsimulatedMAX-CUTgraphcoloringprobabilisticcomputing
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper reports a hardware Ising machine that unites two nanotechnologies in one optimization loop: a memristor crossbar stores the spin-spin couplings, and a stochastic magnetic tunnel junction (SMTJ) supplies the noisy spin updates. Its central proposal is that annealing needs no separate controller, because the very read voltage that drives the crossbar also biases the SMTJs; raising this voltage makes the spin statistics more deterministic, which is equivalent to lowering the machine's temperature. On this basis the paper claims its prototype consistently reaches the global optimum of a 24-vertex weighted MAX-CUT instance and a 10-vertex, three-color graph-coloring problem at room temperature and zero magnetic field. The reader should care because the approach removes the supervisory annealing circuitry that other Ising machines require and places both device types in CMOS back-end-of-line layers, pointing toward vertical integration.

What carries the argument

The load-bearing mechanism is the voltage-controlled sigmoid of an SMTJ (a magnetic tunnel junction whose free-layer magnetization fluctuates randomly under thermal noise) combined with the analog multiply-and-accumulate current of a memristor crossbar. Feeding the crossbar current into the SMTJ through the conversion $V_{\mathrm{MTJ}} = V_{0.5} + I_{\mathrm{MAC}} R_\alpha$ turns each spin update into a physical Gibbs sample, and setting $V_{\mathrm{read}} \propto \beta$ turns the same circuit into an annealer. The paper also relies on a RESET-based program-and-verify memristor programming scheme, whose month-scale conductance stability is what lets a programmed problem remain solvable without reprogramming.

What would settle it

Hold $V_{\mathrm{read}}$ constant during runs on a small coupling matrix and record the histogram of visited spin configurations; if the energy distribution does not match the Boltzmann law with a single temperature proportional to $1/V_{\mathrm{read}}$, or if the measured switching probability deviates from the sigmoid of Eq. (5) at read voltages below roughly 40 mV, then the voltage ramp is not a controlled annealing schedule. A simpler device-level check is to fix all spins and measure whether the crossbar's MAC current remains linear in $V_{\mathrm{read}}$ down to the voltages used for exploration.

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Extended reading notes

Core claim

On the paper's own terms, the discovery is a device-level identity: when the crossbar's multiply-and-accumulate current is converted to an SMTJ voltage, the resulting switching probability takes exactly the Gibbs-sampling sigmoid form $P_{\mathrm{AP}} = \frac{1}{1+\exp(-\beta K V_{\mathrm{ref}} R_\alpha (\sum_j J_{ij} s_j + h_i))}$. Because the read voltage is set as $V_{\mathrm{read}} = \beta V_{\mathrm{ref}}$, a single monotonic ramp of the read voltage implements simulated annealing: low $V_{\mathrm{read}}$ keeps the junction near its 50% switching point for broad exploration, and high $V_{\mathrm{read}}$ pushes the switching probability toward a deterministic decision. The authors support the claim experimentally with two optimization benchmarks, each solved to its global optimum in repeated trials using different SMTJs.

Load-bearing premise

Everything rests on the device sigmoid and the crossbar's MAC current combining to reproduce the Gibbs-sampling update at every stage of the anneal — in particular, the SMTJ switching probability must keep its fixed sigmoid shape and the memristor current must stay linear in $V_{\mathrm{read}}$ even at the low read voltages used in the high-temperature phase.

Editorial extensions

If this is right

  • Annealing reduces to a single global voltage ramp, so the machine needs only two shared DACs rather than per-spin schedule logic.
  • The MAC current feeds directly into the SMTJ without an analog-to-digital converter, removing a major energy and latency cost from the critical path.
  • Because both memristors and SMTJs sit in the CMOS back end of line, the paper's integration roadmap — interposer, hybrid bonding, monolithic 3-D — could shrink interconnect lengths toward the nanosecond SMTJ switching time.
  • The demonstrated 130 ns SMTJ sampling, combined with parallel Gibbs-sampling extensions, implies that a fully integrated machine could approach nanosecond-scale parallel spin updates.
  • A programmed coupling matrix retains usable conductance values for at least a month, so a solved problem can be rerun without reprogramming the array.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the voltage ramp is a faithful temperature schedule, the same hardware should also be a Boltzmann sampler: fixing $V_{\mathrm{read}}$ and histogramming sampled spin configurations should give energies distributed as $e^{-\beta H}$, a distributional check the paper does not report.
  • The intrinsic mechanism suggests a natural replica-exchange protocol: toggling $V_{\mathrm{read}}$ per replica could emulate parallel tempering without any thermal control, which the paper mentions only as a future direction.
  • The equivalence in Eq. (13) depends on linear MAC currents, so pushing the same device stack toward a sampler rather than an optimizer — holding $V_{\mathrm{read}}$ fixed and collecting samples — would be a direct test of how far the Gibbs-sampling analogy extends.
  • Replacing the single prototype SMTJ with one p-bit per row, as in the paper's projected circuit, should let chromatic or asynchronous parallel Gibbs sampling exploit the same voltage-controlled anneal.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 4 minor

Summary. The manuscript reports a hybrid Ising machine in which a hafnium-oxide memristor crossbar implements the coupling matrix and stochastic magnetic tunnel junctions (SMTJs) implement probabilistic spins. The central claim is that, because the same read voltage that drives the crossbar also biases the SMTJs, raising Vread decreases the SMTJ switching probability and thereby implements an intrinsic simulated-annealing schedule with essentially no extra circuitry. The authors derive Eq. (13) to show that the hardware update matches Gibbs sampling with inverse temperature β = Vread/Vref, and they report that the prototype solves a 24-vertex weighted MAX-CUT and a 10-vertex three-color graph-coloring problem, with global optimality checked by exhaustive enumeration. A 30-day retention study of the memristor conductances is also presented.

Significance. If the intrinsic annealing mechanism is correct, the work is significant: it would be the first demonstration of annealing without an external controller in a hybrid nanodevice Ising machine, and both constituent technologies are CMOS-back-end compatible, suggesting a scalable path to 3D-integrated optimizers. The paper deserves credit for checking the final configurations against an exhaustive solver, for testing each benchmark with three different SMTJs, and for explicitly discussing the limitations of the low-voltage regime. However, the central mechanistic claim is not directly validated by the experiments, as detailed below.

major comments (4)
  1. [Methods, 'Annealing schedule', Eq. (13)] The claim that the Vread ramp implements controlled annealing rests on Eq. (13), which assumes the SMTJ sigmoid of Eq. (5) has constant K and V0.5, the MAC of Eq. (4) is perfectly linear, and the voltage conversion of Eq. (6) holds with a fixed Rα. The Methods passage explicitly states that at low Vread 'memristor conductance can be partly nonlinear' and that schedules are 'tuned empirically.' No measurement is reported of the actual switching probability of the SMTJ as a function of the combined MAC current during the optimization runs, nor of the sampled distribution against the Boltzmann law of Eq. (2). Consequently, the experiments do not establish that the voltage ramp is a calibrated temperature schedule; they only show that this particular stochastic search finds the optimum on two small instances.
  2. [Solving a weighted MAX-CUT instance; Solving a graph coloring instance with bias terms] The paper does not report any control experiments, such as fixed-voltage operation, an inverted schedule, or a schedule with random voltage jumps. Without such controls, the observed convergence cannot be attributed to the gradual lowering of effective temperature rather than to the final, near-deterministic regime or to the particular stochastic dynamics. Since the schedules are per-task tuned from prior simulations, the success of the two benchmarks is also consistent with a tuned stochastic search that is not performing simulated annealing in the intended sense.
  3. [Figs. 3b and 4b] Only three independent runs are reported per benchmark, each with a different SMTJ. With n=3 the statement that the prototype 'consistently reaches the global optimum' is statistically weak, especially given the documented die-to-die SMTJ variability in Fig. 2d,e; a few additional trials or a success-probability estimate with confidence bounds would be needed to support the robustness claim.
  4. [Fig. 4f and main text] The one-month rerun of the graph-coloring experiment used a software-emulated SMTJ sigmoid, not the physical SMTJ, because the probe station was unavailable. The text discloses this, but the sentence 'the solver still converges to the optimal coloring' could mislead readers into thinking the full hybrid machine was re-validated after one month. This experiment only demonstrates memristor conductance retention, so the claim should be scoped accordingly.
minor comments (4)
  1. [Fig. 2 caption] The word 'charasteristic' is a typo and should be 'characteristic'; similarly 'represesents' in Fig. 2b should be 'represents'.
  2. [Methods, 'Fabrication of the stochastic magnetic tunnel junctions'] The word 'Muli-layer' should be 'Multi-layer' in the description of the SAF structure.
  3. [Mapping graph coloring to the Ising Hamiltonian] The phrase 'it would possible to use differential memristor structures' is missing 'be'; it should read 'it would be possible'.
  4. [Eq. (2) and annealing schedule] The pseudo-temperature T is introduced via β = 1/T without units or a precise definition of its scale; since the hardware maps β to Vread/Vref, a brief statement connecting the dimensionless units of T to the voltage ratio would improve interpretability.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: Eq. (13) is a direct composition of independently measured device equations, and the optimization results are verified against exhaustive software search.

full rationale

The paper's central derivation is Eq. (13), obtained by substituting the memristor MAC relation (Eq. 4), the measured SMTJ sigmoid (Eq. 5), and the voltage conversion (Eq. 6) into the annealing schedule definition Vread = beta Vref (Eq. 12). Each ingredient is independently characterized: memristor conductances are programmed and verified (Fig. 2a-b), and the SMTJ sigmoid is fitted to measured switching statistics (Fig. 1e and Methods). The result is an algebraic consequence of those measured device equations, not a quantity that was used to define them. The fitted parameters K and V0.5 describe the device; they do not encode the benchmark solution. The optimization outcomes are checked against an exhaustive solver, so the experimental claim is not baked into the inputs. The self-citations (e.g., refs. 59-62) concern fabrication and programming procedures, not the load-bearing mathematical or experimental claim. The Methods passage admitting that annealing schedules are 'tuned empirically' and that low-Vread conductance 'can be partly nonlinear' is a validation limitation, as is the absence of a distributional check against the intended Boltzmann law; but these are empirical-strength concerns, not circularity. No step reduces by construction to a fitted parameter renamed as a prediction, and no uniqueness theorem or ansatz is imported from the authors' prior work.

Assumptions & free parameters 4 free parameters · 4 assumptions · 0 invented entities

No new physical entities are introduced; both devices are existing nanotechnologies. The free parameters are the device sigmoid fit (K, V0.5), the design constant R_alpha, and the per-task annealing schedules. The central mapping to Gibbs sampling relies on assumptions about device linearity and stationarity that the paper does not directly verify.

free parameters (4)
  • K (SMTJ sigmoid slope) = Not reported in text
    Fitted to switching probability vs. voltage data in Eq. (5); the effective inverse temperature in Eq. (13) is proportional to K, so the device fit sets the temperature scale.
  • V0.5 (SMTJ sigmoid midpoint) = Not reported in text
    Fitted parameter in Eq. (5); used as the operating-point bias in Eq. (6) so that zero field maps to P=0.5.
  • R_alpha (MAC-to-SMTJ voltage conversion) = 2 * (R_mtj + R_plus)
    Chosen design constant in Eq. (6); sets the mapping from crossbar current to SMTJ voltage and therefore the effective beta scale, though the schedule is re-tuned empirically.
  • Annealing schedule (Vread start, Vread end, step) = 30-40 mV to about 250 mV; temperature changed every 50 iterations; per-task values in Figs. 3b and 4b
    Chosen based on prior simulations of the Ising machine (Methods, 'Annealing schedule'), so the demonstration uses task-specific hand-tuned schedules rather than a fixed general protocol.
assumptions (4)
  • domain assumption The SMTJ switching probability follows the sigmoid of Eq. (5) with stable K and V0.5 throughout the experiments.
    Eq. (5) is an empirical fit to 1000-pulse statistics; the Gibbs-sampling mapping of Eq. (13) assumes this curve is stationary during the anneal.
  • domain assumption The memristor crossbar performs linear multiply-and-accumulate: I_i = (sum_j J_ij s_j + h_i) Vread (Eq. 4).
    Kirchhoff current summation with programmed conductances is assumed linear across the full Vread range, including the low-voltage high-temperature phase where conductance nonlinearity is acknowledged as a concern.
  • domain assumption Sequential Gibbs sampling with the effective beta of Eq. (13) explores the Ising Hamiltonian's low-energy configurations.
    The paper assumes the stochastic flips of the SMTJ behave like thermal Boltzmann sampling; this is the physical basis of p-bit computing and is not independently verified here beyond reaching the known optima.
  • ad hoc to paper Simulated annealing with the empirically chosen linear schedules reaches the global optimum on these instances.
    Classical annealing guarantees apply to infinitely slow schedules; the paper uses short linear schedules (changed every 50 iterations) chosen via simulation, so convergence is an empirical property of the tested graphs, not a theorem.

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Cite this review

Pith. "Pith review of Intrinsic Annealing in a Hybrid Memristor-Magnetic Tunnel Junction Ising Machine." pith.science (2026). https://pith.science/paper/3JSHUJDS

@misc{pith2026250614676,
  author       = {Pith},
  title        = {Pith review of: Intrinsic Annealing in a Hybrid Memristor-Magnetic Tunnel Junction Ising Machine},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/3JSHUJDS}},
  note         = {Machine review of arXiv:2506.14676}
}
read the original abstract

Hardware implementations of the Ising model offer promising solutions to large-scale optimization tasks. In the literature, various nanodevices have been shown to emulate the spin dynamics for such Ising machines with remarkable effectiveness. Other nanodevices have been shown to implement spin-spin coupling with compact footprint and minimal energy dissipation. However, an ideal Ising machine would associate both types of nanodevices, and they must operate synergistically to support annealing: a progressive reduction of machine stochasticity that allows it to settle to energy minimum. Here, we report an Ising machine that combines two nanotechnologies: memristor crossbar -- storing multi-level couplings -- and stochastic magnetic tunnel junction (SMTJ), acting as thermally driven spins. Because the same read voltage that interrogates the crossbar also biases the SMTJs, increasing this voltage automatically lowers the effective temperature of the machine, providing an intrinsic, nearly circuit-free annealing technique. Operating at zero magnetic field, our prototype consistently reaches the global optimum of a 24-vertex weighted MAX-CUT and a 10-vertex, three-color graph-coloring problem. Given that both nanotechnologies in our demonstrator are CMOS-integrated, this approach is compatible with advanced 3D integration, offering a scalable pathway toward compact, fast, and energy-efficient large-scale Ising solvers.

Figures

Figures reproduced from arXiv: 2506.14676 by the authors.

Figure 1
Figure 1. Hybrid memristor-SMTJ Ising-machine architecture and device primitives. a System-level concept: A hafnium-oxide memristor crossbar computes the weighted sum of neighbouring spins, while a stochastic magnetic tunnel junction (SMTJ) converts that current into a probabilistic spin update. b Die micrograph of the 32×64 memristor crossbar integrated above CMOS. c Scanning Electron Microscopy (SEM) image highlighting the … view at source ↗
Figure 2
Figure 2. Device-level characterisation underpinning reliable, analog coupling and stochastic spins. a Histograms of programmed memristor state, with target conductance states (0 µS, 33 µS, 66 µS, 99 µS, and 140 µS) after programming. b Measured multiply-and-accumulate (MAC) output current versus expected value, validating linear summation of Jij and hi (see Methods). The full line represesents y=x, as a guide for the eyes. E… view at source ↗
Figure 3
Figure 3. Hardware solution of a 24-node weighted MAX-CUT instance. a Conductance map programmed into the memristor array, implementing a three-level Jij matrix (33 µS, 66 µS, 99 µS), and hi = 0). b Linear temperature schedule (1/β) applied by ramping the read voltage Vread and evolution of Ising energy during 7200 sequential spin updates; the system escapes local minima early and converges to the optimum cut predicted by a s… view at source ↗
Figures from the paper (1 more)
Figure 4
Figure 4. Figure 4: Graph-coloring benchmark solved with the same hardware. a One-hot encoding of a ten-node, three-color problem mapped to a sparse 30×30 memristor matrix (140 µS negative couplings) plus a 70 µS positive bias column. b Linear temperature schedule (1/β) applied by ramping…

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Works this paper leans on

60 extracted references · 58 canonical work pages

  1. [1]

    Crystal statistics

    Onsager, L. Crystal statistics. i. a two-dimensional model with an order-disorder transition.Phys. review 65, 117 (1944). 2.Lucas, A. Ising formulations of many np problems.Front. Phys.2(2014)

    work page 1944

  2. [3]

    & Roychowdhury, J

    Wang, T. & Roychowdhury, J. Oscillator-based ising machine.arXiv preprint arXiv:1709.08102(2017)

    arXiv 2017

  3. [4]

    S., Paik, H., Schlom, D

    Dutta, S., Khanna, A., Assoa, A. S., Paik, H., Schlom, D. G., Toroczkai, Z., Raychowdhury, A. & Datta, S. An ising hamiltonian solver based on coupled stochastic phase-transition nano-oscillators.Nat. Electron.4, 502–512 (2021)

    work page 2021

  4. [5]

    & Roychowdhury, J

    Wang, T., Wu, L., Nobel, P. & Roychowdhury, J. Solving combinatorial optimisation problems using oscillator based ising machines.Nat. Comput.20, 287–306 (2021)

    work page 2021

  5. [6]

    & Kim, C

    Ahmed, I., Chiu, P.-W., Moy, W. & Kim, C. H. A probabilistic compute fabric based on coupled ring oscillators for solving combinatorial optimization problems.IEEE J. Solid-State Circuits56, 2870–2880 (2021)

    work page 2021

  6. [7]

    Moy, W., Ahmed, I., Chiu, P.-w., Moy, J., Sapatnekar, S. S. & Kim, C. H. A 1,968-node coupled ring oscillator circuit for combinatorial optimization problem solving.Nat. Electron.5, 310–317 (2022)

    work page 2022

  7. [8]

    & Hofmann, K

    Graber, M. & Hofmann, K. An integrated coupled oscillator network to solve optimization problems. Commun. Eng.3, 116 (2024)

    work page 2024

  8. [9]

    K., Mallick, A., Truesdell, D

    Bashar, M. K., Mallick, A., Truesdell, D. S., Calhoun, B. H., Joshi, S. & Shukla, N. Experimental demonstration of a reconfigurable coupled oscillator platform to solve the max-cut problem.IEEE J. on Explor. Solid-State Comput. Devices Circuits6, 116–121 (2020). 16/22

    work page 2020

Show all 60 references
  1. [10]

    & Todri-Sanial, A

    Delacour, C., Carapezzi, S., Boschetto, G., Abernot, M., Gil, T., Azemard, N. & Todri-Sanial, A. A mixed-signal oscillatory neural network for scalable analog computations in phase domain.Neuromorphic Comput. Eng.3, 034004 (2023)

    2023

  2. [11]

    & Hutin, L

    Bazzi, A., Hardy, E., Ballester, J., Badets, F. & Hutin, L. Optimizing with phases: design and application space assessment for networks of phase-locked ring oscillators. In2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS), 602–606 (IEEE, 2024)

    2024

  3. [12]

    J., Linares-Barranco, B., Todri-Sanial, A., Indiveri, G

    Maher, O., Jiménez, M., Delacour, C., Harnack, N., Núñez, J., Avedillo, M. J., Linares-Barranco, B., Todri-Sanial, A., Indiveri, G. & Karg, S. A cmos-compatible oscillation-based vo2 ising machine solver. Nat. Commun.15, 3334 (2024)

    2024

  4. [13]

    A., Pervaiz, A

    Borders, W. A., Pervaiz, A. Z., Fukami, S., Camsari, K. Y., Ohno, H. & Datta, S. Integer factorization using stochastic magnetic tunnel junctions.Nature573, 390–393 (2019)

    2019

  5. [14]

    A., Camsari, K

    Kaiser, J., Borders, W. A., Camsari, K. Y., Fukami, S., Ohno, H. & Datta, S. Hardware-aware in situ learning based on stochastic magnetic tunnel junctions.Phys. Rev. Appl.17, 014016 (2022)

    2022

  6. [15]

    A., Grimaldi, A., Carpentieri, M., Theogarajan, L., Martinis, J

    Aadit, N. A., Grimaldi, A., Carpentieri, M., Theogarajan, L., Martinis, J. M., Finocchio, G. & Camsari, K. Y. Massively parallel probabilistic computing with sparse ising machines.Nat. Electron.5, 460–468 (2022)

    2022

  7. [16]

    In2022 International Electron Devices Meeting (IEDM), 36.1.1–36.1.4 (IEEE, 2022)

    Yin, J.et al.Scalable ising computer based on ultra-fast field-free spin orbit torque stochastic device with extreme 1-bit quantization. In2022 International Electron Devices Meeting (IEDM), 36.1.1–36.1.4 (IEEE, 2022)

    2022

  8. [17]

    S., Kobayashi, K., Cao, Q., Selcuk, K., Hu, T., Niazi, S., Aadit, N

    Singh, N. S., Kobayashi, K., Cao, Q., Selcuk, K., Hu, T., Niazi, S., Aadit, N. A., Kanai, S., Ohno, H., Fukami, S.et al.Cmos plus stochastic nanomagnets enabling heterogeneous computers for probabilistic inference and learning.Nat. Commun.15, 2685 (2024)

    2024

  9. [18]

    Energy-efficient superparamagnetic ising machine and its application to traveling salesman problems

    Si, J., Yang, S., Cen, Y., Chen, J., Huang, Y., Yao, Z., Kim, D.-J., Cai, K., Yoo, J., Fong, X.et al. Energy-efficient superparamagnetic ising machine and its application to traveling salesman problems. Nat. Commun.15, 3457 (2024)

    2024

  10. [19]

    A., Chowdhury, S

    Nikhar, S., Kannan, S., Aadit, N. A., Chowdhury, S. & Camsari, K. Y. All-to-all reconfigurability with sparse and higher-order ising machines.Nat. Commun.15, 8977 (2024)

    2024

  11. [20]

    Y., Faria, R., Sutton, B

    Camsari, K. Y., Faria, R., Sutton, B. M. & Datta, S. Stochastic p-bits for invertible logic.Phys. Rev. X 7, 031014 (2017)

    2017

  12. [21]

    Y., Sutton, B

    Camsari, K. Y., Sutton, B. M. & Datta, S. p-bits for probabilistic spin logic.Appl. Phys. Rev.6, 011305 (2019). 22.Kaiser, J. & Datta, S. Probabilistic computing with p-bits.Appl. Phys. Lett.119, 150503 (2021)

    2019

  13. [23]

    J., Beausoleil, R., Lu, W

    Cai, F., Kumar, S., Van Vaerenbergh, T., Sheng, X., Liu, R., Li, C., Liu, Z., Foltin, M., Yu, S., Xia, Q., Yang, J. J., Beausoleil, R., Lu, W. D. & Strachan, J. P. Power-efficient combinatorial optimization using intrinsic noise in memristor hopfield neural networks.Nat. Elect...

    2020

  14. [24]

    Jiang, M., Shan, K., Sheng, X., Graves, C., Strachan, J. P. & Li, C. An efficient synchronous-updating memristor-based ising solver for combinatorial optimization. In2022 International Electron Devices Meeting (IEDM), 22.2.1–22.2.4 (IEEE, 2022)

    2022

  15. [25]

    Jiang, M., Shan, K., He, C. & Li, C. Efficient combinatorial optimization by quantum-inspired parallel annealing in analogue memristor crossbar.Nat. communications14, 5927 (2023). 17/22

    2023

  16. [26]

    & Kim, H

    Kim, K., Youn, S., Park, J. & Kim, H. Ising solver using weight profile of memristor crossbar array for combinatorial optimization. In2024 IEEE International Electron Devices Meeting (IEDM), 1–4 (IEEE, 2024)

    2024

  17. [27]

    One-step combinatorial optimization solver with fully integrated analog memristors and annealing module

    Shan, K., Jiang, M., Du, Z., Xiao, Y., Tong, Y., Li, Z., Yang, S.-H., He, C., Mao, R., Lin, P.et al. One-step combinatorial optimization solver with fully integrated analog memristors and annealing module. In2024 IEEE International Electron Devices Meeting (IEDM), 1–4 (IEEE, 2024)

    2024

  18. [28]

    H., Khanna, A., Ye, H., Niazi, S., Chakraborty, B., Weinstock, E., Babu, N., Mukhopadhyay, S., Datta, S., Camsari, K

    Pantha, T. H., Khanna, A., Ye, H., Niazi, S., Chakraborty, B., Weinstock, E., Babu, N., Mukhopadhyay, S., Datta, S., Camsari, K. & Dutta, S. Towards 3d cmos+x ising machines: Addressing the connectivity problem with back-end-of-line fefets. In2024 IEEE International Electron D...

    2024

  19. [29]

    Kirkpatrick, S., Gelatt, C. D. & Vecchi, M. P. Optimization by simulated annealing.Science220, 671–680 (1983)

    1983

  20. [30]

    G., Querlioz, D.et al.Noise-enhanced synchronization of stochastic magnetic oscillators

    Locatelli, N., Mizrahi, A., Accioly, A., Matsumoto, R., Fukushima, A., Kubota, H., Yuasa, S., Cros, V., Pereira, L. G., Querlioz, D.et al.Noise-enhanced synchronization of stochastic magnetic oscillators. Phys. Rev. Appl.2, 034009 (2014)

    2014

  21. [31]

    Y., Appenzeller, J., Datta, S

    Debashis, P., Faria, R., Camsari, K. Y., Appenzeller, J., Datta, S. & Chen, Z. Experimental demonstration of nanomagnet networks as hardware for ising computing. In2016 IEEE International Electron Devices Meeting (IEDM), 34–3 (IEEE, 2016)

    2016

  22. [32]

    S., Vincent, A

    Vodenicarevic, D., Locatelli, N., Mizrahi, A., Friedman, J. S., Vincent, A. F., Romera, M., Fukushima, A., Yakushiji, K., Kubota, H., Yuasa, S.et al.Low-energy truly random number generation with superparamagnetic tunnel junctions for unconventional computing.Phys. Rev. Appl.8...

    2017

  23. [34]

    & Kos, A

    Rippard, W., Heindl, R., Pufall, M., Russek, S. & Kos, A. Thermal relaxation rates of magnetic nanoparticles in the presence of magnetic fields and spin-transfer effects.Phys. Rev. B84, 064439 (2011)

    2011

  24. [35]

    & Zhang, S

    Li, Z. & Zhang, S. Thermally assisted magnetization reversal in the presence of a spin-transfer torque. Phys. Rev. B69, 134416 (2004)

    2004

  25. [36]

    & Fukami, S

    Hayakawa, K., Kanai, S., Funatsu, T., Igarashi, J., Jinnai, B., Borders, W., Ohno, H. & Fukami, S. Nanosecond random telegraph noise in in-plane magnetic tunnel junctions.Phys. review letters126, 117202 (2021)

    2021

  26. [37]

    & Sun, J

    Safranski, C., Kaiser, J., Trouilloud, P., Hashemi, P., Hu, G. & Sun, J. Z. Demonstration of nanosecond operation in stochastic magnetic tunnel junctions.Nano letters21, 2040–2045 (2021)

    2021

  27. [38]

    Soumah, L., Desplat, L., Phan, N.-T., Valli, A. S. E., Madhavan, A., Disdier, F., Auffret, S., Sousa, R., Ebels, U. & Talatchian, P. Nanosecond stochastic operation in perpendicular superparamagnetic tunnel junctions.arXiv preprint arXiv:2402.03452, Phys. Rev. Applied, press(2024)

    2024 arXiv

  28. [39]

    & Jakob, G

    Schnitzspan, L., Kläui, M. & Jakob, G. Nanosecond true-random-number generation with superparam- agnetic tunnel junctions: Identification of joule heating and spin-transfer-torque effects.Phys. Rev. Appl. 20, 024002 (2023)

    2023

  29. [40]

    D., Adam, G

    Prezioso, M., Merrikh-Bayat, F., Hoskins, B. D., Adam, G. C., Likharev, K. K. & Strukov, D. B. Training and operation of an integrated neuromorphic network based on metal-oxide memristors.Nature521, 61–64 (2015). 18/22

    2015

  30. [41]

    B., Zhang, W., Wu, D., Deiss, S., Raina, P., Qian, H., Gao, B.et al.A compute-in-memory chip based on resistive random-access memory.Nature608, 504–512 (2022)

    Wan, W., Kubendran, R., Schaefer, C., Eryilmaz, S. B., Zhang, W., Wu, D., Deiss, S., Raina, P., Qian, H., Gao, B.et al.A compute-in-memory chip based on resistive random-access memory.Nature608, 504–512 (2022)

    2022

  31. [42]

    & Troyer, M

    Isakov, S., Zintchenko, I., Rønnow, T. & Troyer, M. Optimised simulated annealing for ising spin glasses. Comput. Phys. Commun.192, 265–271 (2015)

    2015

  32. [43]

    & Camsari, K

    Lee, K., Chowdhury, S. & Camsari, K. Y. Noise-augmented chaotic ising machines for combinatorial optimization and sampling.Commun. Phys.8, 35 (2025)

    2025

  33. [44]

    A., Grimaldi, A., Finocchio, G

    Aadit, N. A., Grimaldi, A., Finocchio, G. & Camsari, K. Y. Physics-inspired ising computing with ring oscillator activated p-bits. In2022 IEEE 22nd International Conference on Nanotechnology (NANO), 393–396 (2022)

    2022

  34. [45]

    M.et al.A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference.Nat

    Le Gallo, M., Khaddam-Aljameh, R., Stanisavljevic, M., Vasilopoulos, A., Kersting, B., Dazzi, M., Karunaratne, G., Brändli, M., Singh, A., Mueller, S. M.et al.A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference.Nat. Elec...

    2023

  35. [46]

    Nature620, 768–775 (2023)

    Ambrogio, S., Narayanan, P., Okazaki, A., Fasoli, A., Mackin, C., Hosokawa, K., Nomura, A., Yasuda, T., Chen, A., Friz, A.et al.An analog-ai chip for energy-efficient speech recognition and transcription. Nature620, 768–775 (2023)

    2023

  36. [47]

    J., Lu, W., Chang, M.-F., Ielmini, D., Yang, Y.et al.Hardware implementation of memristor-based artificial neural networks.Nat

    Aguirre, F., Sebastian, A., Le Gallo, M., Song, W., Wang, T., Yang, J. J., Lu, W., Chang, M.-F., Ielmini, D., Yang, Y.et al.Hardware implementation of memristor-based artificial neural networks.Nat. communications15, 1974 (2024)

    2024

  37. [48]

    & Jin, I

    Park, J., Lee, B., Lee, H., Lim, D., Kang, J., Cho, C., Na, M. & Jin, I. Wafer to wafer hybrid bonding for dram applications. In2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), 126–129 (2022)

    2022

  38. [49]

    & Chudzik, M

    Gorchichko, M., Sharma, S., Ng, B., Sherwood, T., Jeon, Y., Mcintyre, D., Li, K., Singh, S., Iler, E., Knapp, D., Prakash, A., Nguen, V., Sreenivasan, R., Krishnan, S. & Chudzik, M. Novel low thermal budget bonding using single wafer thermal processing system, resulting in exc...

    2024

  39. [50]

    A., Adam, G., Prezioso, M., Hoskins, B., Payvand, M., Madhavan, A., Ghofrani, A., Theogarajan, L., Cheng, K.-T

    Chakrabarti, B., Lastras-Montaño, M. A., Adam, G., Prezioso, M., Hoskins, B., Payvand, M., Madhavan, A., Ghofrani, A., Theogarajan, L., Cheng, K.-T. & Strukov, D. B. A multiply-add engine with monolithically integrated 3d memristor crossbar/cmos hybrid circuit.Sci. Reports7, 4...

    2017

  40. [51]

    Commun.14, 7140 (2023)

    Li, Y.et al.Monolithic three-dimensional integration of rram-based hybrid memory architecture for one-shot learning.Nat. Commun.14, 7140 (2023)

    2023

  41. [52]

    M., Wang, X., Moro, F., Nodin, J.-F., Jana, K., Du, S., Upton, L

    Liu, S., Radway, R. M., Wang, X., Moro, F., Nodin, J.-F., Jana, K., Du, S., Upton, L. R., Chen, W.-C., Chen, J.et al.Edge continual training and inference with rram-gain cell memory integrated on si cmos. In2024 IEEE International Electron Devices Meeting (IEDM), 1–4 (IEEE, 2024)

    2024

  42. [53]

    M., Wang, X., Kwon, J., Trippel, C., Levis, P., Mitra, S

    Liu, S., Radway, R. M., Wang, X., Kwon, J., Trippel, C., Levis, P., Mitra, S. & Wong, H.-S. P. Future of memory: Massive, diverse, tightly integrated with compute - from device to software. In2024 IEEE International Electron Devices Meeting (IEDM), 1–4 (IEEE, 2024)

    2024

  43. [54]

    & Payvand, M

    Vianello, E. & Payvand, M. Scaling neuromorphic systems with 3d technologies.Nat. Electron.7, 419–421 (2024). 19/22

    2024

  44. [55]

    Thousands of conductance levels in memristors integrated on cmos.Nature615, 823–829 (2023)

    Rao, M., Tang, H., Wu, J., Song, W., Zhang, M., Yin, W., Zhuo, Y., Kiani, F., Chen, B., Jiang, X.et al. Thousands of conductance levels in memristors integrated on cmos.Nature615, 823–829 (2023)

    2023

  45. [56]

    Park, J., Kumar, A., Zhou, Y., Oh, S., Kim, J.-H., Shi, Y., Jain, S., Hota, G., Qiu, E., Nagle, A. L.et al. Multi-level, forming and filament free, bulk switching trilayer rram for neuromorphic computing at the edge.Nat. Commun.15, 3492 (2024)

    2024

  46. [57]

    electronic materials8, 2200448 (2022)

    Stecconi, T., Guido, R., Berchialla, L., La Porta, A., Weiss, J., Popoff, Y., Halter, M., Sousa, M., Horst, F., Dávila, D.et al.Filamentary taox/hfo2 reram devices for neural networks training with analog in-memory computing.Adv. electronic materials8, 2200448 (2022)

    2022

  47. [58]

    & Grollier, J

    Laydevant, J., Marković, D. & Grollier, J. Training an ising machine with equilibrium propagation.Nat. Commun.15, 3671 (2024)

    2024

  48. [59]

    & Querlioz, D

    Harabi, K.-E., Hirtzlin, T., Turck, C., Vianello, E., Laurent, R., Droulez, J., Bessière, P., Portal, J.-M., Bocquet, M. & Querlioz, D. A memristor-based bayesian machine.Nat. Electron.6, 52–63 (2023)

    2023

  49. [60]

    Commun.15, 741 (2024)

    Jebali, F., Majumdar, A., Turck, C., Harabi, K.-E., Faye, M.-C., Muhr, E., Walder, J.-P., Bilousov, O., Michaud, A., Vianello, E.et al.Powering ai at the edge: A robust, memristor-based binarized neural network with near-memory computing and miniaturized solar cell.Nat. Commun...

    2024

  50. [61]

    Commun.14, 7530 (2023)

    Bonnet, D., Hirtzlin, T., Majumdar, A., Dalgaty, T., Esmanhotto, E., Meli, V., Castellani, N., Martin, S., Nodin, J.-F., Bourgeois, G.et al.Bringing uncertainty quantification to the extreme-edge with memristor-based bayesian neural networks.Nat. Commun.14, 7530 (2023)

    2023

  51. [62]

    & Vianello, E

    Esmanhotto, E., Hirtzlin, T., Bonnet, D., Castellani, N., Portal, J.-M., Querlioz, D. & Vianello, E. Experimental demonstration of multilevel resistive random access memory programming for up to two months stable neural networks inference accuracy.Adv. Intell. Syst.4, 2200145 (2022)

    2022

  52. [63]

    et al.Ferroelectric compute-in-memory annealer for combinatorial optimization problems.Nat

    Yin, X., Qian, Y., Vardar, A., Günther, M., Müller, F., Laleni, N., Zhao, Z., Jiang, Z., Shi, Z., Shi, Y. et al.Ferroelectric compute-in-memory annealer for combinatorial optimization problems.Nat. Commun. 15, 2419 (2024). 20/22 F eature This work Cai et al. (2020)23 Jiang et ...

    2024

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