SparseDPD: A Sparse Neural Network-based Digital Predistortion FPGA Accelerator for RF Power Amplifier Linearization

Chang Gao; Manno Versluis; Yizhuo Wu

arxiv: 2506.16591 · v1 · submitted 2025-06-19 · 💻 cs.AR · eess.SP

SparseDPD: A Sparse Neural Network-based Digital Predistortion FPGA Accelerator for RF Power Amplifier Linearization

Manno Versluis , Yizhuo Wu , Chang Gao This is my paper

Pith reviewed 2026-05-19 08:50 UTC · model grok-4.3

classification 💻 cs.AR eess.SP

keywords digital predistortionFPGA acceleratorneural networkpower amplifiersparse modelunstructured pruningRF linearization

0 comments

The pith

SparseDPD deploys a 74% sparse neural network on FPGA to linearize RF power amplifiers with -59.4 dBc ACPR at 241 mW.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces SparseDPD, an FPGA accelerator for digital predistortion that replaces heavy polynomial models with a pruned neural network. It applies unstructured pruning to a phase-normalized time-delay neural network, cutting the model to 64 parameters at 74% sparsity. The resulting design runs on a Xilinx Zynq-7Z010 at 170 MHz, delivering strong linearization metrics while drawing only 241 mW dynamic power. This shows that sparsity can make neural-network DPD practical for real-time wireless hardware without accuracy loss.

Core claim

By applying unstructured pruning to a phase-normalized time-delay neural network, SparseDPD produces a 74% sparse model with 64 parameters that, when accelerated on a Xilinx Zynq-7Z010 FPGA at 170 MHz, achieves ACPR of -59.4 dBc, EVM of -54.0 dBc, and NMSE of -48.2 dB while consuming 241 mW dynamic power.

What carries the argument

Spatially sparse phase-normalized time-delay neural network (PNTDNN) created by unstructured pruning, which reduces multiply-accumulate operations for FPGA deployment while keeping linearization performance.

If this is right

NN-based DPD becomes feasible on low-cost FPGAs for real-time wireless transmitters.
Dynamic power for predistortion drops to levels suitable for battery or edge devices.
Unstructured pruning offers a general route to shrink other signal-processing neural networks for hardware.
The 64-parameter footprint leaves headroom for additional baseband processing on the same chip.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

The same pruning strategy could be tested on larger FPGAs or ASICs to support wider bandwidth signals.
Public code release makes it straightforward to adapt the accelerator to different PA models or frequency bands.
Further sparsity levels or mixed-precision arithmetic might push power below 200 mW while retaining performance.

Load-bearing premise

Unstructured pruning keeps the neural network's linearization accuracy intact once the sparse model is placed on the target FPGA hardware.

What would settle it

Measure ACPR, EVM, and NMSE on the actual Xilinx Zynq-7Z010 FPGA running the SparseDPD bitstream and check whether the values reach or exceed the reported -59.4 dBc, -54.0 dBc, and -48.2 dB.

Figures

Figures reproduced from arXiv: 2506.16591 by Chang Gao, Manno Versluis, Yizhuo Wu.

**Figure 2.** Figure 2: The FEx layer implementation, where m is the window size of the [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗

**Figure 3.** Figure 3: The inverse square root implementation. E. Phase Denormalization The final stage restores the original phase to the FC layer outputs: Iy,t + jQy,t = (IOUT,y,t + jQOUT,y,t)P ∗ (13) where P ∗ is the complex conjugate of P from (7), ensuring the predistorted signal aligns with the input’s phase properties. III. ACCELERATOR DESIGN The SparseDPD accelerator is engineered for efficiency on the FPGA, optimizing e… view at source ↗

**Figure 4.** Figure 4: DPD model accuracy while pruning for various amounts of bits, with 12 bias parameters and a hidden size of 12, one seed only. Trained for 400 [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗

**Figure 5.** Figure 5: Experimental setup for dataset acquisition and DPD performance [PITH_FULL_IMAGE:figures/full_fig_p003_5.png] view at source ↗

read the original abstract

Digital predistortion (DPD) is crucial for linearizing radio frequency (RF) power amplifiers (PAs), improving signal integrity and efficiency in wireless systems. Neural network (NN)-based DPD methods surpass traditional polynomial models but face computational challenges limiting their practical deployment. This paper introduces SparseDPD, an FPGA accelerator employing a spatially sparse phase-normalized time-delay neural network (PNTDNN), optimized through unstructured pruning to reduce computational load without accuracy loss. Implemented on a Xilinx Zynq-7Z010 FPGA, SparseDPD operates at 170 MHz, achieving exceptional linearization performance (ACPR: -59.4 dBc, EVM: -54.0 dBc, NMSE: -48.2 dB) with only 241 mW dynamic power, using 64 parameters with 74% sparsity. This work demonstrates FPGA-based acceleration, making NN-based DPD practical and efficient for real-time wireless communication applications. Code is publicly available at https://github.com/MannoVersluis/SparseDPD.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

SparseDPD shows a practical sparse NN DPD on cheap FPGA with open code and solid metrics, though the no-accuracy-loss pruning claim lacks a hardware dense comparison.

read the letter

The paper gives a working FPGA implementation of a sparse neural network for digital predistortion. It runs a 74% sparse PNTDNN with 64 parameters on a Xilinx Zynq-7Z010 at 170 MHz, reports ACPR of -59.4 dBc along with good EVM and NMSE, and uses only 241 mW dynamic power. What stands out is the practical mapping. They apply unstructured pruning to reduce the network size without claiming any accuracy drop, synthesize it for the FPGA, and release the code. This shows a path to make NN-based DPD feasible on inexpensive hardware for wireless applications. The results are concrete and the power figure is attractive for real deployments. The open source aspect adds value for reproduction. The soft spot is the pruning claim. The headline metrics come only from the sparse model. There is no reported comparison of the dense network running on the same FPGA setup, including quantization and routing effects. Without that, it is difficult to confirm that pruning truly caused no loss under hardware constraints. The stress-test concern about this is fair given the abstract. Experimental details are also sparse. The abstract does not spell out the measurement setup, the specific PA, or the test signals used. This leaves the central performance claim less anchored than it could be. This work is for engineers and researchers focused on FPGA accelerators for RF systems. Someone building or evaluating DPD solutions for cost-sensitive wireless devices would find the implementation details and code useful. I recommend sending it to peer review. The implementation is real and the code is public, so referees can request the dense baseline and more setup information. It is worth the effort rather than rejecting outright.

Referee Report

1 major / 2 minor

Summary. The paper introduces SparseDPD, an FPGA accelerator for RF power amplifier linearization that employs unstructured pruning on a phase-normalized time-delay neural network (PNTDNN) to achieve 74% sparsity with 64 parameters. Implemented on a Xilinx Zynq-7Z010 at 170 MHz, it reports ACPR of -59.4 dBc, EVM of -54.0 dBc, NMSE of -48.2 dB, and 241 mW dynamic power, claiming no accuracy loss relative to the dense model while making the code publicly available.

Significance. If the no-accuracy-loss claim is substantiated, the work would demonstrate a practical route to deploying NN-based DPD on low-cost FPGAs, improving efficiency for real-time wireless applications. The public code release and measured hardware results (rather than purely simulated) strengthen the contribution to the field of hardware-accelerated signal processing.

major comments (1)

[Results] Results section (performance metrics paragraph): The headline figures (ACPR -59.4 dBc, EVM -54.0 dBc, NMSE -48.2 dB) are reported exclusively for the 74%-sparse PNTDNN. No table or figure directly compares these metrics for the dense versus pruned model after FPGA synthesis, quantization, and routing under identical test waveforms and PA conditions; this comparison is required to substantiate the central claim that unstructured pruning incurs no accuracy loss on the target hardware.

minor comments (2)

[Abstract] Abstract and §3: The measurement setup (test waveform, PA model, training dataset size, and verification procedure for the no-accuracy-loss claim) is not summarized; adding a concise description would improve reproducibility.
[Method] Implementation details: Clarify how the 64-parameter count and 74% sparsity are obtained after pruning (e.g., exact pruning criterion and retraining protocol) to allow readers to assess the method's generality.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for their constructive feedback on our manuscript. We appreciate the emphasis on substantiating the no-accuracy-loss claim with hardware-level comparisons and will revise the paper to address this.

read point-by-point responses

Referee: The headline figures (ACPR -59.4 dBc, EVM -54.0 dBc, NMSE -48.2 dB) are reported exclusively for the 74%-sparse PNTDNN. No table or figure directly compares these metrics for the dense versus pruned model after FPGA synthesis, quantization, and routing under identical test waveforms and PA conditions; this comparison is required to substantiate the central claim that unstructured pruning incurs no accuracy loss on the target hardware.

Authors: We concur that a side-by-side comparison of the metrics for the dense and pruned models post-FPGA synthesis, quantization, and routing is essential to robustly support our claim. The manuscript includes software-based evaluations (in the performance evaluation subsection) demonstrating that the 74% sparse PNTDNN achieves nearly identical ACPR, EVM, and NMSE to the dense model under the same test waveforms and PA conditions. Due to the dense model's significantly higher computational complexity, it could not be synthesized and routed on the resource-constrained Xilinx Zynq-7Z010 without exceeding available hardware resources. The sparse implementation is specifically designed to enable deployment on such low-cost FPGAs. In the revised version, we will include an additional table in the Results section that tabulates the software metrics for both models and explicitly discusses the hardware implementation feasibility, thereby clarifying the context of our no-accuracy-loss statement. revision: yes

Circularity Check

0 steps flagged

No circularity: performance claims rest on hardware measurements, not on equations or fits that reduce to inputs by construction

full rationale

The paper presents an FPGA implementation of a pruned PNTDNN for DPD, with reported metrics (ACPR, EVM, NMSE, power) obtained from physical synthesis and benchmarking on the Zynq-7Z010 at 170 MHz. No derivation chain, first-principles prediction, or fitted parameter is invoked whose output is mathematically forced to equal the input data or a prior self-citation. The central results are empirical measurements under stated test conditions rather than algebraic identities or renamed fits. Minor self-citations to prior NN-DPD work exist but are not load-bearing for the hardware claims, which remain independently verifiable via the public code and FPGA platform.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 0 invented entities

The work rests on the domain assumption that a phase-normalized time-delay neural network is an appropriate base model for DPD and that unstructured pruning can be applied without accuracy loss on the target hardware.

free parameters (1)

sparsity level
74% sparsity is selected via pruning to reduce computation while claiming no accuracy loss; this value is central to the reported efficiency.

axioms (1)

domain assumption PNTDNN is a suitable neural architecture for RF power amplifier linearization
The design begins from this model before applying sparsity.

pith-pipeline@v0.9.0 · 5725 in / 1340 out tokens · 38307 ms · 2026-05-19T08:50:51.217101+00:00 · methodology

discussion (0)

Lean theorems connected to this paper

Citations machine-checked in the Pith Canon. Every link opens the source theorem in the public Lean library.

IndisputableMonolith/Cost/FunctionalEquation.lean washburn_uniqueness_aczel unclear

?

unclear
Relation between the paper passage and the cited Recognition theorem.

SparseDPD accelerator employing a spatially sparse phase-normalized time-delay neural network (PNTDNN), optimized through unstructured pruning... 64 parameters with 74% sparsity... 170 MHz... ACPR -59.4 dBc
IndisputableMonolith/Foundation/RealityFromDistinction.lean reality_from_one_distinction unclear

?

unclear
Relation between the paper passage and the cited Recognition theorem.

feature extraction... phase normalization... fully connected layers... phase denormalization

What do these tags mean?

matches: The paper's claim is directly supported by a theorem in the formal canon.
supports: The theorem supports part of the paper's argument, but the paper may add assumptions or extra steps.
extends: The paper goes beyond the formal theorem; the theorem is a base layer rather than the whole result.
uses: The paper appears to rely on the theorem as machinery.
contradicts: The paper's claim conflicts with a theorem or certificate in the canon.
unclear: Pith found a possible connection, but the passage is too broad, indirect, or ambiguous to say the theorem truly supports the claim.

Reference graph

Works this paper leans on

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S. Wesemann, J. Du, and H. Viswanathan, “Energy efficient extreme mimo: Design goals and directions,” IEEE Communications Magazine , vol. 61, no. 10, pp. 132–138, 2023

work page 2023

[2] [2]

A generalized memory polynomial model for digital predistortion of rf power ampli- fiers,

D. Morgan, Z. Ma, J. Kim, M. Zierdt, and J. Pastalan, “A generalized memory polynomial model for digital predistortion of rf power ampli- fiers,” IEEE Transactions on Signal Processing , vol. 54, no. 10, pp. 3852–3860, 2006

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D. Wang, M. Aziz, M. Helaoui, and F. M. Ghannouchi, “Augmented real-valued time-delay neural network for compensation of distortions and impairments in wireless transmitters,” IEEE Transactions on Neural Networks and Learning Systems , vol. 30, no. 1, pp. 242–254, Jun 2019

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An inter-modulation oriented learning based digital pre-distortion technique via joint interme- diate and radio frequency optimization,

X. Chen, Z. Lu, S. Zhang, S. Xu, and Y . Wang, “An inter-modulation oriented learning based digital pre-distortion technique via joint interme- diate and radio frequency optimization,” IEEE Transactions on Wireless Communications, vol. 22, no. 6, pp. 3777–3789, 2023

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A. Fischer-B ¨uhner, L. Anttila, M. D. Gomony, and M. Valkama, “Phase- normalized neural network for linearization of rf power amplifiers,” IEEE Microwave and Wireless Technology Letters , vol. 33, no. 9, pp. 1357–1360, 2023

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S. Han, J. Pool, J. Tran, and W. J. Dally, “Learning both weights and connections for efficient neural networks,” in Proceedings of the 29th International Conference on Neural Information Processing Systems - V olume 1, ser. NIPS’15. Cambridge, MA, USA: MIT Press, 2015, p. 1135–1143

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Parhami, Computer arithmetic: Algorithms and hardware designs

B. Parhami, Computer arithmetic: Algorithms and hardware designs . Oxford University Press, 2000

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MP-DPD: Low-complexity mixed-precision neural networks for energy-efficient digital predistortion of wideband power amplifiers,

Y . Wu, A. Li, M. Beikmirza, G. D. Singh, Q. Chen, L. C. N. de Vreede, M. Alavi, and C. Gao, “MP-DPD: Low-complexity mixed-precision neural networks for energy-efficient digital predistortion of wideband power amplifiers,” IEEE Microwave and Wireless Technology Letters , vol. 34, no. 6, pp. 817–820, 2024

work page 2024

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A sparse neural network-based power adaptive dpd design and its hardware implementation,

M. Tanio, N. Ishii, and N. Kamiya, “A sparse neural network-based power adaptive dpd design and its hardware implementation,” IEEE Access, vol. 10, pp. 114 673–114 682, 2022

work page 2022

[10] [10]

Power con- sumption and linearization performance of a bit- and frequency-scalable am/am am/pm pre-distortion on fpga,

T. Cappello, G. Jindal, J. Nunez-Yanez, and K. Morris, “Power con- sumption and linearization performance of a bit- and frequency-scalable am/am am/pm pre-distortion on fpga,” in 2022 International Workshop on Integrated Nonlinear Microwave and Millimetre-Wave Circuits (IN- MMiC), 2022, pp. 1–3

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Reducing power consumption of digital predistortion for rf power amplifiers using real-time model switching,

Y . Li, X. Wang, and A. Zhu, “Reducing power consumption of digital predistortion for rf power amplifiers using real-time model switching,” IEEE Transactions on Microwave Theory and Techniques , vol. 70, no. 3, pp. 1500–1508, 2022

work page 2022

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Novel parallel-processing-based hardware implementation of baseband digital predistorters for linearizing wideband 5g transmitters,

H. Huang, J. Xia, and S. Boumaiza, “Novel parallel-processing-based hardware implementation of baseband digital predistorters for linearizing wideband 5g transmitters,”IEEE Transactions on Microwave Theory and Techniques, vol. 68, no. 9, pp. 4066–4076, 2020

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[13] [13]

Gpu-based implementation of pruned artificial neural networks for dig- ital predistortion linearization of wideband power amplfiers,

W. Li, R. Criado, W. Thompson, C. G. K. Montoro, and P. L. Gilabert, “Gpu-based implementation of pruned artificial neural networks for dig- ital predistortion linearization of wideband power amplfiers,” TechRxiv, 2024

work page 2024

[14] [14]

DPD- NeuralEngine: A 22-nm 6.6-tops/w/mm 2 recurrent neural network accelerator for wideband power amplifier digital pre-distortion,

A. Li, H. Wu, Y . Wu, Q. Chen, L. C. N. de Vreede, and C. Gao, “DPD- NeuralEngine: A 22-nm 6.6-tops/w/mm 2 recurrent neural network accelerator for wideband power amplifier digital pre-distortion,” 2025. [Online]. Available: https://arxiv.org/abs/2410.11766

work page arXiv 2025

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May 2024

Y . Wu, G. D. Singh, M. Beikmirza, L. C. N. de Vreede, M. Alavi, and C. Gao, “OpenDPD: An open-source end-to-end learning & benchmarking framework for wideband power amplifier modeling and digital pre-distortion,” in 2024 IEEE International Symposium on Circuits and Systems (ISCAS) . IEEE, May 2024, p. 1–5. [Online]. Available: http://dx.doi.org/10.1109/I...

work page doi:10.1109/iscas58744.2024.10558162 2024

[16] [16]

Energy-efficient activity- driven computing architectures for edge intelligence,

S.-C. Liu, C. Gao, K. Kim, and T. Delbruck, “Energy-efficient activity- driven computing architectures for edge intelligence,” in 2022 Interna- tional Electron Devices Meeting (IEDM) , 2022, pp. 21.2.1–21.2.4

work page 2022

[17] [17]

Deltadpd: Exploiting dynamic temporal sparsity in recurrent neural networks for energy-efficient wideband digital pre- distortion,

Y . Wu, Y . Zhu, K. Qian, Q. Chen, A. Zhu, J. Gajadharsing, L. C. N. de Vreede, and C. Gao, “Deltadpd: Exploiting dynamic temporal sparsity in recurrent neural networks for energy-efficient wideband digital pre- distortion,” IEEE Microwave and Wireless Technology Letters , vol. 35, no. 6, pp. 772–775, 2025. 5

work page 2025