Pith. sign in

REVIEW 4 major objections 5 minor 25 references

A TRNG Implemented using a Soft-Data Based Sponge Function within a Unified Strong PUF Architecture

T0 review · 4 major / 5 minor · reviewed 2026-08-06 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read This paper shows that a single FPGA design can act as both a strong PUF and a TRNG: soft delay values run through a sponge function, and the output passes four randomness test suites.

desk verdict A plausible, well-tested unified PUF-TRNG whose load-bearing entropy-source claim is never directly measured; needs revision before it can be trusted as a TRNG. read the letter →

arxiv 2506.17795 v1 pith:Q2MFIW77 submitted 2025-06-21 cs.CR

Rachel Cazzola , Cyrus Minwalla , Calvin Chan , Jim Plusquellic This is my paper · ORCID
classification cs.CR
keywords truerandomnumbergeneratorphysicalunclonablefunctionSiRFPUFsoft-dataspongetime-to-digitalconverterFPGAmin-entropystatisticaltesting
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper proposes a single FPGA circuit that acts as both a strong physical unclonable function (PUF) and a true random number generator (TRNG). It claims that by reusing the SiRF PUF's path-delay measurement hardware and adding a soft-data sponge post-processing step, the circuit produces random bit streams that pass NIST SP 800-22, NIST SP 800-90B, AIS-31, and DieHarder tests. The reported worst-case min-entropy across five boards is between 0.941 and 0.999, with a bit rate of about 2.67 Mbps and only about 5% area overhead over the standalone PUF. This matters because a compact unified hardware security primitive could supply both key generation and random-number generation for resource-constrained systems.

What carries the argument

The load-bearing object is the soft-data sponge: a modified duplex sponge construction that permutes fixed-point values in a range around ±64 through chaining, rather than operating on bitstrings like SHA-3. Its absorption phase uses two 11-bit LFSRs to pseudo-randomly pair stored delay values (DVDiff), followed by GPEV linear transforms that standardize the difference distribution against temperature and voltage; its permutation phase is the Spread-Factor module, which offsets each compensated difference by a running factor and folds outliers back into a bounded band, creating a triangular SF distribution and destroying correlations introduced by reusing the same delay values across iterations. BitGen then squeezes one bit per value by its sign. The randomized Range Constant and Trim Code Constant inject nonce-derived unpredictability into the transforms.

What would settle it

Run NIST SP 800-90B's entropy-source tests on the raw TDC low-order-bit stream before the 12-bit XOR and sponge processing; if the estimated min-entropy per bit is substantially below 1, or adjacent bits are autocorrelated, the claimed one full bit of dynamic entropy per 12 measurements fails and the TRNG's entropy budget collapses.

Watch

Extended reading notes

Core claim

The paper's central claim is that static manufacturing-variation entropy from the SiRF PUF can be combined with dynamic measurement noise from a time-to-digital converter (TDC) to yield a TRNG without building a separate entropy circuit. The key move is a new post-processing chain modeled on a duplex sponge that runs on soft fixed-point delay values rather than bits. Each iteration of the sponge loop recombines stored delay values, compensates for temperature and voltage with the GPEV linear transforms, permutes values through spread-factor chaining, and squeezes one bit per processed value based on sign. The authors report that SF chaining is necessary: without it, correlated copies of difference sequences produce 100% Pearson correlations and the bitstreams fail the statistical suites; with it, correlations stay below ±10% and the bitstreams pass. They also report that XORing the low-order bits of 12 consecutive TDC measurements yields one full bit of dynamic entropy, providing 341 nonce bits per 4,096 path measurements to randomize the sponge parameters. The NIST SP 800-22 suite passed except for a single non-overlapping template subtest on one board, where 36 of 40 strings passed rather than the required 37.

Load-bearing premise

The design's randomness rests on the claim that XORing the low-order bits of 12 consecutive TDC path-delay measurements produces one full bit of independent physical noise, an assertion the paper bases on FPGA experiments but does not check with a source-level entropy test.

Editorial extensions

If this is right

  • A single compact module can serve both PUF-based key generation and TRNG duty in a hardware security module, since the TRNG reuses more than 95% of the standalone SiRF PUF's logic and adds only about 5% area.
  • The reported pass rates across four statistical suites, including long-run DieHarder data, suggest the output meets common acceptance criteria for cryptographic random bit sequences.
  • Because the GPEV compensation is built into the sponge chain, the design carries a built-in defense against temperature and supply-voltage shifts that often destabilize PUF-based entropy.
  • Bit generation scales with clock frequency, so the 2.67 Mbps rate is not a hard ceiling; raising the FPGA clock would roughly double throughput.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The entropy-generating step that most deserves independent scrutiny is the 12-bit XOR distillation; the paper validates it only with post-processed bitstream tests, so a natural extension is to run NIST SP 800-90B directly on the raw XORed noise stream before the sponge.
  • If the raw noise assumption holds, the same soft-data sponge recipe could plausibly be ported to other delay-based PUFs, such as arbiter or ring-oscillator designs, turning any of them into a unified PUF-TRNG without a separate oscillator-based entropy core; the paper does not test this portability.
  • The reported DieHarder run lasted over 20 days, but the paper does not address aging or radiation-induced drift in TDC noise, so a longer-term reliability study would test whether the entropy source degrades over device lifetime.
  • A single marginal failure in one non-overlapping template subtest on one board is not discussed beyond being reported; a stricter multi-board replication with more than 40 sequences per board would show whether that shortfall is a statistical fluke or a systematic weakness.
Share X Bluesky LinkedIn Reddit HN

Signed reviews

No signed human review yet.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The manuscript proposes a unified PUF-TRNG architecture built on the SiRF strong PUF, combining static path-delay differences with dynamic noise captured in the low-order bits of time-to-digital-converter (TDC) measurements. A novel soft-data sponge construction (DVDiff, GPEV, SF chaining, BitGen) post-processes digitized delay values over 2,048 iterations to generate random bit sequences. The authors report that 40 Mbit sequences per board pass NIST SP 800-22, 10 MByte sequences pass NIST SP 800-90B with worst-case min-entropy between 0.941 and 0.946, all AIS-31 tests pass, and all DieHarder tests pass on five Zynq ZYBO boards; they also report a 2.67 Mbps bit rate and about 5% resource overhead over the stand-alone SiRF PUF.

Significance. If the raw dynamic entropy source were properly validated, this would be a valuable compact unified PUF-TRNG with unusually comprehensive statistical testing, and the reuse of the PUF infrastructure is practically attractive. The paper deserves credit for running four statistical test suites, for comparing against OpenSSL, and for reporting resource utilization and throughput. However, the central contribution is currently conditional on an unverified entropy-source claim: the statistical evidence as presented does not establish that the output is truly random, because the entropy source itself is never assessed and the post-processed stream is used for validation.

major comments (4)
  1. [Section III.A and Section IV.E] The claim that XORing the low-order bits of 12 consecutive path-delay measurements yields one full bit of dynamic entropy is never supported by a direct measurement of the raw source. The paper says this was determined from FPGA experiments but provides no raw-source min-entropy estimate, autocorrelation analysis, or noise characterization. Section IV.E applies NIST SP 800-22 to 100,000-bit nonce sequences, but a statistical pass of a distilled sequence does not quantify the entropy rate or independence of the underlying source. Because the TRNG's true-randomness claim rests entirely on this dynamic entropy, the paper must provide an entropy-source-level evaluation, e.g., NIST SP 800-90B on the raw nonce bits, and ideally show that the min-entropy per raw bit is at least 1/12.
  2. [Section IV.B and Table II] The NIST SP 800-90B min-entropy estimates are computed on the final output after 2,048 iterations of deterministic post-processing. As the authors themselves note, the sponge is a pseudo-random permutation; a deterministic bijection fed with constant or very low-entropy input can produce output that passes IID tests and yields high min-entropy estimates (cf. any PRNG). Therefore the values in Table II cannot validate the entropy source. NIST SP 800-90B is explicitly intended for entropy-source evaluation, and applying it only to the post-processed stream is not a substitute.
  3. [Abstract and Section III.E] The manuscript repeatedly states that the soft-data sponge 'adds entropy' to the random bit sequences and 'completely exhausts the underlying entropy.' A deterministic permutation over a finite state space cannot add Shannon or min-entropy; it can only mix and decorrelate. This is not merely a phrasing issue: it obscures the fact that all entropy must originate from the raw path-delay noise and the nonce bits. If the raw source has insufficient entropy, the sponge cannot make the output truly random. The paper should either correct this claim or provide a rigorous argument for how the construction increases entropy.
  4. [Section III (parameter selection)] Several key parameters (XOR count of 12, RC and TCC ranges, SF bound, number of sponge iterations, TDC resolution) are described as having been chosen on the basis of FPGA experiments, and the reported configuration was tuned until the statistical suites passed. Because the same families of boards are used both for parameter selection and for final evaluation, the reported pass rates constitute an in-sample assessment. The paper should provide a clear separation between a design/tuning phase and a validation phase (e.g., a hold-out set of boards or a pre-specified parameter-selection rule) to rule out overfitting as the cause of the statistical quality.
minor comments (5)
  1. [Fig. 6 caption and Section III.C] The caption and text refer to '222 DV Dcs' and '22 DV Dcs'; these appear to be formatting losses for 2 to the power 22 (4,194,304). Please use proper superscript notation consistently.
  2. [Section III.A] 341 nonce bits is 42.625 bytes, so describing them as 'approximately 42 bytes' is imprecise; 'about 43 bytes' would be more accurate.
  3. [Section IV.D] The DieHarder section says 'the amount of data is unknown but in the range of 250 GigaBytes.' This is vague; please report the exact number of bits or bytes used for each board.
  4. [Section III.C.1] The description of the two 11-bit LFSRs does not explain how the per-sample pseudo-random selection works within a single iteration, given that the seeds are merely incremented and decremented at the start of each iteration. Please clarify.
  5. [Equations (2)-(4)] The notation in Eqs. (2)-(4) is confusing: using max(DVD) after defining DVD as a set, and then writing max over all j in |DVD| of DVD_j, mixes set-level and element-level operations. Please rewrite with explicit indexing.

Circularity Check

1 steps flagged · score 3.0 of 10

The dynamic-entropy claim rests on an empirically fitted XOR width (12) that is then validated by the same statistical-test behavior used to select it; the rest of the evaluation is external and non-circular.

  1. fitted input called prediction [Section III.A (Source of Static and Dynamic Entropy), with confirmation in Section IV.E]
    "A full bit of dynamic entropy is obtained by XOR'ing the low-order bits of 12 consecutive path delay measurements. The need for 12 consecutive measurements was obtained from experiments carried out on FPGAs. We show in the Experimental Results section that this type of distillation process produces bitstrings that pass all statistical tests."

    The number 12 is not derived from a noise model or from a raw-source entropy measurement; it is a parameter chosen from FPGA experiments. The paper's support for the 'full bit of dynamic entropy' claim is that the resulting bitstrings pass statistical tests. But because the parameter was selected using those experiments and the paper states that the chosen distillation passes the tests, the later 'pass' result is a restatement of the selection criterion rather than an independent confirmation.

full rationale

The overall validation is substantially external: the paper reports passes against NIST SP 800-22, NIST SP 800-90B, AIS-31, and DieHarder on multiple FPGA boards, with data volumes up to 250 GB, and compares favorably with OpenSSL in DieHarder. Those pass/fail outcomes are not circular because they are generated by independent test suites. The main circularity is confined to the dynamic-entropy claim: the XOR width of 12 consecutive low-order path-delay bits is said to have been obtained from FPGA experiments, and the same kind of statistical-test behavior is then cited in Section IV.E as evidence that the distillation produces high-quality bits. This makes the 'full bit of dynamic entropy' assertion partly a retrospective fit. The self-citation to the SiRF PUF [6] provides the netlist and PUF details, but it is not load-bearing for the TRNG randomness claim, so it does not raise the score further. No other derivation in the paper reduces to its own inputs by construction.

Assumptions & free parameters 7 free parameters · 5 assumptions · 0 invented entities

The TRNG's security rests on physical noise assumptions and an unproven permutation property of the soft-data sponge, plus several hand-tuned parameters (XOR count, outlier trim, RC/TCC ranges).

free parameters (7)
  • Dynamic entropy XOR count = 12
    Number of consecutive low-order delay bits XORed to produce one nonce bit; chosen from FPGA experiments (Section III.A).
  • GPEV outlier trim = 5%
    Range measurement uses max/min offset by 5% to avoid outliers (Eqs. 2-3); hand-chosen, affects standardization.
  • Range Constant (RC) range = 128 to 191
    Randomized range expansion in GPEV, selected by 6-bit nonce; range bounds are design choices (Section III.C.2).
  • Trim Code Constant (TCC) range = 8 to 22 even
    SF module step size selected by 3-bit nonce; bounds chosen to keep SF bounded (Section III.C.3).
  • SF bound = +/-64
    Spread-Factor values are bounded to +/-64 (Eq. 7); design choice affecting mixing.
  • Sponge iterations = 2048
    Number of sponge loop iterations per Phase 1 refresh; affects throughput and mixing.
  • TDC resolution = ~18 ps
    Hardware resolution of the time-to-digital converter; not fitted but affects noise capture.
assumptions (5)
  • domain assumption SiRF PUF path delays are stable and unique across devices.
    Static entropy source; based on prior SiRF PUF work [6].
  • domain assumption TDC measurement noise is random and independent across measurements.
    Dynamic entropy source; not directly validated with entropy estimation.
  • domain assumption XOR of 12 low-order bits of consecutive delay measurements yields an unbiased bit.
    Empirical tuning from experiments; statistical tests on nonce bits only with NIST 800-22.
  • ad hoc to paper SF chaining behaves as a pseudo-random permutation over the DV Dc state space.
    Claimed in Section III.E without proof; central to decorrelation.
  • standard math Statistical test suites passing implies cryptographic randomness.
    Standard practice for TRNG evaluation, though not a guarantee.

how reviews work

0 comments
Cite this review

Pith. "Pith review of A TRNG Implemented using a Soft-Data Based Sponge Function within a Unified Strong PUF Architecture." pith.science (2026). https://pith.science/paper/Q2MFIW77

@misc{pith2026250617795,
  author       = {Pith},
  title        = {Pith review of: A TRNG Implemented using a Soft-Data Based Sponge Function within a Unified Strong PUF Architecture},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/Q2MFIW77}},
  note         = {Machine review of arXiv:2506.17795}
}
read the original abstract

Hardware security primitives including True Random Number Generators (TRNG) and Physical Unclonable Functions (PUFs) are central components to establishing a root of trust in microelectronic systems. In this paper, we propose a unified PUF-TRNG architecture that leverages a combination of the static entropy available in a strong PUF called the shift-register, reconvergent-fanout (SiRF) PUF, and the dynamic entropy associated with random noise present in path delay measurements. The SiRF PUF uses an engineered netlist containing a large number of paths as the source of static entropy, and a time-to-digital-converter (TDC) as a high-resolution, embedded instrument for measuring path delays, where measurement noise serves as the source of dynamic entropy. A novel data postprocessing algorithm is proposed based on a modified duplex sponge construction. The sponge function operates on soft data, i.e., fixed point data values, to add entropy to the ensuing random bit sequences and to increase the bit generation rate. A postprocessing algorithm for reproducing PUF-generated encryption keys is also used in the TRNG to protect against temperature voltage attacks designed to subvert the random characteristics in the bit sequences. The unified PUF-TRNG architecture is implemented across multiple instances of a ZYBO Z7-10 FPGA board and extensively tested with NIST SP 800-22, NIST SP 800-90B, AIS-31, and DieHarder test suites. Results indicate a stable and robust TRNG design with excellent min-entropy and a moderate data rate.

Figures

Figures reproduced from arXiv: 2506.17795 by the authors.

Figure 1
Figure 1. SiRF TRNG algorithm. PUF using magnetic RAM (MRAM) based on spin-transfer torque variations, which theoretically achieved zero-bit error rates. The PUF, however, was not physically realized, and its error rate remains untested in practice. Following this, Khan et al. [13] proposed a similar MRAM-based PUF and successfully fabricated and tested their model. Zalivako et al. [14] explored the use of a ring oscillator P… view at source ↗
Figure 2
Figure 2. Basic building block of the SiRF PUF-TRNG architecture. [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Example DVA, DVB and DV D path delay distributions. The DV D are computed by creating differences using all combinations of elements in the DVA and DVB groups. modules are described in the following with illustrations to show the effect that they have on the DV. Each data post￾processing module is executed 2,048 times, with each iteration producing 2,048 random bits. In tandem, these steps capture the necessary prop… view at source ↗
Figures from the paper (5 more)
Figure 4
Figure 4. Figure 4: The randomized Trim Code Constant (TCC) parameter [PITH_FULL_IMAGE:figures/full_fig_p006_4.png]
Figure 5
Figure 5. Figure 5: is created by starting with iteration 19 of the Sponge Function loop. However, the other 19 distributions that can be created in this fashion are very similar [PITH_FULL_IMAGE:figures/full_fig_p006_5.png]
Figure 6
Figure 6. Figure 6: Distribution of the 2 22 normalized DV Dcs generated over all 2,048 iterations of the Sponge Function loop. 4) Bit Generation: Until now, the DVDiff, GPEV, and SF modules absorbed and transformed fixed point values. The final step of our Sponge Function loop, BitGen, s…
Figure 7
Figure 7. Figure 7: Pearson’s correlation coefficients computed using all [PITH_FULL_IMAGE:figures/full_fig_p007_7.png]
Figure 8
Figure 8. Figure 8: Box plots showing the NIST SP 800-90B Non-IID min [PITH_FULL_IMAGE:figures/full_fig_p010_8.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

25 extracted references · 23 canonical work pages

  1. [1]

    Physical unclonable function and true random number generator: A compact and scalable implementation,

    A. Maiti, R. Nagesh, A. Reddy, and P. Schaumont, “Physical unclonable function and true random number generator: A compact and scalable implementation,” in GLSVLSI, 2009, p. 425–428

    work page 2009

  2. [2]

    Calibration of ring oscillator PUF and TRNG,

    C. Mart ´ınez-G´omez and I. Baturone, “Calibration of ring oscillator PUF and TRNG,” in ECCTD, 2020, pp. 1 – 4

    work page 2020

  3. [3]

    Lightweight inte- grated design of puf and trng security primitives based on eflash memory in 55-nm cmos,

    S. Larimian, M. R. Mahmoodi, and D. B. Strukov, “Lightweight inte- grated design of puf and trng security primitives based on eflash memory in 55-nm cmos,” Trans. on Electron Devices , vol. 67, no. 4, pp. 1586– 1592, 2020

    work page 2020

  4. [4]

    36.1 unified in-memory dynamic trng and multi-bit static puf entropy generation for ubiquitous hardware security,

    S. Taneja, V . K. Rajanna, and M. Alioto, “36.1 unified in-memory dynamic trng and multi-bit static puf entropy generation for ubiquitous hardware security,” in ISSCC, vol. 64, 2021, pp. 498–500

    work page 2021

  5. [5]

    Puf-based random number generation,

    G. E. S. Charles W. O’Donnell and S. Devadas, “Puf-based random number generation,” in MIT CSAIL CSG TM 481 , 2004, pp. 1 – 4

    work page 2004

  6. [6]

    Shift Register, Reconvergent-Fanout (SiRF) PUF Implementation on an FPGA,

    J. Plusquellic, “Shift Register, Reconvergent-Fanout (SiRF) PUF Implementation on an FPGA,” Cryptography, vol. 6, no. 4, 2022. [Online]. Available: https://www.mdpi.com/2410-387X/6/4/59

    work page 2022

  7. [7]

    A new reconfigurable true random number generator and physical unclonable function unified chip with on-chip auto-calibration

    Y . Cao, W. Liu, Y . Zheng, S. Chen, J. Ye, L. Qian, and C.-H. Chang, “A new reconfigurable true random number generator and physical unclonable function unified chip with on-chip auto-calibration.” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS , 2023

    work page 2023

  8. [8]

    Memristive true random number generator with intrinsic two-dimensional physical unclonable function

    B. Liu, J. Ma, H. H. Tai, D. Verma, M. Sahoo, Y .-F. Chang, H. Liang, S. Feng, L.-J. Li, T.-H. Hou, and C.-S. Lai, “Memristive true random number generator with intrinsic two-dimensional physical unclonable function.” ACS APPLIED ELECTRONIC MATERIALS , 2023

    work page 2023

Show all 25 references
  1. [9]

    A tale of twin primitives: Single-chip solution for PUFs and TRNGs,

    K. Pratihar, U. Chatterjee, M. Alam, D. Mukhopadhyay, and R. S. Chakraborty, “A tale of twin primitives: Single-chip solution for PUFs and TRNGs,” Cryptology ePrint Archive, Paper 2021/1067, 2021

    2021

  2. [10]

    Hardware-Efficient Configurable Ring-Oscillator-Based Physical Unclonable Function/True Random Number Generator Module for Secure Key Management

    S. S ´anchez-Solano, L. F. Rojas-Mu ˜noz, M. C. Mart ´ınez-Rodr´ıguez, and P. Brox, “Hardware-Efficient Configurable Ring-Oscillator-Based Physical Unclonable Function/True Random Number Generator Module for Secure Key Management.” Sensors, vol. 24, no. 17, p. 5674, 2024

    2024

  3. [11]

    An all- digital unified physically unclonable function and true random number generator featuring self-calibrating hierarchical von neumann extraction in 14-nm tri-gate CMOS

    S. K. Satpathy, S. K. Mathew, R. Kumar, V . Suresh, M. A. Anders, H. Kaul, A. Agarwal, S. Hsu, R. K. Krishnamurthy, and V . De, “An all- digital unified physically unclonable function and true random number generator featuring self-calibrating hierarchical von neumann extracti...

    2019

  4. [12]

    Security primitives (puf and trng) with stt-mram,

    E. I. Vatajelu, G. Di Natale, and P. Prinetto, “Security primitives (puf and trng) with stt-mram,” in VTS, 2016, pp. 1–4

    2016

  5. [13]

    A morphable physically unclonable function and true random number generator using a commercial magnetic memory,

    M. N. I. Khan, C. Y . Cheng, S. H. Lin, A. Ash-Saki, and S. Ghosh, “A morphable physically unclonable function and true random number generator using a commercial magnetic memory,” in ISQED, 2020, pp. 197–197

    2020

  6. [14]

    The use of physical unclonable functions for true random number sequences generation

    S. S. Zalivako and A. A. Ivaniuk, “The use of physical unclonable functions for true random number sequences generation.” Automatic Control and Computer Sciences , vol. 47, no. 3, pp. 156 – 164, 2013

    2013

  7. [15]

    Physical unclonable function (puf) based random number generator

    A. Sadr and M. Zolfaghari-Nejad, “Physical unclonable function (puf) based random number generator.” Advanced Computing: An Interna- tional Journal, vol. 3, pp. 139 – 145, 2012

    2012

  8. [16]

    Design of true random numbers generators with ternary physical unclonable functions

    B. F. Cambou, “Design of true random numbers generators with ternary physical unclonable functions.” Advances in Science, Technology and Engineering Systems Journal , vol. 3, pp. 15 – 29, 2018

    2018

  9. [17]

    TROT: A Three-Edge Ring Oscillator Based True Random Number Generator With Time-to-Digital Conver- sion,

    M. Gruji ´c and I. Verbauwhede, “TROT: A Three-Edge Ring Oscillator Based True Random Number Generator With Time-to-Digital Conver- sion,” IEEE Transactions on Circuits and Systems I: Regular Papers , vol. 69, no. 6, pp. 2435–2448, 2022

    2022

  10. [18]

    A High-Performance and Secure TRNG Based on Chaotic Cellular Automata Topology,

    Y . Luo, W. Wang, S. Best, Y . Wang, and X. Xu, “A High-Performance and Secure TRNG Based on Chaotic Cellular Automata Topology,” IEEE Transactions on Circuits and Systems I: Regular Papers , vol. 67, no. 12, pp. 4970–4983, 2020

    2020

  11. [19]

    Sponge-based pseudo-random number generators,

    G. Bertoni, J. Daemen, M. Peeters, and G. Van Assche, “Sponge-based pseudo-random number generators,” in Cryptographic Hardware and Embedded Systems, CHES 2010 , S. Mangard and F.-X. Standaert, Eds. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010, pp. 33–47

    2010

  12. [20]

    A statistical test suite for random and pseudorandom number generators for cryptographic applications,

    A. Rukhin, S. Soto, J. Nechvatal, M. Smid, E. Barker, S. Leigh, M. Levenson, M. Vangel, D. Banks, N. Heckert, J. Dray, S. V o, and L. Bassham, “A statistical test suite for random and pseudorandom number generators for cryptographic applications,” National Institute of Standar...

  13. [21]

    Recommendation for the entropy sources used for random bit generation,

    M. Turan, E. Barker, J. Kelsey, K. McKay, M. Baish, and M. Boyle, “Recommendation for the entropy sources used for random bit generation,” National Institute of Standards and Technology, Special Publication 800-90B, 2018. [Online]. Available: https://doi.org/10.6028/NIST.SP.800-90B

    2018 doi

  14. [22]

    A proposal for: Functionality classes for random number generators,

    W. Killman and W. Schindler, “A proposal for: Functionality classes for random number generators,” Bundesamt f ¨ur Sicherheit in der Informa- tionstechnik (BSI), Technical Guideline, Sept. 2011

    2011

  15. [23]

    DieHarder: A Random Number Test Suite,

    R. G. Brown, D. Eddelbuettel, and D. Bauer, “DieHarder: A Random Number Test Suite,” https://webhome.phy.duke.edu/ rgb/General/dieharder.php

  16. [24]

    [Online]

    ZYBO Reference Manual, 2014. [Online]. Available: https://digilent.com

    2014

  17. [2010]

    Available: https://doi.org/10.6028/NIST.SP.800-22r1a

    [Online]. Available: https://doi.org/10.6028/NIST.SP.800-22r1a

    doi

Pith tools

Reviewed August 6, 2026 · model on record in the stance chip above.