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A Large Language Model-based Multi-Agent Framework for Analog Circuits' Sizing Relationships Extraction

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arxiv 2506.18424 v1 pith:253GBAKY submitted 2025-06-23 cs.AI cs.ET

classification cs.AIcs.ET
keywords sizinganalogcircuitsearchspacecircuitsframeworkoptimization
verification ladder T0 review T1 audit T2 compute T3 formal
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abstract

In the design process of the analog circuit pre-layout phase, device sizing is an important step in determining whether an analog circuit can meet the required performance metrics. Many existing techniques extract the circuit sizing task as a mathematical optimization problem to solve and continuously improve the optimization efficiency from a mathematical perspective. But they ignore the automatic introduction of prior knowledge, fail to achieve effective pruning of the search space, which thereby leads to a considerable compression margin remaining in the search space. To alleviate this problem, we propose a large language model (LLM)-based multi-agent framework for analog circuits' sizing relationships extraction from academic papers. The search space in the sizing process can be effectively pruned based on the sizing relationship extracted by this framework. Eventually, we conducted tests on 3 types of circuits, and the optimization efficiency was improved by $2.32 \sim 26.6 \times$. This work demonstrates that the LLM can effectively prune the search space for analog circuit sizing, providing a new solution for the combination of LLMs and conventional analog circuit design automation methods.

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