MEDEA: A Design-Time Multi-Objective Manager for Energy-Efficient DNN Inference on Heterogeneous Ultra-Low Power Platforms

David Atienza; Hossein Taji; Jos\'e Miranda; Miguel Pe\'on-Quir\'os

REVIEW 3 major objections 6 minor 1 cited by

MEDEA: A Design-Time Multi-Objective Manager for Energy-Efficient DNN Inference on Heterogeneous Ultra-Low Power Platforms

T0 review · 3 major / 6 minor · reviewed 2026-08-15 · deepseek-v4-flash

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Pith's one-line read A design-time scheduler that chooses per-kernel processor, voltage-frequency, and tiling can reduce DNN inference energy by up to 38% on ultra-low-power heterogeneous chips while meeting deadlines.

desk verdict Solid systems integration with a real hole in the optimality argument; worth reviewing, but the claim needs to be fixed or softened. read the letter →

arxiv 2506.19067 v3 pith:CI6KL5Q4 submitted 2025-06-23 cs.AR

Hossein Taji , José Miranda , Miguel Peón-Quirós , David Atienza This is my paper · ORCID

classification cs.AR

keywords ultra-lowpowersystemsDNNinferenceschedulingheterogeneousprocessingelementskernel-levelDVFSmemory-awaretilingdesign-timeoptimizationtransformerseizuredetectionmultiple-choiceknapsackproblem

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper proposes MEDEA, a design-time manager that decides for each kernel of a DNN which processing element should run it, at which voltage-frequency point, and with which memory tiling mode. The aim is to minimize total energy for one inference window while respecting an application deadline. Using a heterogeneous ultra-low-power platform with a RISC-V core plus two accelerators, the authors show that per-kernel choices outperform baselines that pick one accelerator or one voltage for the whole workload, with energy savings up to 38 percent and all timing constraints met. A reader should care because these are the decisions a wearable or implantable device must make to run AI within milliwatt power budgets, and the paper gives a concrete recipe for computing them ahead of time.

What carries the argument

The load-bearing object is the per-kernel execution configuration $\omega_{ij} = (p_{ij}, v_{ij}, c_{ij})$: a processor, a voltage/frequency operating point from the platform's discrete V-F set, and a tiling mode (single- or double-buffered). A timing model $G_T(\cdot)$ converts profiled cycle counts and data-movement cycles into execution time, and power profiles supply active and idle power; together they give each configuration an energy cost and a time weight. MEDEA pre-selects the faster tiling mode for each processor/V-F pair, then solves a multiple-choice knapsack problem with the deadline as capacity and total active energy as the objective, using an ILP solver to pick exactly one configuration per kernel. This mechanism makes the scheduling problem a finite combinatorial optimization that can be solved at design time.

What would settle it

Fabricate the HEEPTimize chip, run the TSD workload at the 200 ms deadline using MEDEA's schedule, and compare measured end-to-end latency and total energy against the predicted 200.0 ms and 395 µJ; a deadline miss or an energy total above the prediction by more than the model's margin would contradict the central claim.

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Extended reading notes

Core claim

MEDEA's central claim is that the energy-optimal execution of a DNN on a heterogeneous ULP platform is found by co-optimizing three kernel-level knobs: processor assignment, voltage/frequency setting, and single- versus double-buffered tiling, all under a hard deadline. The paper models each kernel as an item group whose configurations have an energy cost and a time weight, casts the whole workload as a multiple-choice knapsack problem, and solves it with integer linear programming. Evaluated on the HEEPTimize platform running a Transformer seizure-detection model, this yields 14%, 38%, and 7% energy reductions over the strongest baseline at 50 ms, 200 ms, and 1000 ms deadlines, while always completing within the deadline. The paper further claims that the relative energy efficiency of the two accelerators crosses over as voltage changes, so the best processor for a kernel can depend on the deadline.

Load-bearing premise

The central results assume that cycle counts measured on an FPGA and power numbers estimated by an ASIC design flow reflect real fabricated silicon closely enough that MEDEA's predicted energies and deadlines are accurate; if either estimate is wrong, the claimed energy savings and deadline guarantees would not hold on physical hardware.

Editorial extensions

If this is right

Under MEDEA's model, finishing earlier than the deadline is never beneficial when idle power is positive, because any faster schedule costs more active energy and leaves a longer sleep interval.
Kernel-level DVFS contributes the largest share of the savings: 31.3% at the 200 ms deadline, while contributing nothing at 1000 ms because all kernels already run at the lowest V-F point.
Adaptive tiling, choosing single- versus double-buffering per kernel, yields 4.8% to 8.5% energy savings across the tested deadlines.
The optimal processor for a kernel can switch with the deadline; as voltage drops, the CGRA becomes relatively more energy-efficient than the NMC, so PE selection and V-F selection must be co-optimized.
A schedule that meets the deadline and minimizes active energy can be extracted directly from the ILP solution and applied at runtime without further search.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The paper's formulation does not depend on transformers; any DNN expressible as a sequence of supported kernels could be scheduled the same way once profiles exist, so the method should extend to CNNs, GNNs, and other workloads without changing the optimizer.
The measured efficiency crossover between the two accelerators suggests that PE rankings are voltage-dependent; if that pattern holds generally, hardware selection for ULP systems should be characterized per V-F point rather than per PE.
Because the search is done at design time, the method's practical cost is offline; one extension would be to precompute schedules for a library of DNNs and deadlines, then load the appropriate schedule at runtime.
The paper stops short of validating on fabricated silicon; a natural follow-up is to measure the same schedules on the real chip and compare energy and latency against the model predictions.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Quick take: this is a credible design-time scheduler for heterogeneous ULP platforms, and the integration it does—kernel-level DVFS, per-kernel scheduling, adaptive tiling, deadline-aware energy minimization—is genuinely new relative to the cited literature. But the paper's optimality argument has a hole that the authors' own Figure 7 exposes. I'd still send it to reviewers, with a clear request to fix or reframe the claim.

What's good: The problem is real. Most existing DNN deployment work either ignores DVFS, schedules at block-level, or doesn't handle tiling under tight memory. MEDEA solves an MCKP over per-kernel configurations on a concrete platform (HEEPTimize) with a plausible characterization pipeline. The evaluation uses a transformer-based seizure detection model, which is a good test case. The feature ablation (DVFS, scheduling, tiling) is a nice way to separate contributions. The paper is honest about the FPGA/EDA characterization.

Where it's soft: Section 3.3 claims that any faster schedule must use higher V-F and thus higher active energy, so the optimal policy is to minimize active energy while filling the deadline. That reasoning assumes execution time and active energy are monotonically related for each kernel. The paper's own Figure 7 shows the CGRA/Carus energy ratio crosses over as voltage changes. So a faster schedule could move a kernel to the other accelerator at a higher V-F and end up with lower active energy. The proof does not go through. This matters because Eq. (10) is not equivalent to Eq. (7) in general. The ILP solutions are feasible and probably good, but 'globally energy-optimal' is not established. The reported 14/38/7% savings may shift, though I don't think they're likely to reverse.

Second, the deadline compliance is model-estimated, not measured end-to-end. The active times in Table 5 sit exactly on the deadline in the tight cases, which is a clue that the timing model is the arbiter. FPGA cycle counts are real, but power from EDA at 22nm is still an estimate. I'd want the authors to say that plainly in the abstract and conclusions.

Third, no code or data. That's a minor issue for a systems paper, but given the non-fabricated platform, artifacts would help reviewers check the characterization.

Bottom line: This paper deserves a serious referee. It's not a desk reject. The authors have a working manager and a transparent evaluation. They need to either prove (or add conditions for) the monotonicity assumption, or reframe the optimization as a heuristic for minimizing total energy. I'd recommend major revision.

Referee Report

3 major / 6 minor

Summary. The paper introduces MEDEA, a design-time manager for energy-efficient DNN inference on heterogeneous ultra-low-power platforms. MEDEA selects, for each kernel of a sequential DNN workload, a processing element, a voltage/frequency operating point, and a tiling mode, subject to an application-level deadline, and solves the resulting multiple-choice knapsack problem with an ILP. The authors evaluate MEDEA on HEEPTimize, a 22 nm FPGA-prototyped platform with a RISC-V core, an NMC accelerator, and a CGRA, using a transformer-based seizure-detection model. They report energy reductions of up to 38% relative to adapted state-of-the-art baselines while claiming consistent deadline satisfaction, with a feature analysis attributing savings to kernel-level DVFS, kernel-level scheduling, and adaptive tiling.

Significance. If the results hold, the paper makes a useful practical contribution by showing how four previously separate mechanisms—kernel-level DVFS, kernel-level PE scheduling, memory-aware tiling, and deadline-constrained energy optimization—can be integrated into a single design-time flow for heterogeneous ULP platforms. The evaluation on a custom FPGA-prototyped, ASIC-characterized platform, together with the feature-ablation study, is a strength. However, the central claim that the proposed objective exactly minimizes total energy under a deadline is not established, and the deadline-compliance claim rests on a timing model rather than on end-to-end measurement. Because these issues affect the meaning of the reported 38% savings and the 'consistently meeting deadlines' statement, the paper needs revision before its central claims can be accepted.

major comments (3)

[Section 3.3] The reduction of the total-energy objective to active-energy-only minimization is not valid in general and is contradicted by the paper's own observations. The argument in Section 3.3 assumes that any schedule that finishes earlier must use higher V-F settings and therefore has higher active energy. However, Section 5.2 and Figure 7 show that the relative energy efficiency of CGRA versus Carus crosses over across the V-F range, so a faster schedule can reassign kernels to the PE that is more efficient at the higher operating point and thereby achieve both shorter time and lower active energy. In addition, the true objective in Eq. (7) contains the term -P_slp * T_a for schedules finishing before the deadline; with P_slp = 129 uW and the 1000 ms case of Table 5 (T_a = 223 ms, sleep energy = 100 uJ), a slower schedule with slightly higher active energy but longer active time can have lower total energy. The ILP therefore minimizes E_a, not E_t, and the statement that MEDEA 'minimizes energy' under the deadline is not supported. The objective should be changed to E_a - P_slp * T_a (up to a constant) or to the exact E_t, or the paper should be reframed as a heuristic that minimizes active energy only.
[Section 3.3] Pre-selecting the tiling mode that yields the minimum execution cycles for each (PE, V-F) pair discards configurations from Omega_i before the energy optimization. A single-buffer mode can have more cycles than double-buffering but lower energy because it uses fewer and larger data transfers, and it may be the energy-optimal choice when the deadline is slack. Since the pre-selection criterion is execution cycles rather than energy, the resulting configuration set may exclude the global energy optimum. The paper should either optimize over both tiling modes within the ILP or explicitly justify why cycle-minimal tiling is always energy-optimal for the considered platform.
[Section 4.1.2] Deadline compliance is asserted from the timing model G_T, which combines FPGA-measured cycle counts for representative kernels with estimated data-movement cycles, but the paper does not report an end-to-end run of any MEDEA-generated schedule on the FPGA or a comparison between G_T estimates and measured total execution time for the full workload. Given the central claim that MEDEA 'consistently meets all timing requirements,' the paper should provide measured end-to-end validation on the prototype, or at least a quantified bound on G_T error. Without such validation, the deadline-compliance claim is not empirically established.

minor comments (6)

[Section 5.3] The 'w/o KerDVFS' configuration applies a single AppDVFS setting described as the lowest V-F point that allows the schedule to meet the deadline; it is not clear whether this setting is computed by re-solving the scheduling problem or by post-scaling the MEDEA schedule, which could bias the feature-impact comparison.
[Section 4.1.2] Table 5 introduces P_slp = 129 uW as the platform sleep power, but the extraction of this value from the ASIC characterization flow is not described in Section 4.1.2; please clarify how this number was obtained.
[Section 3.1.3] The assumption that power for a given kernel type on a PE and voltage is independent of kernel operational size is stated without validation; for memory-intensive kernels, dynamic power per cycle can vary with data activity. A brief justification or sensitivity check would strengthen the model.
[Throughout] The platform name is written both as 'HEEPtimize' and 'HEEPTimize' in different places; please standardize the spelling.
[Section 6] The conclusion contains a typo: 'this work has proposed a a robust and adaptive manager' should read 'a robust and adaptive manager.'
[Section 3.3] The max(0, T_d - T_a) term in Eq. (7) is redundant given the timing constraint in Eq. (11), which already enforces T_a <= T_d; simplifying the expression would avoid confusion.

Circularity Check

1 steps flagged · score 2.0 of 10

No significant circularity: MEDEA's energy savings are computed from FPGA-measured cycle counts, EDA power characterization, and a standard ILP; the only self-citations are minor, non-load-bearing design conventions.

other [Section 3.1.2 (HULP's Specifications), definition of the V-F operating point set S_vf (Eq. (3))]
"where, consistent with common practice in works like [33], the system is usually operating at the maximum supported frequency, f_l = F_max(v_l), at voltage v_l."

[33] is the authors' own ISLPED 2024 paper, so the max-frequency-per-voltage convention that determines MEDEA's DVFS knob set is imported by self-citation. It is a genuine self-citation of a design convention, but it is not load-bearing: the paper independently derives the f_max values via STA (Table 2), the power decoupling cited to [20] is re-executed with per-voltage PrimePower runs, and the ILP structure would accept any discrete V-F set. The central 38% energy-reduction claim is computed from FPGA cycle counts, EDA power, and the ILP objective, and does not reduce to [33] or [20]. Flagged for completeness; it does not force the reported result.

full rationale

The central derivation is self-contained. MEDEA takes as inputs measured FPGA cycle counts (S_c) and EDA-characterized power (S_P; Section 4.1.2), builds per-configuration energy E_a = G_P x T_a (Eq. (9)), and solves the MCKP/ILP of Eqs. (10)-(13). The reported energy values (Fig. 5, Table 5) and the 14%/38%/7% savings are objective values for MEDEA and for baselines anchored to external literature (e.g., [13,17,23,35,36,2,9,26]), all evaluated with the same profiles. No parameter is fitted to the reported savings, so no fitted input is renamed as a prediction, and no quantity is defined in terms of the target result. Section 5.3's feature ablation compares MEDEA with itself, but that is a standard sensitivity analysis whose percentages are computed from the same profiled inputs, not a fitted prediction. Two supporting conventions are self-cited: the max-frequency-per-voltage practice ([33], Section 3.1.2) and the two-frequency power-decoupling technique ([20], Section 3.1.3); both are re-executed in this paper (STA for Table 2; per-voltage PrimePower runs), so these citations are real supporting evidence, not load-bearing, and the 38% claim does not reduce to them. For completeness, two passages bound the strength of the claims without indicating circularity: Section 3.3's simplification from total energy E_t (Eq. (7)) to active energy E_t,a (Eq. (10)) rests on a monotonicity assertion that the paper's own Fig. 7 efficiency crossover plausibly undercuts (finishing earlier on a different PE at lower V-F can be both faster and cheaper), and Section 4.1.2 concedes that characterization 'in the absence of fabricated silicon' rests on FPGA prototyping plus ASIC-flow estimates. Both are correctness/validation risks, not circularity, because the energy numbers follow from measured inputs and an optimization, not from the claimed outcome.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

No numbers are fitted to make the central result: voltage/frequency points come from static timing analysis, power from post-synthesis PrimePower, cycle counts from FPGA execution, and sleep power from profiling. The load-bearing additions are modeling assumptions, mainly that FPGA/EDA characterization represents silicon, that power is size-independent for a kernel type, and that faster schedules are never energetically preferable. No new physical entities are introduced. The TSD approximations are application-level changes with an explicit accuracy cost, not MEDEA parameters.

assumptions (4)

domain assumption FPGA-prototyped cycle counts and ASIC post-synthesis power simulations represent the target HEEPTimize silicon's timing and energy behavior.
Section 4.1.2 states that characterization was performed in the absence of fabricated silicon, so all energy and deadline results inherit this assumption.
domain assumption For a given kernel type on a given PE at a voltage, power consumption is independent of the kernel's operational size.
Section 3.3 states: 'It is assumed that the power consumption for a given kernel type ... is independent of the kernel's operational size.' This underpins the energy model used in the ILP.
ad hoc to paper Any schedule that finishes earlier than the deadline has higher active energy, so minimizing active energy under the deadline is equivalent to minimizing total energy including sleep power.
Section 3.3, Optimization Objective Rationale, asserts this monotonicity rather than proving it. It can fail when PE assignment changes, because the relative efficiency of CGRA and Carus depends on voltage, as shown in Figure 7.
domain assumption The TSD model approximations, constant softmax, FFT magnitude instead of log-amplitude, and PWL GeLU, preserve acceptable application accuracy.
Section 4.3 reports an F1 drop from 66.6% to 60.3% for the FFT magnitude change and treats it as an acceptable accuracy/energy trade-off. This is an application-level decision, not part of the MEDEA manager itself.

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Cite this review

Pith. "Pith review of MEDEA: A Design-Time Multi-Objective Manager for Energy-Efficient DNN Inference on Heterogeneous Ultra-Low Power Platforms." pith.science (2026). https://pith.science/paper/CI6KL5Q4

@misc{pith2026250619067,
  author       = {Pith},
  title        = {Pith review of: MEDEA: A Design-Time Multi-Objective Manager for Energy-Efficient DNN Inference on Heterogeneous Ultra-Low Power Platforms},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/CI6KL5Q4}},
  note         = {Machine review of arXiv:2506.19067}
}

read the original abstract

The growing demand for on-device AI necessitates energy-efficient execution of DNN based applications on resource-constrained ultra-low power (ULP) platforms. Heterogeneous architectures, combining specialized processing elements (PEs), have emerged as a key solution for achieving the required performance and energy efficiency. However, optimizing energy while executing applications on these platforms requires efficiently managing platform resources like PEs, power features, and memory footprint, all while adhering to critical application deadlines. This paper presents MEDEA, a novel design-time multi-objective manager for energy-efficient DNN inference on Heterogeneous ULP (HULP) platforms. MEDEA uniquely integrates: kernel-level dynamic voltage and frequency scaling (DVFS) for dynamic energy adaptation; kernel-level granularity scheduling, suitable for specialized accelerators; memory-aware adaptive tiling to navigate severe memory constraints; and all within a timing constraint-based optimization strategy, which minimizes energy based on application deadline. To showcase practical viability, we evaluate MEDEA on HEEPtimize, a heterogeneous ULP platform (22 nm, FPGA-prototyped) featuring a RISC-V processor besides Near-Memory Computing (NMC) and Coarse-Grained Reconfigurable Array (CGRA) accelerators. Experimental results, using a biomedical seizure detection case study, demonstrate that MEDEA achieves overall energy reductions of up to 38% compared to representative state-of-the-art methods, while consistently meeting all timing and memory requirements. This effectiveness is attributed to its integrated features, with our analysis showing that kernel-level DVFS alone can be responsible for over 31% of the energy savings in specific scenarios.

Figures

Figures reproduced from arXiv: 2506.19067 by the authors.

**Figure 1.** Overview of the MEDEA design-time multi-objective manager, illustrating its kernel-level decisions on PE, V-F, and Tiling [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗

**Figure 2.** Overview of the MEDEA design-time multi-objective manager, illustrating its inputs, output/knobs, and core management and [PITH_FULL_IMAGE:figures/full_fig_p006_2.png] view at source ↗

**Figure 3.** High-level block diagram of HEEPTimize. 4.1.1 Architecture. HEEPTimize integrates a low-power RISC-V processor with two types of specialized accelerators: an CGRA and an NMC. These three PEs correspond to the set P, Eq. (2), considered by MEDEA. This selection stems from their demonstrated potential for high energy efficiency and computational flexibility in ULP applications [4, 27]. The main controller is the CV32E… view at source ↗

Figures from the paper (5 more)

**Figure 4.** Figure 4: TSD model architecture, illustrating the decomposition into processing kernels (where G=GeLU, SM=SoftMax, T=Transpose, [PITH_FULL_IMAGE:figures/full_fig_p013_4.png]

**Figure 5.** Figure 5: Total energy and active execution time of one window while running the TSD model using MEDEA versus baseline schedulers [PITH_FULL_IMAGE:figures/full_fig_p015_5.png]

**Figure 6.** Figure 6: Snapshot of MEDEA scheduling decisions (PE allocation and V-F level per kernel) for a portion of the TSD transformer workload [PITH_FULL_IMAGE:figures/full_fig_p016_6.png]

**Figure 7.** Figure 7: TSD matmul subset: Ratio of CGRA performance and energy metrics (Energy, Power, Time) over Carus metrics versus V-F [PITH_FULL_IMAGE:figures/full_fig_p017_7.png]

**Figure 8.** Figure 8: Energy saving when selectively disabling core MEDEA features for the TSD model under different timing constraints. [PITH_FULL_IMAGE:figures/full_fig_p018_8.png]

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