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REVIEW 4 major objections 6 minor 43 references

Data-Driven Power Modeling and Monitoring via Hardware Performance Counter Tracking

T0 review · 4 major / 6 minor · reviewed 2026-08-06 · deepseek-v4-flash

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Pith's one-line read The paper claims that an automated, DVFS-aware lookup-table power model built from hardware performance counters estimates instantaneous power to an average 7.5% error and energy to 1.3% error on the NVIDIA Jetson AGX Xavier, with online…

desk verdict A solid, well-engineered power-modeling paper with a real kernel contribution, but the headline accuracy and overhead numbers are narrower than the abstract suggests. read the letter →

arxiv 2506.23672 v1 pith:EL3JCOEC submitted 2025-06-30 cs.PF cs.AR

Sergio Mazzola , Gabriele Ara , Thomas Benz , Björn Forsberg , Tommaso Cucinotta , Luca Benini This is my paper · ORCID
classification cs.PFcs.AR
keywords powermodelingperformancemonitoringcountersDVFSruntimeestimationLinuxkernelheterogeneousembeddedsystemslookuptablemodelNVIDIAJetsonAGXXavier
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper claims that accurate, low-overhead online power measurement for heterogeneous embedded systems can be built from hardware performance counters alone, without microarchitectural knowledge. Its method profiles each sub-system's counters, keeps those most linearly correlated with measured power at each DVFS state, and trains a separate simple linear model for each state. These per-subsystem models are combined into a lookup table so that total power is the sum of a CPU term and a GPU term. On the NVIDIA Jetson AGX Xavier, the combined model reports an average instantaneous power error of 7.5% and an energy error of 1.3%, with those numbers holding for realistic CPU/GPU frequency combinations; across all tested combinations the average power error is 8.6%. The authors also present Runmeter, an in-kernel counter-sampling framework that evaluates the model online with a worst-case overhead of 0.7%, which would make power-aware DVFS and scheduling practical in the OS.

What carries the argument

The load-bearing mechanism is the lookup table $\mathrm{LUT}[d, f_d]$ holding one linear model per sub-system $d$ and DVFS state $f_d$. The characterization pipeline normalizes PMC counts by the sampling period, runs a linear regression of each event against measured power, discards events with $p>0.05$, ranks survivors by Pearson correlation, then picks a compatible subset that the PMU can count simultaneously; NNLS trains the final weights. At runtime, Runmeter uses a moving window that decouples how often counters are read from how long an observation window spans, and evaluates the linear model with fixed-point arithmetic so estimates stay cheap enough for kernel-level use.

What would settle it

Run a workload at an extreme frequency mismatch on the same board, such as CPU at 2.3 GHz with GPU at 115 MHz, and compare the model's online estimate against the onboard sensor over repeated trials; if the average error is substantially larger than 7.5% while CPU/GPU frequencies are held constant, the independence assumption is the limiting factor.

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Extended reading notes

Core claim

The central discovery is that DVFS-aware power estimation can be reduced to a lookup table of per-subsystem linear models, one entry per sub-system and frequency, with predictors chosen automatically by linear correlation and weights trained by non-negative least squares. Each model has the form $P_d = L_d + \sum_i (x_i/T) w_i$, where $x_i$ are PMC counts normalized by sampling period, $L_d$ captures leakage, and non-negative weights keep the terms physically meaningful. Because frequency is factored out through the lookup table, the nonlinear voltage-frequency behavior is absorbed into different table entries, and the total power is computed as a simple sum over sub-systems. The paper reports that this approach reaches the stated accuracy on a heterogeneous NVIDIA board and shows that its fixed-point in-kernel implementation loses at most 0.8% relative to floating point.

Load-bearing premise

The load-bearing assumption is that the CPU's and GPU's power draw add up independently, so the total is just the sum of the two per-subsystem models; when one sub-system stalls waiting on the other, the model cannot see the interaction and the headline accuracy no longer holds.

Editorial extensions

If this is right

  • The same automated pipeline can be rerun on a new board or after a hardware revision, since only benchmarks and PMC traces are needed, not a manual architectural study.
  • Because the model is a sum of per-subsystem terms, online estimates expose how much power comes from the CPU and how much from the GPU, enabling task-level attribution.
  • The fixed-point kernel implementation keeps the model's accuracy loss below 0.8%, so the offline accuracy carries over to online monitoring.
  • At a 10 Hz sampling rate with under 1% worst-case overhead, the estimates are fast enough to close a DVFS or scheduling control loop in the kernel.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The paper leaves open whether the same LUT structure extends to other accelerators on the same SoC; a natural test is adding the video or deep-learning accelerator as additional entries in $D^*$.
  • The independence assumption suggests a testable boundary: workloads with extreme frequency asymmetry expose the model's main failure mode, and adding a cross-term or a stall-state feature would likely recover accuracy there.
  • Because the ground truth is a 200 mW-resolution onboard sensor, the true model ceiling may be better than reported; an external high-resolution measurement setup would settle how much of the 7.5% is sensor-limited.
  • The selected PMCs themselves could seed a hybrid model, using them as a starting point for architectural refinement rather than as the final black box.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 6 minor

Summary. The paper presents a data-driven methodology for PMC-based power modeling of heterogeneous embedded platforms, decomposing the system into per-subsystem linear models stored in a DVFS-aware lookup table and trained via non-negative least squares. The authors also introduce Runmeter, an open-source Linux kernel module for PMC sampling and online model evaluation. On an NVIDIA Jetson AGX Xavier, the combined CPU+GPU model is reported to achieve an average instantaneous power MAPE of 7.5% and an energy error of 1.3%, with Runmeter adding a worst-case overhead of 0.7%.

Significance. If the claims hold, the paper would make a useful contribution: an automated, architecture-agnostic, decomposable, and low-overhead alternative to hand-tuned analytical power models, with public code and kernel integration. The NNLS-based training, PMU-aware counter selection, and fixed-point in-kernel implementation are well-motivated. The CPU monitor is carefully validated, and the overhead measurements are useful. However, the headline accuracy and overhead figures are only demonstrated under restricted conditions, and the validation methodology is not sufficient to support the stated generalization.

major comments (4)
  1. [§5.3, Abstract] The headline numbers 7.5% MAPE and 1.3% energy error are reported only for the restricted frequency range fGPU > 600 MHz; over all CPU/GPU frequency combinations the model's average MAPE is 8.6% and the energy error is 2.5%. The justification that divergent-frequency operation is 'highly unlikely' is an assertion, not a measurement of actual workload frequency residency. As the abstract presents the 7.5%/1.3% figures as the overall result, the central accuracy claim is conditional on an untested operating-region assumption and must be rephrased or supported by workload-distribution data.
  2. [§5.2.2, §5.3] The validation uses a random 70/30 split of the same benchmark workloads used for training, and the number of PMCs (e.g., eight for the GPU) and the p-value threshold are tuned using the validation set. This procedure does not demonstrate generalization to unseen workload behavior, and the reported errors are likely optimistic. A held-out workload set, leave-one-workload-out cross-validation, or an independent benchmark suite is needed to support the claim of a 'dataset-independent result' made in §3.2.
  3. [§4, §5.4.3] The 0.7% worst-case overhead is measured only for the in-kernel CPU power model. The complete CPU+GPU model, which tracks eight GPU PMCs per frequency and reconfigures the tracked counter set on DVFS changes, is never executed inside Runmeter. Therefore the abstract's claim that Runmeter provides low-overhead online execution of the complete model is not supported by the evaluation; the overhead of the full subsystem set, including GPU counter sampling and LUT reconfiguration, remains undemonstrated.
  4. [§3.4, Eq. (2)] The linear composition in Eq. (2) rests on the assumption of power independence among subsystems, which the paper itself shows to fail in §5.3 for low fGPU relative to fCPU, where CPU stall behavior is not captured. The paper's response—excluding such cases—makes the model's validity domain a design choice rather than a consequence of the modeled physics. A concrete test, such as profiling the frequency residency of representative real workloads and reporting the error distribution with and without the filter, would make the restriction transparent and the accuracy claim meaningful.
minor comments (6)
  1. [Figure 5] The y-axis label reads 'Power [mW]', but the plotted values (e.g., 10–15 in the bottom panel) are implausible for milliwatts and are presumably watts; please correct the unit.
  2. [Table 1] The use of '✓✓✓' and '≈≈≈' symbols is not standard and is difficult to decode; provide a legend or use conventional check/cross marks.
  3. [§5.2.2] The sentence reporting 'MAPE between 3% and 4.4% ... with a standard deviation of approximately 5%' is ambiguous: the standard deviation likely refers to the per-workload MAPE spread, but it should be stated explicitly.
  4. [§5.4.2] The online CPU energy MAPE is about 9%, notably higher than the offline CPU MAPE of 3–4.4%; this discrepancy is attributed to transients in the text, but it deserves a brief quantitative discussion, for example the fraction of samples in transient phases.
  5. [Eq. (4)] The underbrace in Eq. (4) appears malformed or, at least, the derivation of the simplified summation is not clearly stated; please rewrite for readability.
  6. [General] The paper extends prior work [12] but does not explicitly list the concrete differences in methodology or evaluation; a short paragraph in the introduction enumerating what is new relative to [12] would help readers place the contribution.

Circularity Check

1 steps flagged · score 4.0 of 10

Headline accuracy is partially self-selected: the number of GPU PMCs is chosen on validation error, and the same validation set yields the quoted MAPE.

  1. fitted input called prediction [Section 3.3 (Platform Characterization) and Section 5.2.1/5.2.2 (GPU modeling and validation)]
    "The optimal number of PMCs with respect to model accuracy can be defined by iteratively considering the estimation error results from the model evaluation step (Figure 1, 11 ). [...] through the validation step, we find that a number of eight PMCs per frequency is the optimal trade-off between model evaluation time and the power estimate accuracy."

    The model-selection hyperparameter (the number of GPU PMCs) is tuned by minimizing error on the validation set, and the same validation set is then used to report the headline accuracy: 'Comparing the instantaneous power consumption estimation with the data measured on the real platform, we obtain a MAPE between 6% and 8%' and, after frequency filtering, 'an instantaneous power MAPE of 7.5%'. The reported prediction error is therefore partly the objective used to select the model, not an independent evaluation of a fixed architecture. This is a validation-set-selection bias rather than a full collapse: the NNLS regression weights themselves are trained on a separate 70% split, so the derivation is not equivalent to its input by construction.

full rationale

The paper's central claim is an empirical fit: NNLS regression of PMC rates on INA3221 power measurements, evaluated on a 30% holdout of the same benchmark suite. That part is not circular: the reported MAPE is computed on data not used to fit the regression weights, and the methodology does not assume the conclusion. No load-bearing self-citation was found: reference [12] supplies the PMU-compatibility heuristic and a benchmark, but the accuracy evaluation is performed here on the Jetson AGX Xavier and the heuristic is described in the text rather than invoked as an external uniqueness theorem. The one partial circularity is architectural model selection: the number of GPU PMCs (eight) is chosen by iterating on validation error, and the same validation set then produces the quoted 6-8% GPU MAPE and the 7.5% combined MAPE. The headline number is therefore not an independent test of the final architecture; it is partially the objective used to select it. This is a validation-set-selection issue rather than a derivation-collapsing circularity, because the regression weights are fitted on a separate 70% split. The exclusion of fGPU <= 600 MHz and the fact that the complete CPU+GPU model is not exercised inside Runmeter are reporting/scope concerns, not circularity.

Assumptions & free parameters 3 free parameters · 4 assumptions · 0 invented entities

The central model is a fitted linear regression; its weights and selected counters are the main fitted degrees of freedom. The evaluation depends on a set of domain assumptions (independence, linearity, sensor fidelity, workload representativeness) that are stated but only partially validated. No new physical entities are introduced.

free parameters (3)
  • NNLS regression weights (L_d and w_i) = not listed in paper
    For each subsystem and DVFS state, a linear model is trained with non-negative least squares on PMC rates and measured power (Sections 3.4, 5.2). These weights are the core fitted parameters.
  • Number of PMCs per subsystem/frequency = CPU: 3 configurable + cycle counter; GPU: 8
    Selected through validation to trade accuracy versus overhead (Section 5.2.1). The optimal count is chosen from the validation set, not a held-out test set.
  • p-value threshold for counter retention = 0.05
    Counters with p > 0.05 in LLS regression are discarded (Section 3.3). This cutoff is a hand-set hyperparameter.
assumptions (4)
  • domain assumption Power consumption of subsystems is independent and sums linearly
    The LUT reduction sum in Eq. (2) assumes P_total = sum P_d. Stated in Sections 3.1 and 3.4, and acknowledged to fail when fGPU is low relative to fCPU in Section 5.3.
  • domain assumption PMC rates linearly predict subsystem power within a fixed DVFS state
    The model form in Eq. (3) is a linear combination of counter rates plus a leakage constant; NNLS assumes linearity and non-negative weights.
  • domain assumption The built-in INA3221 sensor provides a usable ground truth
    Training and validation labels come from the onboard sensor with 200mW resolution (about 3% of measured power). The paper acknowledges this limits achievable accuracy.
  • domain assumption The benchmark suite covers representative workload behaviors
    Rodinia plus synthetic stress tests are used for training and validation; the 70/30 split is random, so held-out data is from the same distribution (Sections 3.2, 5.2).

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Cite this review

Pith. "Pith review of Data-Driven Power Modeling and Monitoring via Hardware Performance Counter Tracking." pith.science (2026). https://pith.science/paper/EL3JCOEC

@misc{pith2026250623672,
  author       = {Pith},
  title        = {Pith review of: Data-Driven Power Modeling and Monitoring via Hardware Performance Counter Tracking},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/EL3JCOEC}},
  note         = {Machine review of arXiv:2506.23672}
}
read the original abstract

Energy-centric design is paramount in the current embedded computing era: use cases require increasingly high performance at an affordable power budget, often under real-time constraints. Hardware heterogeneity and parallelism help address the efficiency challenge, but greatly complicate online power consumption assessments, which are essential for dynamic hardware and software stack adaptations. We introduce a novel power modeling methodology with state-of-the-art accuracy, low overhead, and high responsiveness, whose implementation does not rely on microarchitectural details. Our methodology identifies the Performance Monitoring Counters (PMCs) with the highest linear correlation to the power consumption of each hardware sub-system, for each Dynamic Voltage and Frequency Scaling (DVFS) state. The individual, simple models are composed into a complete model that effectively describes the power consumption of the whole system, achieving high accuracy and low overhead. Our evaluation reports an average estimation error of 7.5% for power consumption and 1.3% for energy. We integrate these models in the Linux kernel with Runmeter, an open-source, PMC-based monitoring framework. Runmeter manages PMC sampling and processing, enabling the execution of our power models at runtime. With a worst-case time overhead of only 0.7%, Runmeter provides responsive and accurate power measurements directly in the kernel. This information can be employed for actuation policies in workload-aware DVFS and power-aware, closed-loop task scheduling.

Figures

Figures reproduced from arXiv: 2506.23672 by the authors.

Figure 1
Figure 1. Scheme of the proposed data-driven, automatic power modeling approach for [PITH_FULL_IMAGE:figures/full_fig_p011_1.png] view at source ↗
Figure 2
Figure 2. Instantaneous power estimate over the validation set for the system-level power [PITH_FULL_IMAGE:figures/full_fig_p020_2.png] view at source ↗
Figure 3
Figure 3. Distribution of approximation error between floating-point and fixed-point [PITH_FULL_IMAGE:figures/full_fig_p024_3.png] view at source ↗
Figures from the paper (2 more)
Figure 4
Figure 4. Figure 4: Distribution of the APE of the online energy estimates over the duration of each [PITH_FULL_IMAGE:figures/full_fig_p024_4.png]
Figure 5
Figure 5. Figure 5: Comparison of the instantaneous CPU power consumption measurement provided [PITH_FULL_IMAGE:figures/full_fig_p025_5.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

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Reviewed August 6, 2026 · model on record in the stance chip above.