Paper Citation Record · LEDGER

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification

As of 10 August 2026, this Paper Citation Record lists 45 of 45 outbound references and 3 inbound Pith citation observations for arXiv:2507.04276.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2507.04276 v1

Coverage vector

measured 45 of 45 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-06T19:58:09.740831Z

measured 48 of 48 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-10T06:31:04.303077+00:00

measured 3 of 3 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-05T05:50:29.940447Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-05-21T06:54:01.150104Z

Reference resolution

45 of 45 outbound references displayed

verified exact0
verified fuzzy42
unresolved3
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation 0e53dca8-250b-44ac-92d6-c0185779e852 · outbound

This paper cites Gpt4aigchip: Towards next-generation ai accelerator design automation via large language models.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Gpt4aigchip: Towards next-generation ai accelerator design automation via large language models

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:17.389822Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 9ad825e7-1ed2-42dc-9a92-e0c1c7bb8522 · outbound

This paper cites Chatcpu: An agile cpu design & verification platform with llm.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Chatcpu: An agile cpu design & verification platform with llm

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:17.222405Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 4cb16823-069b-46f2-872f-8bdb2e82c861 · outbound

This paper cites (security) assertions by large language models.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification (security) assertions by large language models

Reference 3

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:17.084015Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation e2537a76-8ba2-4bdd-b3b6-9f3def3a264f · outbound

This paper cites Meic: Re-thinking rtl debug automation using llms.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Meic: Re-thinking rtl debug automation using llms

Reference 4

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:16.899152Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 80233273-dd69-413b-a21c-933a9e0afae5 · outbound

This paper cites Verilogeval: Evaluating large language models for verilog code genera- tion.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Verilogeval: Evaluating large language models for verilog code genera- tion

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:16.734731Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 3385fc1b-99b3-4c0e-ac1b-08f5c9161d29 · outbound

This paper cites Llm4sechw: Leveraging domain-specific large language model for hardware debugging.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Llm4sechw: Leveraging domain-specific large language model for hardware debugging

Reference 6

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:16.590161Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 2d040a57-fb36-4b19-afde-e0058242a738 · outbound

This paper cites What’s missing in agile hardware design? verification! J.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification What’s missing in agile hardware design? verification! J

Reference 7

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:16.485730Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 59eaa53d-6f5d-4fc5-8274-89313cd9b5de · outbound

This paper cites H ¨am¨al¨ainen.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification H ¨am¨al¨ainen

Reference 8

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:16.350575Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation d02b70b4-c1e3-4e20-bdfb-37929e60ca6c · outbound

This paper cites Delivering Functional Verification Engagements.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Delivering Functional Verification Engagements

Reference 9

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:16.233335Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation da1977ea-2ff9-4136-acd5-525e6ca73c88 · outbound

This paper cites Chip-chat: Challenges and opportunities in conversational hardware design.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Chip-chat: Challenges and opportunities in conversational hardware design

Reference 10

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:16.114966Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 3b70d61d-9172-4139-a513-6df3d732ec1d · outbound

This paper cites Directed test generation for hardware validation: A survey.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Directed test generation for hardware validation: A survey

Reference 11

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:16.016264Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation ecc4edaf-d397-41f6-b8a3-f9f81d14138e · outbound

This paper cites Electronic Design Automation: Synthesis, Verification, and Test.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Electronic Design Automation: Synthesis, Verification, and Test

Reference 12

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:15.897753Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 8f61c2ff-c9db-4515-9e6f-0bfee7c37160 · outbound

This paper cites Formal and simulation verification: Comparing and contrasting the two verification approaches.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Formal and simulation verification: Comparing and contrasting the two verification approaches

Reference 13

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:15.783169Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation d1d0ef85-5a18-4e27-a6c8-fbd3572ccc6c · outbound

This paper cites Functional verification 2003: technology, tools and methodology.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Functional verification 2003: technology, tools and methodology

Reference 14

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:15.664470Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 3943858f-bcc5-462c-a4de-201093b2ea6d · outbound

This paper cites an unresolved cited work.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Unresolved cited work

Reference 15

Resolution: unresolved; raw_fallback, observed 2026-08-06T19:58:15.490804Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 67a4c1d0-c95a-4ede-8fd0-75409632176c · outbound

This paper cites Greenstreet.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Greenstreet

Reference 16

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:15.310176Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation e1117e50-f160-46a0-b04d-a8c00647ebc3 · outbound

This paper cites RTL Formal Verification, pages 103–129.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification RTL Formal Verification, pages 103–129

Reference 17

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:15.102652Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 34313e69-a7a5-4d04-a4a9-82cd015f7fd8 · outbound

This paper cites Towards Developing High Performance RISC-V Processors Using Agile Methodology.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Towards Developing High Performance RISC-V Processors Using Agile Methodology

Reference 18

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:14.911432Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation c5f45238-915c-4db6-a466-27eb98f3eaaa · outbound

This paper cites High-level synthesis, volume 1.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification High-level synthesis, volume 1

Reference 19

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:14.674427Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 759b99d0-82d6-4e8f-a366-0fbb9d36aa94 · outbound

This paper cites System-on-a-chip verification: methodology and techniques.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification System-on-a-chip verification: methodology and techniques

Reference 20

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:14.509597Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation fc43320a-e41b-4220-ace0-3b07ae05ff5f · outbound

This paper cites Verigen: A large language model for verilog code generation.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Verigen: A large language model for verilog code generation

Reference 21

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:14.335883Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 3c0a45a9-f362-4700-b7e7-7468d74ab0cb · outbound

This paper cites BetterV: Controlled verilog generation with discriminative guidance.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification BetterV: Controlled verilog generation with discriminative guidance

Reference 22

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:14.184552Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 256640df-43b9-40a6-b401-c541f87e27b2 · outbound

This paper cites Rtlcoder: Outperforming gpt-3.5 in design rtl generation with our open-source dataset and lightweight solution.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Rtlcoder: Outperforming gpt-3.5 in design rtl generation with our open-source dataset and lightweight solution

Reference 23

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:14.037187Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 8c4b527c-0f43-4179-95d7-e4405667be8b · outbound

This paper cites Rtlfixer: Automatically fixing rtl syntax errors with large language model.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Rtlfixer: Automatically fixing rtl syntax errors with large language model

Reference 24

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:13.885090Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 5aa6fded-6150-4291-8179-dfc5a9cd7903 · outbound

This paper cites Chipgpt: How far are we from natural language hardware design.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Chipgpt: How far are we from natural language hardware design

Reference 25

Resolution: unresolved; no resolver link, observed 2026-08-06T19:58:08.131583Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 0f6e7ad9-45d6-40ee-ba20-ebfc8455d07a · outbound

This paper cites LLM4DV: Using large language models for hardware test stimuli generation.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification LLM4DV: Using large language models for hardware test stimuli generation

Reference 26

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:13.687227Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 262d6368-00b9-43d0-8b29-d94efc113196 · outbound

This paper cites Verilogreader: Llm-aided hardware test gener- ation.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Verilogreader: Llm-aided hardware test gener- ation

Reference 27

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:13.502969Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 3af963cf-91ae-43be-8886-fa625f902237 · outbound

This paper cites Assertllm: Generating hardware verification assertions from design specifications via multi-llms.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Assertllm: Generating hardware verification assertions from design specifications via multi-llms

Reference 28

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:13.360747Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 16d7501f-556c-46d2-ab23-fb6bb5a1d523 · outbound

This paper cites Autobench: Automatic testbench generation and evaluation using llms for hdl design.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Autobench: Automatic testbench generation and evaluation using llms for hdl design

Reference 29

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:13.190102Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation ed2b0642-d6f1-4aaa-aefb-9b0fbaf00534 · outbound

This paper cites Rtllm: An open- source benchmark for design rtl generation with large language model.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Rtllm: An open- source benchmark for design rtl generation with large language model

Reference 30

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:12.966515Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 32500853-a472-48d3-8eb4-c177ce6a5462 · outbound

This paper cites FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware

Reference 31

Resolution: unresolved; no resolver link, observed 2026-08-06T19:58:08.613716Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 91285ab6-a61f-438b-a4c8-844bc1ca33d3 · outbound

This paper cites Specification and design of embed- ded hardware-software systems.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Specification and design of embed- ded hardware-software systems

Reference 32

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:12.695870Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 00b970ec-c3f0-434b-8706-fdc6c3d5ab36 · outbound

This paper cites Behavioral con- sistency of c and verilog programs using bounded model checking.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Behavioral con- sistency of c and verilog programs using bounded model checking

Reference 33

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:12.497888Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 54ca48ee-f19b-4d78-8772-411dfb92a601 · outbound

This paper cites Digital design with RTL design, VHDL, and Verilog.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Digital design with RTL design, VHDL, and Verilog

Reference 34

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:12.354654Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation b0b3fa09-4afe-447e-8c99-b165abc5e81d · outbound

This paper cites Writing testbenches using SystemVerilog.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Writing testbenches using SystemVerilog

Reference 35

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:12.162904Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation b6c141b6-dca3-40f8-922d-a9b79c752913 · outbound

This paper cites SystemVerilog for verification: a guide to learning the testbench language features.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification SystemVerilog for verification: a guide to learning the testbench language features

Reference 36

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:11.944165Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 88e08987-1d3b-4218-91c7-c55568f76af5 · outbound

This paper cites Assertion-based design.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Assertion-based design

Reference 37

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:11.751074Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation a0f39fff-90b6-4c06-9688-caf62ec6350d · outbound

This paper cites Cadre: Cycle- accurate deterministic replay for hardware debugging.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Cadre: Cycle- accurate deterministic replay for hardware debugging

Reference 38

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:11.549035Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 6f2c57e9-3539-465c-b3f1-3ad03a3143fe · outbound

This paper cites Chipnemo: Domain-adapted llms for chip design, 2024.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Chipnemo: Domain-adapted llms for chip design, 2024

Reference 39

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:11.383037Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 93d1f221-b776-4e6c-88c9-5a22a6addb3d · outbound

This paper cites https://opencores.org/.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification https://opencores.org/

Reference 40

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:11.130941Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation f66c8905-9d31-4d7a-a66e-5fd88d50596f · outbound

This paper cites Let me do it for you: Towards llm empowered rec- ommendation via tool learning.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Let me do it for you: Towards llm empowered rec- ommendation via tool learning

Reference 41

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:10.939624Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 211cd06f-1203-4b2d-995d-e626eec58a90 · outbound

This paper cites Flexkbqa: A flexible llm-powered frame- work for few-shot knowledge base question answering.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Flexkbqa: A flexible llm-powered frame- work for few-shot knowledge base question answering

Reference 42

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:10.761096Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 9a61942c-9658-4ece-918b-01d352d4638b · outbound

This paper cites Natural language is not enough: Benchmarking multi-modal generative ai for verilog generation, 2024.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Natural language is not enough: Benchmarking multi-modal generative ai for verilog generation, 2024

Reference 43

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:10.553188Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 8f2f434a-50e5-4772-a818-612cb3566a57 · outbound

This paper cites Vgv: Verilog generation using visual capabilities of multi-modal large lan- guage models.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Vgv: Verilog generation using visual capabilities of multi-modal large lan- guage models

Reference 44

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:10.375488Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 4ad050e5-bad1-462c-b5c1-c2323de961af · outbound

This paper cites Semikong: Curating, training, and evaluating a semiconductor industry-specific large language model.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification Semikong: Curating, training, and evaluating a semiconductor industry-specific large language model

Reference 45

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T19:58:10.165856Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Pith citing papers

Observation 906a3cae-8dbb-43c1-9f09-55e02d796b6d · inbound

Revolution or Hype? Seeking the Limits of Large Models in Hardware Design cites this paper.

Revolution or Hype? Seeking the Limits of Large Models in Hardware Design FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification

Reference 48

Resolution: unresolved; no resolver link, observed 2026-08-05T05:50:29.940447Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 1aae74e9-a6d3-4cfe-aba7-7a0f18e5aa27 · inbound

RefEvo: Agentic Design with Co-Evolutionary Verification for Agile Reference Model Generation cites this paper.

RefEvo: Agentic Design with Co-Evolutionary Verification for Agile Reference Model Generation FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification

Reference 20

Resolution: verified exact; arxiv_id, observed 2026-05-11T22:11:14.654290Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation b7e3a6db-ed67-4195-956d-928466af1167 · inbound

Agentic Agile-V: From Vibe Coding to Verified Engineering in Software and Hardware Development cites this paper.

Agentic Agile-V: From Vibe Coding to Verified Engineering in Software and Hardware Development FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification

Reference 31

Resolution: verified exact; arxiv_id, observed 2026-05-21T06:54:01.151821Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.