Pith. sign in

REVIEW 3 major objections 4 minor 14 references

Manarat: A Scalable QICK-Based Control System for Superconducting Quantum Processors Supporting Synchronized Control of 10 Flux-Tunable Qubits

T0 review · 3 major / 4 minor · reviewed 2026-08-06 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗

Pith's one-line read A multi-board extension of QICK achieves sub-100 ps timing alignment across RFSoC boards, validated by cross-board CZ chevrons on a 10-qubit processor.

desk verdict Useful QICK-extension paper with a plausible but under-quantified sub-100 ps multi-board sync claim; deserves serious review, not desk reject. read the letter →

arxiv 2507.10676 v2 pith:QDMEHDLM submitted 2025-07-14 quant-ph

Agustin Silva , Alvaro Orgaz-Fuertes This is my paper
classification quant-ph
keywords multi-boardsynchronizationRFSoCqubitcontrolQICKflux-tunabletransmonCZgatecalibrationFPGAtimingalignmentsuperconductingquantumprocessor
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper argues that the single-board ceiling of the open-source QICK control system can be broken without abandoning it: by adding a shared low-jitter clock, a wired-AND sync bus, a new tProcessor sync instruction, and a firmware fix that removes fetch jitter, multiple RFSoC boards can run pulse programs in deterministic sub-100 ps alignment. That matters because a 10-qubit flux-tunable processor needs more drive, flux, and readout lines than one RFSoC board provides, and entangling gates across boards require timing precision far below a clock period. The authors validate the claim on a two-board setup driving a commercial 10-qubit flux-tunable transmon chip, showing phase-aligned 4.5 GHz pulses and coherent CZ-type chevron fringes for qubit pairs controlled by different boards. A sympathetic reading is that this is the demonstration of synchronized pulse-level control beyond a single board that QICK lacked.

What carries the argument

The load-bearing mechanism is the pair formed by the Sync instruction with the Sync IP and the modified instruction-fetch logic of the tProcessor. The Sync instruction drives a GPIO line to high impedance to signal readiness and then stalls on an external flag; the wired-AND bus pulls the shared line high only when all boards are ready; the Sync IP in each FPGA detects that edge and releases the tProcessor on a clock-aligned signal. The crucial firmware fix pauses the program counter update immediately after the Sync instruction is fetched, so the external flag is sampled on the very next clock edge identically on every board instead of with the standard +/-2-cycle flush uncertainty.

What would settle it

Take two boards through the documented synchronization sequence and record the rising edges of a repeated square pulse at 1 ps resolution over many trials while varying each tProcessor program's length so that the old two-cycle flush would matter; if the observed inter-board skew ever jumps by a multiple of the 122.88 MHz clock period (about 8.14 ns) or exceeds roughly 100 ps, the fetch_en pause is not doing the claimed work. A complementary check is a cross-board CZ randomized-benchmarking run: if the extracted gate error shows periodic sensitivity to program-length offsets, sub-100 ps alignment alone is not sufficient for coherent two-qubit gates.

Watch

Extended reading notes

Core claim

The central claim is that deterministic, sub-100 ps synchronized program execution across multiple AMD ZCU216 RFSoC boards is achievable by combining four elements: an HMC7044-derived 7.68 MHz reference distributed to each board's LMK04828 in nested zero-delay dual-loop mode; SYSREF-based Multi-Tile Synchronization for the data converters; a custom wired-AND bus plus Sync IP that releases all tProcessors only when every board reports ready; and a tProcessor modification that pauses the program counter update (fetch_en=0) after a Sync instruction until the external flag arrives, eliminating the standard two-cycle fetch uncertainty. With these changes, all boards read the release edge on the same 122.88 MHz clock cycle and resume simultaneously. Oscilloscope overlays show less than 100 ps skew between square pulses from two boards, phase-aligned 4.5 GHz Gaussian pulses, and chevron patterns for cross-board CZ-type interactions on a 10-qubit flux-tunable processor, which the paper presents as evidence of coherent multi-board control.

Load-bearing premise

Deterministic sub-100 ps alignment depends on every board's Sync IP observing the wired-AND release edge on the same 122.88 MHz clock cycle, with the GPIO high-impedance releases and flag chains adding negligible skew; if release edges arrive with cycle-to-cycle or board-to-board skew, the claimed alignment fails even though the clocks themselves are locked.

Editorial extensions

If this is right

  • Cross-board CZ calibration on a two-board system is shown, implying entangling operations can be scheduled across control boards without a separate coincidence stage.
  • Because the synchronization scheme uses one GPIO per board, it scales to at least six boards from a single HMC7044 evaluation board, extending the channel count well beyond the single-board limit.
  • The tProcessor pause fix makes program start times independent of program length and control flow, so conditional branches and feedback loops can be re-synchronized at each experimental repetition.
  • Integration with the Qibo software stack means calibration and algorithm execution can treat the distributed boards as a single virtual device.
  • The 0.17 ns waveform-padding resolution available in the driver enables high-resolution duration sweeps of flux pulses, useful for mapping fast two-qubit interactions.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The same clock-tree and fetch-pause recipe should port to other QICK-compatible RFSoC boards, since the clock-distribution path and tProcessor RTL are shared; a direct test would be re-running the square-pulse skew measurement on a mixed set of board types.
  • The wired-AND release is an all-to-all barrier, well-suited to fixed repeated schedules; extending it to event-driven triggers such as measurement feedback would require a different arbitration scheme, which the paper does not yet claim.
  • The chevron fringes are qualitative evidence; a concrete next step the authors leave implicit is a randomized-benchmarking estimate of cross-board CZ fidelity, which would quantify how much of the sub-100 ps alignment translates into gate error.
  • The demonstrated 4.5 GHz phase alignment across boards could also enable distributed drive tones for cavity or coupler control where two boards cooperate on the same physical mode.
Share X Bluesky LinkedIn Reddit HN

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 4 minor

Summary. The paper describes Manarat, a multi-board control system for superconducting qubits based on the QICK framework. The system uses an HMC7044 clock distribution network feeding LMK04828 clock conditioners on two ZCU216 RFSoC boards, plus a custom wired-AND synchronization bus, a new Sync IP block, and tProcessor firmware modifications intended to make program execution start and resume on the same clock cycle across boards. A custom analog front-end combines DC bias from a DAC80508 with RF flux pulses, and a software orchestration layer integrates with the Qibo/Qibolab stack. Validation consists of oscilloscope overlays of square and 4.5 GHz Gaussian pulses from two boards, a simultaneous flux-dependent resonator spectroscopy across ten qubits, and cross-board CZ-type chevron patterns for two qubit pairs. The central claim is sub-100 ps timing alignment and deterministic multi-board program execution.

Significance. If the sub-100 ps deterministic synchronization claim holds, this is a useful step toward scaling QICK-based control beyond a single RFSoC board, with a clear hardware recipe (HMC7044/LMK04828 clock tree, Sync IP, tProcessor modifications) and a working 10-qubit demonstration. The validation is genuinely external: oscilloscope overlays and qubit response patterns are independent of the system's internal assumptions, so the circularity risk is low. The chevron patterns with clear fringes are a nice demonstration of coherent cross-board control. However, the load-bearing timing evidence is qualitative snapshots rather than quantitative statistics, and the synchronization mechanism has an unaddressed metastability/cycle-slip risk. No firmware or software artifacts are released, which prevents independent reproduction of the central claim. The significance is therefore conditional on tightening the timing evidence.

major comments (3)
  1. [IV.A] The central sub-100 ps claim rests on oscilloscope overlays (Figs. 10 and 11) described only as "two distinct traces" at 100 ps/div. The paper reports no number of captured edges, no skew histogram, no mean/standard deviation/maximum, and no measurement uncertainty. The phrase "thousands of repetitions" is unquantified, and a persistence overlay cannot rule out rare one-cycle slips. Please provide a statistical timing-error characterization, e.g., time-interval error histograms over many events with a worst-case bound, rather than representative snapshots.
  2. [III.C.3-4] The wired-AND release edge is an asynchronous analog transition on a shared line; each board's input buffer, routing, and threshold add board-specific delay. Nothing in the design guarantees that every Sync IP samples this edge on the same 122.88 MHz clock cycle. If the edge lands within the setup/hold window of any sampling register, that board latches one clock later, producing an 8.14 ns skew that is 80 times the claimed bound. Because the tProcessor time counters are reset at sync (Sec. III.C.3), such a slip shifts all subsequent pulses on that board. The manuscript needs an explicit margin analysis or measured cycle-slip statistics showing that the release edge is safely outside all setup/hold windows, or a synchronizer/handshake design that makes a slip impossible.
  3. [IV.B.3] The CZ chevrons in Fig. 14 show coherent oscillations between |11> and |02>, which is consistent with synchronized operation, but the pattern does not provide a quantitative upper bound on cross-board timing error. A constant few-nanosecond offset in flux pulse arrival would barely perturb a chevron, so these data cannot support the sub-100 ps claim. Please either provide a quantitative relationship between timing skew and the chevron/gate observable, or explicitly state that the chevrons only validate sub-nanosecond alignment.
minor comments (4)
  1. [Title and text] There are several typos, including "Flux-T unable" in the title, "lenght" in Sec. III.C.4, "thorugh" in Sec. III.B.3, "biassing" in Sec. IV.B.2, and "Rasberry Pi" in Sec. III.B.2.
  2. [Figs. 9-11] Fig. 9 is referenced before Figs. 10 and 11 and appears to show a more complex sequence; consider reordering the figures for clarity.
  3. [Introduction, ref. [24]] The in-text claim about a Floquet-mode traveling-wave parametric amplifier attributed to Wang et al. [24] does not match the listed reference, whose title is about dielectric spectroscopy. Please correct the citation.
  4. [Abstract and Conclusion] The abstract claims "sub-100 ps timing alignment" while the concluding paragraph states "sub-nanosecond synchronization and coherent control"; use one consistent bound or explain the distinction.

Circularity Check

0 steps flagged · score 2.0 of 10

No significant circularity: the sub-100 ps timing claim is validated by external oscilloscope and qubit measurements, not by construction; the only self-citations are minor software-stack references that are not load-bearing.

full rationale

Manarat is an experimental hardware and software paper rather than a derivation, so the main circularity patterns do not arise. The central sub-100 ps timing alignment claim is supported by external measurements: oscilloscope traces showing a temporal difference of less than 100 picoseconds at 100 ps/div, phase-aligned 4.5 GHz Gaussian pulses, and cross-board CZ chevron patterns on a 10-qubit processor. The chevron is an observed coherent oscillation between |11> and |02>, not a quantity obtained by fitting the synchronization mechanism; no parameter of the timing chain is extracted from the validation data and then reused as a prediction. The tProcessor and Sync IP modifications are described as design mechanisms that improve determinism; the possibility that an asynchronous wired-AND release edge could be sampled one clock cycle later on one board is a robustness and validation gap, not a circular reduction. The Qibo, Qibolab, and Qibocal references include an author overlap, and the paper states that its control stack is fully integrated with the open-source Qibo framework, but this software integration is ancillary to the synchronization claim and is not used to prove it. No equation equates the output to the input by construction, and no imported uniqueness theorem forces the result. Thus there is no load-bearing circularity; at most there is a minor, non-load-bearing self-citation.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

The system introduces no new physical entities or fitted numerical parameters. The claims rest on datasheet-level hardware behavior, clock alignment, MTS, and on a specific interpretation of chevron data; these are stated as domain assumptions rather than demonstrated first principles.

assumptions (4)
  • domain assumption A shared 7.68 MHz reference from the HMC7044 combined with the LMK04828 in nested zero-delay dual-loop mode yields deterministic phase-aligned clocks across all boards.
    Invoked in Sec. III.B.2-3 and III.C.1 to build the clock tree; all later timing claims depend on this alignment.
  • domain assumption The wired-AND Sync bus and Sync IP release every stalled tProcessor on the same 122.88 MHz clock edge, with negligible board-to-board propagation skew.
    This premise is required in Sec. III.C.3-4 for the modified tProcessor to resume at exactly the same cycle; the paper argues for it but does not independently measure the flag-path skew.
  • domain assumption AMD Multi-Tile Synchronization, activated with SYSREF, deterministically aligns RF-DAC and RF-ADC tiles across separate RFSoC devices.
    Used in Sec. III.C.2 to justify phase-aligned 4.5 GHz outputs and the observed MTS behavior in Fig. 11.
  • domain assumption The avoided-crossing model for flux-mediated CZ gates (|11> to |02> coupling) describes the SpinQ 10-qubit processor used in the experiments.
    Adopted in Sec. IV.B.3 to interpret chevron fringes as coherent cross-board two-qubit interaction, citing standard transmon physics rather than an independent calibration of this specific chip.

how reviews work

0 comments
Cite this review

Pith. "Pith review of Manarat: A Scalable QICK-Based Control System for Superconducting Quantum Processors Supporting Synchronized Control of 10 Flux-Tunable Qubits." pith.science (2026). https://pith.science/paper/QDMEHDLM

@misc{pith2026250710676,
  author       = {Pith},
  title        = {Pith review of: Manarat: A Scalable QICK-Based Control System for Superconducting Quantum Processors Supporting Synchronized Control of 10 Flux-Tunable Qubits},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/QDMEHDLM}},
  note         = {Machine review of arXiv:2507.10676}
}
read the original abstract

A scalable control architecture for superconducting quantum processors is essential as the number of qubits increases and coherent multi-qubit operations span beyond the capacity of a single control module. The Quantum Instrumentation Control Kit (QICK), built on AMD RFSoC platforms, offers a flexible open-source framework for pulse-level qubit control but lacks native support for multi-board synchronization, limiting its applicability to mid- and large-scale quantum devices. To overcome this limitation, we introduce Manarat, a scalable multi-board control platform based on QICK that incorporates hardware, firmware, and software enhancements to enable sub-100 ps timing alignment across multiple AMD ZCU216 RFSoC boards. Our system integrates a low-jitter clock distribution network, modifications to the tProcessor, and a synchronization scheme to ensure deterministic alignment of program execution across boards. It also includes a custom analog front-end for flux control that combines high-speed RF signals with software-programmable DC biasing voltages generated by a low-noise, high-precision DAC. These capabilities are complemented by a software stack capable of orchestrating synchronized multi-board experiments and fully integrated with the open-source Qibo framework for quantum device calibration and algorithm execution. We validate Manarat on a 10-qubit superconducting processor controlled by two RFSoC boards, demonstrating reliable execution of synchronized control sequences for cross-board CZ gate calibration. These results confirm that sub-nanosecond synchronization and coherent control is achievable across multiple RFSoC boards, enabling scalable operation of superconducting quantum computers.

Figures

Figures reproduced from arXiv: 2507.10676 by the authors.

Figure 1
Figure 1. FIG. 1: Setup for synchronizing two boards to control up to 12 flux-tunable qubits. A) Rasberry Pi. B) Analog Devices [PITH_FULL_IMAGE:figures/full_fig_p004_1.png] view at source ↗
Figure 2
Figure 2. FIG. 2: Analog Devices HMC7044 clock distribution mod [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. FIG. 3: Simplified functional block diagram illustrat [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figures from the paper (10 more)
Figure 5
Figure 5. Figure 5: FIG. 5: Schematic for the Bias Tee for combining DC and [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 6
Figure 6. Figure 6: FIG. 6: Schematic of Wired-AND circuit to detect when all [PITH_FULL_IMAGE:figures/full_fig_p005_6.png]
Figure 8
Figure 8. Figure 8: FIG. 8: Clock Tree Design Part 2 (Clock generation within [PITH_FULL_IMAGE:figures/full_fig_p006_8.png]
Figure 9
Figure 9. Figure 9: FIG. 9: Synchronized flux, drive, and readout pulses across boards illustrate coordination for qubit control. [PITH_FULL_IMAGE:figures/full_fig_p010_9.png]
Figure 10
Figure 10. Figure 10: FIG. 10: Overlay of square pulses from two different board [PITH_FULL_IMAGE:figures/full_fig_p010_10.png]
Figure 11
Figure 11. Figure 11: FIG. 11: Phase-aligned 4.5 GHz Gaussian pulses from both [PITH_FULL_IMAGE:figures/full_fig_p010_11.png]
Figure 12
Figure 12. Figure 12: FIG. 12: Results for the simultaneous execution of resonator flux dependence experiments on all 10 qubits. Each subplot [PITH_FULL_IMAGE:figures/full_fig_p011_12.png]
Figure 13
Figure 13. Figure 13: FIG. 13: Layout of the 10-qubit processor used in this work. [PITH_FULL_IMAGE:figures/full_fig_p011_13.png]
Figure 14
Figure 14. Figure 14: FIG. 14: CZ interaction chevrons for pairs of qubits q2-q7 (a) and q1-q6 (b). In the z-axis we see the normalized magnitude [PITH_FULL_IMAGE:figures/full_fig_p012_14.png]
Figure 15
Figure 15. Figure 15: FIG. 15: Full experimental setup for the 10-qubit processor. [PITH_FULL_IMAGE:figures/full_fig_p014_15.png]

Discussion (0). Sign in to comment.

Reference graph

Works this paper leans on

14 extracted references · 10 canonical work pages

  1. [5]

    26Yilun Xu, Abhi D Rajagopala, Neelay Fruitwala, and Gang Huang

    Accessed: 2025-07-14. 26Yilun Xu, Abhi D Rajagopala, Neelay Fruitwala, and Gang Huang. Multi- fpga synchronization and data communication for quantum control and measurement. arXiv preprint arXiv:2506.09856,

    arXiv 2025

  2. [6]

    Accessed: 2025-07-14. 28AMD. XM655 RF Analog Front-End Card. https://docs.amd.com/r/ en-US/ug1390-zcu216-eval-bd/XM655/ ,

    work page 2025

  3. [7]

    30Texas Instruments

    Ac- cessed: 2025-07-14. 30Texas Instruments. LMK04828: Ultra-Low Jitter Clock Synthesizer and Jitter Cleaner. https://www.ti.com/product/LMK04828/,

    work page 2025

  4. [8]

    31Xilinx

    Ac- cessed: 2025-07-14. 31Xilinx. PYNQ xrfclk GitHub Repository. https://github.com/ Xilinx/PYNQ/tree/master/sdbuild/packages/xrfclk,

    work page 2025

  5. [9]

    32QICK Developers

    Ac- cessed: 2025-07-14. 32QICK Developers. Qick firmware project: qick_tprocv2_216_standard. https://github.com/openquantumhardware/qick/tree/main/ firmware/projects/qick_tprocv2_216_standard,

    work page 2025

  6. [10]

    Accessed: 2025-07-11. 33AMD. PetaLinux Tools Documentation: Reference Guide (UG1144) . AMD,

    work page 2025

  7. [11]

    34Xilinx

    Accessed: 2025-07-14. 34Xilinx. PYNQ xrfdc GitHub Repository. https://github.com/ Xilinx/PYNQ/tree/master/sdbuild/packages/xrfdc,

    work page 2025

  8. [12]

    35Xilinx

    Ac- cessed: 2025-07-14. 35Xilinx. RFSoC-MTS: Multi-Tile Synchronization examples for Zynq Ul- traScale+ RFSoC. GitHub repository. Accessed: 2025-07-14. 36Stavros Efthymiou, Sergi Ramos-Calderer, Carlos Bravo-Prieto, Adrián Pérez-Salinas, Diego García-Martín, Artur Garcia-Saez, José Ignacio La- torre, and Stefano Carrazza. Qibo: a framework for quantum sim...

    work page 2025

Show all 14 references
  1. [13]

    Qibocal: an open-source framework for calibration of self-hosted quantum devices

    38Andrea Pasquale, Edoardo Pedicillo, Juan Cereijo, Sergi Ramos-Calderer, Alessandro Candido, Gabriele Palazzo, Rodolfo Carobene, Marco Gobbo, Stavros Efthymiou, Yuanzheng Paul Tan, et al. Qibocal: an open-source framework for calibration of self-hosted quantum devices. arXiv ...

    arXiv

  2. [14]

    A quantum engineer’s guide to supercon- ducting qubits

    39Philip Krantz, Morten Kjaergaard, Fei Yan, Terry P Orlando, Simon Gus- tavsson, and William D Oliver. A quantum engineer’s guide to supercon- ducting qubits. Applied physics reviews, 6(2), 2019

    2019

  3. [2013]

    2d transmons with lifetimes and coherence times exceeding 1 millisecond.arXiv preprint arXiv:2503.14798,

    23Matthew P Bland, Faranak Bahrami, Jeronimo GC Martinez, Paal H Prestegaard, Basil M Smitham, Atharv Joshi, Elizabeth Hedrick, Alex Pakpour-Tabrizi, Shashwat Kumar, Apoorv Jindal, et al. 2d transmons with lifetimes and coherence times exceeding 1 millisecond.arXiv preprint ar...

    arXiv

  4. [2021]

    Qubic 2.0: An exten- sible open-source qubit control system capable of mid-circuit measurement and feed-forward

    17Yilun Xu, Gang Huang, Neelay Fruitwala, Abhi Rajagopala, Ravi K Naik, Kasra Nowrouzi, David I Santiago, and Irfan Siddiqi. Qubic 2.0: An exten- sible open-source qubit control system capable of mid-circuit measurement and feed-forward. arXiv preprint arXiv:2309.10333,

    arXiv

  5. [2024]

    21Max Werninghaus, Daniel J Egger, Federico Roy, Shai Machnes, Frank K Wilhelm, and Stefan Filipp

    Accessed: 2025-07-14. 21Max Werninghaus, Daniel J Egger, Federico Roy, Shai Machnes, Frank K Wilhelm, and Stefan Filipp. Leakage reduction in fast superconducting qubit gates via optimal control. npj Quantum Information, 7(1):14,

    2025

  6. [2025]

    Evidence of memory effects in the dynamics of two-level system defect ensembles us- ing broadband, cryogenic transient dielectric spectroscopy

    24Qianxu Wang, Sara Magdalena Gómez, Juan S Salcedo-Gallo, Roy Lei- bovitz, Jake Freeman, Salil Bedkihal, and Mattias Fitzpatrick. Evidence of memory effects in the dynamics of two-level system defect ensembles us- ing broadband, cryogenic transient dielectric spectroscopy. ar...

    arXiv

Pith tools

Reviewed August 6, 2026 · model on record in the stance chip above.