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Qrisp Implementation and Resource Analysis of a T-Count-Optimised Non-Restoring Quantum Square-Root Circuit

T0 review · 3 major / 4 minor · reviewed 2026-08-06 · deepseek-v4-flash

Pith's one-line read The paper reports a complete Qrisp implementation of the T-count-optimised non-restoring quantum square-root circuit and claims it validates the theoretical resource counts, while its own resource table reports the original quadratic…

desk verdict The Qrisp square-root code is real, but the paper's own table contradicts its headline T-count claim, so the paper needs major correction before it can be trusted. read the letter →

arxiv 2507.12603 v1 pith:II7ADYWO submitted 2025-07-16 quant-ph

classification quant-ph PACS 03.67.Lx
keywords quantumsquarerootnon-restoringQrispT-countoptimizationT-depthreversiblearithmeticcircuitimplementationcontrolledaddition
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper reports the first complete implementation, in the Qrisp quantum programming framework, of the T-count-optimised non-restoring integer square-root algorithm from the design it builds on. The circuit is assembled from reusable reversible components — a Peres gate, a ripple-carry adder, controlled add/subtract blocks, and a controlled adder — and mirrors the three stages of the non-restoring method: initial subtraction, iterative conditional addition/subtraction, and remainder restoration. The authors claim this validates the theoretical resource estimates, so that a quantum program can call an integer square-root primitive that returns both root and remainder without garbage output. Their stated headline formula is a T-count of $14n-14$ and a T-depth of $5n+3$ for $n$-bit inputs, although the paper's own resource table lists T-counts matching the quadratic estimate from the original design.

What carries the argument

The load-bearing object is the non-restoring square-root algorithm as a reversible circuit, structured as three stages acting on $2n+1$ qubits: an $n$-qubit remainder register R, an $n$-qubit result register F initialised to 1, and a one-qubit control z. The algorithm decides at each step whether to add or subtract by testing the sign of the current partial remainder; the control qubit z encodes that sign, and a conditioned ADD/SUB block executes either operation. The Peres gate — a Toffoli followed by a CNOT — serves as the primitive for the ripple-carry adder and subtractor, and the controlled adder of the final restoration stage comes from a T-count-optimised multiplier design. Swap operations on F move the running root bits into place, and the concluding two-position shift makes F hold the integer square root.

What would settle it

Run the published Qrisp circuit for random inputs at widths $n=18$, $n=20$, and $n=32$, compare F shifted by two to $\lfloor\sqrt{a}\rfloor$ and R to $a-F^2$, and decompile each run to count T gates; if any tested width gives a wrong root, or if the total T-count follows the table rather than $14n-14$, the strong validation claim collapses.

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Extended reading notes

Core claim

On the paper's own terms, the central discovery is that a resource-optimised theoretical square-root design can be turned into executable, modular Qrisp code rather than remaining a gate-level proposal. The implementation reproduces the non-restoring algorithm's three stages and produces the integer square root in the F register and the remainder in the R register, with a final shift of F by two positions accounting for the algorithm's bit ordering. The abstract and conclusion state the result as a validated T-count of $14n-14$ and a T-depth of $5n+3$ for an $n$-bit input. The validation section, however, reports T-counts that match the quadratic formula $\frac{7}{2}n^2 + 21n - 28$ from the original design, and the measured qubit counts $2n+1$ match the theoretical counts. The operative claim, as presented to a fair reader, is that Qrisp can host the complete garbageless square-root circuit with the same resource profile as the published theoretical design.

Load-bearing premise

The whole construction assumes that the Qrisp register slicing and swap sequence reproduce the original algorithm's bit ordering for every width $n$, so that after the final two-position shift F holds the integer square root and R holds the remainder; the paper directly demonstrates this only for the printed cases $a=6$ through $16$.

Editorial extensions

If this is right

  • A quantum program using Qrisp can now call an integer square-root primitive that returns both root and remainder with no garbage register left behind.
  • The modular decomposition into adders, subtractors, controlled blocks, and the Peres gate gives a template for implementing other arithmetic operations in the same framework.
  • Resource counts can be read directly from the framework's operation counts, letting algorithm designers budget T gates before fault-tolerant hardware exists.
  • The full circuit uses $2n+1$ qubits for an $n$-bit input, matching the theoretical design, so the cost of adding square root to a larger algorithm is predictable.
  • The implementation provides an executable point of comparison for alternative square-root circuits, such as Newton-iteration designs.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Inference: the abstract's linear formula $14n-14$ matches the adder's T-count, not the full square-root circuit; if the table is authoritative, the scalable cost is the original quadratic estimate, which grows much faster with $n$.
  • Inference: the printed functional test output covers only $a=6$ through $16$, although the prose says the output is for $a=80$ through $87$; the full-range correctness claim should be treated as unverified until the supplied test harness is inspected or re-run.
  • Inference: a direct extension would be to run the same Qrisp gate on randomized inputs at $n=18$, $20$, and $32$ and decompile the resulting circuits to count T gates, which would settle which of the two stated T-count formulas the implementation actually follows.
  • Inference: because Qrisp compiles toward concrete gate sets, this square-root block could serve as a drop-in arithmetic oracle for larger quantum algorithms, but its T overhead at practical widths would need to be budgeted against specialised arithmetic libraries.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 4 minor

Summary. The paper presents a Qrisp implementation of the non-restoring quantum square-root circuit originally designed by Muñoz-Coreas and Thapliyal. The authors describe modular building blocks (Peres gates, reversible adders, controlled add/subtract units), give Qrisp code for each stage, report functional tests, and tabulate qubit counts and T-counts for n = 6 through 16. The abstract and conclusion claim that the implementation validates the theoretical resource estimates, specifically a T-count of 14n−14 and a T-depth of 5n+3 for n-bit inputs. The body of the paper, however, states that the T-count remains unchanged from the original quadratic estimate 7/2 n² + 21n − 28, and Table 1 exactly matches that quadratic formula. The T-depth claim is never measured or derived.

Significance. If the resource claims were correct, this would be a valuable demonstration that a high-level quantum programming framework can reproduce a T-count-optimized arithmetic circuit with linear T-count and T-depth. The paper has concrete strengths: the implementation code is made available on GitHub, the circuit construction is described in enough detail to be reproduced, and the reported qubit counts match the theoretical estimates in Table 1. However, the central quantitative claim about T-count is directly contradicted by the paper's own data, and the T-depth claim is unsupported. As it stands, the paper does not establish the advertised resource savings; after correction it could still be a useful implementation case study, but not a validation of the claimed linear resource formulas.

major comments (3)
  1. [Abstract, Section 5, Conclusion, Table 1] The abstract and conclusion state that the implementation confirms a T-count of 14n−14 for n-bit inputs, but Table 1 reports T-counts of 224, 364, 532, 728, 952, and 1204 for n = 6, 8, 10, 12, 14, 16. These values exactly match the quadratic formula 7/2 n² + 21n − 28, not 14n−14, which would give 70, 98, 126, 154, 182, and 210 respectively. Section 5 also explicitly says that 'in our implementation, the T-count remains unchanged' relative to the original work. The headline resource claim is therefore contradicted by the paper's own empirical data. This is a load-bearing inconsistency and must be resolved by correcting the abstract, conclusion, and any other statements that assert the linear T-count.
  2. [Abstract, Conclusion, Section 5, Table 1] The claimed T-depth of 5n+3 is asserted in the abstract and conclusion but is never computed, measured, or derived anywhere in the manuscript. Table 1 contains no T-depth column, and the validation section reports only qubit counts and T-counts. Since the paper defines T-depth in Section 2.1 and claims to validate the theoretical resource estimates, the absence of any T-depth analysis leaves the T-depth claim entirely unsupported. The authors should either provide a concrete measurement or derivation of the T-depth of the implemented circuit or remove the T-depth claim.
  3. [Section 5] The validation text says that 'output of the tests for numbers from 80 to 87 is shown below,' but the printed output lists a = 6 through 16. These are different input ranges: 80 to 87 would exercise an 8-qubit register, whereas 6 to 16 primarily exercise 4- and 6-qubit registers. The discrepancy is unexplained and affects the claimed coverage of the functional tests. The authors should clarify which inputs were actually run and ensure that the displayed output corresponds to the described test range.
minor comments (4)
  1. [Section 2.7] The Toffoli decomposition in Figure 4b is described as containing four T gates and four T† gates, but the text concludes that the T-count of the Toffoli gate is 7. Depending on whether T† is counted as a T gate, this decomposition gives a T-count of either 8 or 4, not 7. The convention should be stated explicitly and made consistent with the resource counts used throughout the paper.
  2. [Section 4.8] The rule for choosing n is given as 'the smallest even number of qubits sufficient to represent the input number a in binary (with two extra bits if needed to accommodate the algorithm's grouping of bits).' This is imprecise; the authors should state the exact relationship between the input bit-length and n, since the resource counts in Table 1 depend on n.
  3. [Throughout] There are several typographical errors that should be corrected, for example 'Conditinal' in the Section 4.6 heading, 'opearations' at the start of Section 4.3, 'reminder' in Section 4.9, and 'sequencially' in Section 2.8.
  4. [Table 1] Table 1 compares total qubits and T-count but omits T-depth, even though the abstract and conclusion make a T-depth claim. If the authors keep the T-depth claim, the table should include measured or estimated T-depth values, or the claim should be removed.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: the Qrisp implementation is independently compared against external prior work; the T-count inconsistency is an internal error, not a circular reduction.

full rationale

The paper's derivation chain is not circular. The resource counts in Table 1 are computed from the concrete Qrisp circuit (via count_ops) and compared with the theoretical estimates of Muñoz-Coreas and Thapliyal [9], which are external to the present authors. No parameter is fitted to the target result, no prediction is defined in terms of its own outcome, and no load-bearing premise is justified by the authors' own prior work. The only self-reference is the GitHub repository link [6], which is for code availability and does not support any theoretical claim. The abstract and conclusion claim a T-count of 14n-14 and T-depth of 5n+3 for the square-root circuit, but Section 5 and Table 1 report T-counts matching the quadratic formula 7/2 n^2 + 21n - 28 from [9] (e.g., 224 for n=6, 1204 for n=16), and the T-depth 5n+3 is never measured or derived. This is a serious internal consistency and correctness error in the paper's validation claim, but it is not an instance of circular reasoning: the implemented circuit is still an independent artifact, and the contradicted formula is a quoted external estimate rather than an input that was used to construct the circuit. Similarly, the prose says tests covered 80 to 87 while the printed output shows a=6 to 16; that is another reporting inconsistency, not circularity. Because no step reduces to its own inputs, the circularity score is 0.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

The central resource claim rests on gate counts of literature circuits and on the framework's semantics, not on fitted parameters. The mismatch between the abstract's 14n-14 and Table 1's quadratic values is an internal inconsistency rather than an extra axiom.

assumptions (4)
  • standard math Toffoli gate decomposition has T-count 7 and T-depth 3.
    Used in Section 2.7 to compute adder and controlled-adder T-counts; the decomposition is standard and not re-derived in this paper.
  • domain assumption The three-stage non-restoring square root algorithm of Muñoz-Coreas and Thapliyal [9] is correct and garbage-free for even n-bit inputs.
    Section 3 translates the algorithm without re-proving it; Section 5 tests only a few inputs rather than all widths.
  • domain assumption Qrisp's QuantumFloat registers and zcx zero-controlled operations implement the intended reversible arithmetic semantics.
    The circuit's functional correctness (Section 5) depends on the framework's execution model; no formal proof or verified compiler output is provided.
  • domain assumption The adder and controlled-adder designs from [15] and [8] are correct and T-count-optimal as quoted.
    Sections 2.9 and 2.10 adopt circuit designs from cited papers and rely on their gate counts without independent verification.

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Cite this review

Pith. "Pith review of Qrisp Implementation and Resource Analysis of a T-Count-Optimised Non-Restoring Quantum Square-Root Circuit." pith.science (2026). https://pith.science/paper/II7ADYWO

@misc{pith2026250712603,
  author       = {Pith},
  title        = {Pith review of: Qrisp Implementation and Resource Analysis of a T-Count-Optimised Non-Restoring Quantum Square-Root Circuit},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/II7ADYWO}},
  note         = {Machine review of arXiv:2507.12603}
}
read the original abstract

Efficient quantum arithmetic operations are essential building blocks for complex quantum algorithms, yet few theoretical designs have been implemented in practical quantum programming frameworks. This paper presents the first complete implementation of the T-count optimized non-restoring quantum square root algorithm using the Qrisp quantum programming framework. The algorithm, originally proposed by Thapliyal et al., offers better resource efficiency compared to alternative methods, achieving reduced T-count and qubit requirements while avoiding garbage output. Our implementation validates the theoretical resource estimates, confirming a T-count of 14n-14 and T-depth of 5n+3 for n-bit inputs. The modular design approach enabled by Qrisp allows construction from reusable components including reversible adders, subtractors, and conditional logic blocks built from fundamental quantum gates. The three-stage algorithm - comprising initial subtraction, iterative conditional addition/subtraction, and remainder restoration is successfully translated from algorithmic description to executable quantum code. Experimental validation across multiple test cases confirms correctness, with the circuit producing accurate integer square roots and remainders. This work demonstrates the practical realizability of resource-optimized quantum arithmetic algorithms and establishes a foundation for implementing different arithmetic operations in modern quantum programming frameworks.

Figures

Figures reproduced from arXiv: 2507.12603 by the authors.

Figure 1
Figure 1. NOT and CNOT gates [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. b. 𝑇 -count and 𝑇 -cost of the CNOT gate is 0. a × b b × a (a) SWAP gate. a • • b b • a (b) Decomposition of the SWAP gate [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. The Hadamard gate. 2.6 The T and T† Gates The T and T† gates are single qubit gates that are used to control the phase of a qubit. The T gate is a gate that adds a phase of 𝜋 4 to the state and the T† gate is a gate that removes a phase of 𝜋 4 from the state. 2.7 The Toffoli Gate The Toffoli gate is a 3-qubit reversible gate having the mapping for three input qubits (𝑎, 𝑏, 𝑐) to three output qubits (𝑎, 𝑏, 𝑎.𝑏 ⊕ 𝑐) a… view at source ↗
Figures from the paper (5 more)
Figure 4
Figure 4. Figure 4: The Toffoli gate. a • a b a ⊕ b c a · b ⊕ c (a) Peres gate graphical rep￾resentation. a • • a b • a ⊕ b c a · b ⊕ c (b) Peres gate decomposition [PITH_FULL_IMAGE:figures/full_fig_p004_4.png]
Figure 5
Figure 5. Figure 5: The Peres gate. 2.9 Addition and Subtraction Circuits The quantum square root algorithm described in the next section also requires T-count optimized addition and subtraction circuits. The addition circuit used in the current implementation follows the idea from [15]. …
Figure 6
Figure 6. Figure 6: Example 4-bit addition circuit. gate is used instead). Otherwise, apply the Peres gate to the qubits 𝑏𝑖 , 𝑎𝑖 and 𝑏𝑖+1 such that 𝑏𝑖 , 𝑎𝑖 and 𝑏𝑖+1 are passed to the inputs 𝑎, 𝑏, 𝑐 of the Peres gate respectively. (5) For i=1 to n-2: Apply the CNOT gate to the qubits 𝑏𝑖 an…
Figure 7
Figure 7. Figure 7: Example of 4-bit subtraction circuit. 2.10 Controlled Addition Circuit Another arithmetical operation required by the algorithm is T-Count optimized controlled addition. The implemented version of the controlled addition circuit is theoretically described in [8]. Unlik…
Figure 8
Figure 8. Figure 8: Example 4-bit controlled addition circuit. [PITH_FULL_IMAGE:figures/full_fig_p006_8.png]

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Reference graph

Works this paper leans on

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