VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs

Alexander Garcia; Kimia Tasnia; Sazadur Rahman; Tasnuva Farheen

REVIEW 4 major objections 6 minor 2 cited by

VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs

T0 review · 4 major / 6 minor · reviewed 2026-08-06 · deepseek-v4-flash

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Pith's one-line read VeriOpt claims that structuring an LLM as planner, programmer, reviewer, and evaluator, with synthesis-report feedback, yields functionally correct Verilog that improves on baseline LLM output by up to 88% in power, 76% in area, and 73%…

desk verdict VeriOpt gets the functional numbers right on RTLLM (25/29), but never re-verifies the PPA-optimized designs, so the 'without sacrificing functional correctness' claim is unsubstantiated until that check is done. read the letter →

arxiv 2507.14776 v1 pith:EIENHNEJ submitted 2025-07-20 cs.SE

Kimia Tasnia , Alexander Garcia , Tasnuva Farheen , Sazadur Rahman This is my paper

classification cs.SE

keywords VerilogRTLgenerationPPAoptimizationmulti-roleLLMpromptingin-contextlearningfunctionalcorrectnessRTLLMbenchmarkhardwaredesignautomation

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper proposes VeriOpt, a prompt-only workflow that makes a general-purpose LLM generate synthesizable Verilog with competitive power, performance, and area (PPA) metrics. Instead of fine-tuning on HDL data, it splits generation into four roles—Planner, Programmer, Reviewer, Evaluator—that mimic a human design team, then feeds synthesis reports and PPA optimization tactics such as clock gating, pipelining, resource sharing, and FSM encoding back into the prompt loop. On the RTLLM benchmark of 29 designs, the authors report 25 functionally correct outputs and PPA improvements over their own baseline of up to 88% in power, 76% in area, and 73% in timing, as measured with an industry-standard synthesis tool. The central claim is that this closes the gap between functional correctness and design quality without expensive retraining.

What carries the argument

Two coupled mechanisms carry the argument: multi-role prompting, which decomposes RTL generation into Planner, Programmer, Reviewer, and Evaluator steps with explicit commented traceability and error-log feedback; and PPA-aware in-context learning, which primes the LLM with VLSI optimization techniques, estimation equations, and the base design's synthesis report so it can reason about power, timing, and area trade-offs at the RT level. The synthesis report is the key sensory input: it turns an opaque code-generation task into a feedback loop where the LLM can quantify the effect of its transformations.

What would settle it

Re-run every VeriOpt-optimized design from Table III against the RTLLM golden testbenches (or an equivalent self-checking testbench) and compare the pass rate with the 25/29 reported for the pre-optimization multi-role output. If the optimized designs fail substantially more often, the claim that PPA optimization comes 'without sacrificing functional correctness' is false.

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Extended reading notes

Core claim

VeriOpt's central claim is that domain-specific optimization knowledge can be injected into an LLM purely through structured prompting and in-context learning, with no fine-tuning, so that generated RTL is both functionally correct and PPA-competitive. Functionally, the multi-role loop—planner outlines implementation steps, programmer writes code with comments marking each step, reviewer checks step coverage, evaluator analyzes testbench error logs and suggests fixes—achieves 25 out of 29 passes on the RTLLM benchmark. For quality, the same LLM is then given the correct baseline code, its synthesis report (dynamic and leakage power, cell and design area, critical path length and slack), and a curated set of RT-level optimization techniques; it produces power-, timing-, or area-optimized variants, with reported maximum improvements of 88% dynamic-power reduction, 76% area saving, and 73% critical-path-length reduction. The paper presents this as evidence that structured LLM workflows can meet industrial PPA expectations while preserving functional correctness.

Load-bearing premise

The paper assumes the PPA-optimized designs still satisfy the functional tests, but it only reports testbench results for the initial multi-role output; the optimized designs' functional correctness is not shown to have been re-verified.

Editorial extensions

If this is right

Design teams could obtain functionally correct RTL plus PPA-optimized variants from a stock LLM, without collecting HDL fine-tuning datasets.
The commented step-by-step workflow gives designers a traceable audit trail for where and why the LLM changed the code, easing debug and trust.
On the RTLLM benchmark, the method's 25/29 functional pass rate would exceed the listed baselines (GPT-4: 15/29, RTLLM Self-Planning: 19/29).
The reported PPA gains—up to 88% power, 76% area, and 73% timing—suggest that prompt-level optimization heuristics can recover a large part of the quality gap between naive LLM output and hand-optimized RTL.
Because the framework already produces separate power-, timing-, and area-optimized versions, the same prompt infrastructure could be pointed at different optimization targets per design constraint.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

A natural next experiment the paper does not report: re-run the optimized designs against the RTLLM testbenches; if they pass, the 'without sacrificing functional correctness' claim is directly supported, and if not, the PPA numbers describe a different, possibly unusable, design variant.
The synthesis-report feedback loop suggests a fully automated closed loop: if the LLM were given tool access to iterate on its own synthesis results, the manual step of feeding reports back could disappear—an extension the authors flag as a limitation.
The per-design percentage improvements are relative to the unoptimized multi-role baseline, not to a hand-optimized industrial golden design, so absolute PPA quality against a professional reference remains untested.
The same role-based prompting plus PPA context may transfer to other HDLs or FPGA flows, but that transfer is speculative since all experiments use Verilog and ASIC-style synthesis.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Colleague,

The paper you'd want to know about: VeriOpt is a prompt-only framework that claims to get an LLM to generate both functionally correct and PPA-optimized Verilog on the RTLLM benchmark. The functional half is genuinely good — 25/29 with GPT-4o, outperforming the baselines they list — and the PPA improvements (up to 88% power, 76% area, 73% timing) are eye-catching if they hold up. But they don't hold up as stated because the optimized designs in Table III are never re-run against the golden testbenches. The paper only reports functional correctness for the pre-optimization multi-role output (Table II). The PPA-optimized designs are the ones that carry the headline numbers, and the transformations VeriOpt recommends — pipelining, clock gating, operand isolation, FSM re-encoding, replacing a ripple adder with a CLA — routinely change cycle-level behavior. So the abstract's 'without sacrificing functional correctness' is unsupported for exactly the designs that matter. The paper's own limitation section admits the LLM lacks real-time synthesis access and that improvements must be externally verified, but that verification is about PPA reports, not functional simulation. This is a load-bearing gap, not a cosmetic one.

What's actually new: the multi-role prompting is a variant of existing work (they cite RTLLM Self-Planning, RTLsquad, VerilogCoder), but the PPA-aware in-context learning — feeding the synthesis report of the baseline plus VLSI optimization documents into the prompt, and having the LLM suggest and apply techniques — is a reasonable recipe that I don't think appears this explicitly in prior work. The case study on the 16-bit adder is clear and instructive. The functional results are solid and would be worth publishing on their own.

The softer spots are real but secondary: single pass, no variance; the PPA baseline is self-referential (VeriOpt-optimized vs. VeriOpt's own unoptimized baseline, not external RTL); no artifacts released. If the authors add a functional re-verification column for Table III and report per-design pass/fail, the central claim would become testable. Without it, the PPA numbers are suggestive but not evidence of correctness.

Who should read this: hardware design-automation people and LLM-for-EDA researchers interested in prompt-only RTL workflows. It's a useful recipe, not a new paradigm.

Recommendation: send it to peer review, but require the authors to re-run functional verification on the optimized designs before acceptance. The functional half alone merits a serious referee.

Referee Report

4 major / 6 minor

Summary. The manuscript proposes VeriOpt, a prompt-only framework that uses multi-role LLM prompting (Planner, Programmer, Reviewer, Evaluator) for functional Verilog generation and PPA-aware in-context learning for power, performance, and area optimization. The framework is evaluated on the RTLLM benchmark of 29 designs, reporting a 25/29 functional pass rate and improvements of up to 88% in power, 76% in area, and 73% in timing relative to baseline LLM-generated RTL. The paper argues that VeriOpt produces functionally correct, synthesizable, PPA-competitive Verilog without fine-tuning, validated with Icarus Verilog and Synopsys Design Compiler.

Significance. If the claims hold, VeriOpt would be a practical, no-fine-tuning alternative for LLM-based RTL generation that addresses both correctness and quality, with transparent intermediate steps and falsifiable PPA numbers. The paper has genuine strengths: it uses the standard RTLLM benchmark, reports per-design results in Table II and Table III, compares against several prior methods, and grounds its optimization suggestions in well-known RT-level techniques. The main weakness is that the central claim about functional correctness after PPA optimization is not supported by the reported experiments: only the pre-optimization multi-role output appears to have been run against the golden testbenches. This is a load-bearing gap, but it is fixable within the manuscript's scope by re-running verification on the optimized designs.

major comments (4)

[IV-C and Table III] The optimized RTL whose PPA gains are reported in Table III is never re-run against the RTLLM golden testbenches. Section IV-B's 25/29 pass rate is explicitly scoped to the multi-role baseline output, and Section V-C concedes that all optimizations must be verified externally with Design Compiler. This matters because the transformations VeriOpt recommends, including pipelining, FSM re-encoding, clock gating, operand isolation, and replacing ripple adders with carry-lookahead adders, can change cycle-level behavior and internal state semantics. The abstract's claim that VeriOpt achieves PPA-efficient code generation 'without sacrificing functional correctness' therefore rests on an unverified assumption. Please re-run functional verification on every optimized design, report pass/fail per design, and either revise the headline claim or restrict it to the subset of designs for which equivalence was confirmed.
[IV-C and Table III] The PPA improvement percentages are computed relative to VeriOpt's own multi-role baseline, with no external PPA baseline synthesized under the same conditions. Since the baseline is produced by the same framework, the reported improvements could partly reflect a weak starting point rather than a general capability to produce PPA-efficient RTL. Please add at least one independent baseline (for example, direct GPT-4 output, RTLCoder output, or Thakur et al. output) synthesized under identical settings, or report absolute PPA numbers for all designs so that final design quality can be assessed directly.
[IV-A3] The experimental setup omits critical synthesis details: the technology library, process corner, clock frequency and constraints, Design Compiler version, and synthesis optimization effort are not reported. These choices materially affect power, area, and timing measurements, and their absence prevents reproduction and cross-paper comparison. Please include a complete synthesis configuration in the paper or in a reproducibility appendix.
[IV-B and IV-C] All functional and PPA results appear to be single runs with GPT-4o. Because LLM outputs are stochastic and the prompt-optimization loop includes free-form generation, the headline numbers (25/29, 88%, 76%, 73%) carry no variance or confidence information. Please report results over multiple independent runs, with means and standard deviations at least for the main functional success rate and the main PPA improvement claims.

minor comments (6)

[II-C] The sentence 'hardware codes contributes on 0.3% of the dataset' should read 'hardware code contributes about 0.3% of the dataset'; the grammar and preposition should be corrected.
[IV-A3] There is a typo in 'thre-of-the-art': it should be 'state-of-the-art'.
[Author affiliation] The affiliation 'Lousiana State University' should be spelled 'Louisiana State University'.
[Fig. 7] Figure 7 lacks axis labels, units, and a definition of what each plotted point represents; please clarify how the trade-off curves were constructed.
[IV-C] The explanation for the right shifter's -50% critical-path-slack change mentions a 'marginal primary slack of -0.02'; since the baseline slack is negative, the percentage-change convention should be defined explicitly.
[IV-B] Table II states that syntactically failed cases are marked '-', and the text claims that VeriOpt generates 100% syntactically correct codes; please state explicitly whether any VeriOpt row required syntax repair before functional evaluation.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: VeriOpt's functional and PPA claims are empirical measurements against external testbenches and an EDA synthesis tool, with no fitted parameter or prediction that reduces to its inputs.

full rationale

VeriOpt makes no first-principles derivation that could reduce to its own inputs. Functional correctness is evaluated externally by running generated RTL against RTLLM's golden testbenches (Section IV-B, Table II), and PPA is measured from Synopsys Design Compiler synthesis reports (Section IV-A3, Table III). The optimization step feeds the baseline synthesis report and textbook PPA techniques into the prompt, but the resulting improvements are empirical EDA synthesis outputs, not quantities defined by the prompt. The baseline for PPA comparison is the authors' own multi-role pipeline rather than an independent external baseline, which limits the strength of the 'improvement' claim, but that is a comparison-design limitation, not circularity. The paper does not re-run the RTLLM testbenches on the PPA-optimized RTL, so the abstract's 'without sacrificing functional correctness' is unsubstantiated for the optimized designs; this is a correctness and rigor gap, not a circular reduction. The only overlapping-author citation ([6], supporting a GitHub code-distribution statistic) is motivational and not load-bearing for any central result. No fitted parameter, self-referential equation, or imported uniqueness theorem appears anywhere in the claimed derivation chain.

Assumptions & free parameters 0 free parameters · 3 assumptions · 0 invented entities

No fitted numeric parameters appear; the framework is prompt-based. The main load-bearing assumptions are about tool accuracy, golden testbenches, and functional preservation after optimization.

assumptions (3)

domain assumption Synthesis reports from Synopsys Design Compiler provide accurate PPA metrics for the generated RTL.
Used in Section III-B2 S3 to give LLM feedback; no technology library, constraints, or tool version are reported, so the numbers cannot be independently checked.
domain assumption The RTLLM benchmark's testbenches are golden and sufficient to establish functional correctness.
Section IV-A2 defines functional pass as meeting all RTLLM testbench cases; no additional formal verification or property checks are used.
ad hoc to paper Optimized RTL produced by the LLM remains functionally equivalent after PPA transformations.
Section IV-C and Table III report PPA gains but do not state any functional re-test of the optimized code; the abstract asserts correctness is not sacrificed.

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Cite this review

Pith. "Pith review of VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs." pith.science (2026). https://pith.science/paper/EIENHNEJ

@misc{pith2026250714776,
  author       = {Pith},
  title        = {Pith review of: VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/EIENHNEJ}},
  note         = {Machine review of arXiv:2507.14776}
}

read the original abstract

The rapid adoption of large language models(LLMs) in hardware design has primarily focused on generating functionally correct Verilog code, overlooking critical Power Performance-Area(PPA) metrics essential for industrial-grade designs. To bridge this gap, we propose VeriOpt, a novel framework that leverages role-based prompting and PPA-aware optimization to enable LLMs to produce high-quality, synthesizable Verilog. VeriOpt structures LLM interactions into specialized roles (e.g., Planner, Programmer, Reviewer, Evaluator) to emulate human design workflows, while integrating PPA constraints directly into the prompting pipeline. By combining multi-modal feedback (e.g., synthesis reports, timing diagrams) with PPA aware prompting, VeriOpt achieves PPA-efficient code generation without sacrificing functional correctness. Experimental results demonstrate up to 88% reduction in power, 76% reduction in area and 73% improvement in timing closure compared to baseline LLM-generated RTL, validated using industry standard EDA tools. At the same time achieves 86% success rate in functionality evaluation. Our work advances the state-of-the-art AI-driven hardware design by addressing the critical gap between correctness and quality, paving the way for reliable LLM adoption in production workflows.

Figures

Figures reproduced from arXiv: 2507.14776 by the authors.

**Figure 2.** Challenges and limitations of current work. (a) Code distribution in [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗

**Figure 3.** Overview of VeriOpt LLM-based HDL coding flow with multi-role (green) and contextual PPA-aware prompting (purple). frequency, the entire product launch can be delayed or forced to operate at suboptimal speeds [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗

Figures from the paper (4 more)

**Figure 4.** Figure 4: Multi role based LLM’s (Planner, Programmer, Reviewer, Evaluator) flow diagram to develop a functionally correct Verilog code. [PITH_FULL_IMAGE:figures/full_fig_p004_4.png]

**Figure 5.** Figure 5: In-context learning for PPA optimization by [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]

**Figure 6.** Figure 6: VeriOpt generated PPA optimized designs. (a) A functionally correct but PPA un-optimized baseline design developed by multi-role LLM from Sec. III-A, (b) VeriOpt analyzes the design structure, synthesis report and suggests PPA optimization techniques, (c) timing, (d) p…

**Figure 7.** Figure 7: Overall improvement in circuit performance considering PPA trade [PITH_FULL_IMAGE:figures/full_fig_p008_7.png]

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Forward citations

Cited by 2 Pith papers

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A Progressive Approach to Synthesizable RTL Design Generation Using LLMs
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VeriRefine boosts LLM-generated RTL correctness to 94.0% on RTLLM v2.0 and 98.1% on VerilogEval-Human v2 by refining and auditing a per-signal intermediate representation before code generation.
ECOLogic: Enabling Circular, Obfuscated, and Adaptive Logic via eFPGA-Augmented SoCs
cs.AR 2025-08 reject novelty 4.0 of 10

ECOLogic embeds an eFPGA fabric into an ASIC and uses a weighted ECOScore framework to decide which IP blocks should be reconfigurable, claiming near-ASIC performance with large power and carbon savings.

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Large language model-aware in-context learning for code generation,

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Optimized sequential state encoding methods for finite-state machines in field-programmable gate array implementations,

V . Salauyou and W. Bułatow, “Optimized sequential state encoding methods for finite-state machines in field-programmable gate array implementations,” applied sciences, 2024

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Pith tools

Reviewed August 6, 2026 · model on record in the stance chip above.

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Benchmarking large language models for automated verilog rtl code generation,

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Chipgpt: How far are we from natural language hardware design,

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arXiv 2023

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Rtlcoder: Outperforming gpt-3.5 in design rtl generation with our open-source dataset and lightweight solution,

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K. Tasnia and S. Rahman, “Opl4gpt: An application space exploration of optimal programming language for hardware design by llm,” in Proceedings of the 30th Asia and South Pacific Design Automation Conference , 2025, pp. 981–987

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MEIC: Re-thinking RTL Debug Automation using LLMs

K. Xu, J. Sun, Y . Hu, X. Fang, W. Shan, X. Wang, and Z. Jiang, “Meic: Re-thinking rtl debug automation using llms,” arXiv preprint arXiv:2405.06840 , 2024

work page Pith review arXiv 2024

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Betterv: Controlled verilog generation with discriminative guidance,

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arXiv 2024