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REVIEW 5 major objections 4 minor 38 references

Systolic Array-based Accelerator for Structured State-Space Models

T0 review · 5 major / 4 minor · reviewed 2026-08-06 · deepseek-v4-flash

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Pith's one-line read This paper claims that EpochCore, a systolic-array accelerator built around reconfigurable LIMA-PE processing elements and a diagonal dataflow, runs S4 and Liquid-S4 inference on Long Range Arena workloads roughly 2000x faster than an…

desk verdict A plausible SSM-specialized systolic array with real PE-level novelty, but the headline speedups rest on an underspecified baseline and a single-layer workload; the Mamba support claim contradicts the paper's own Section III.G. read the letter →

arxiv 2507.21394 v3 pith:CWYBFGHU submitted 2025-07-29 cs.LG cs.SYeess.SY

Shiva Raja , Cansu Demirkiran , Aakash Sarkar , Milos Popovic , Ajay Joshi This is my paper
classification cs.LGcs.SYeess.SY
keywords state-spacemodelsS4Liquid-S4systolicarrayhardwareacceleratorprocessingelementdataflowenergyefficiency
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims that a systolic-array accelerator can natively execute structured state-space models (S4 and Liquid-S4) and ordinary dense neural networks on the same hardware, removing the bottleneck that makes these long-context models slow on GPUs and traditional systolic arrays. The proposed design, EpochCore, builds every processing element from a reconfigurable MAC unit that handles fixed and time-varying recurrent integration in a single cycle, and couples it with a dataflow that streams inputs diagonally through the array so the recurrent state update and the output linear layer run in one pass. On Long Range Arena benchmarks the authors report roughly 2000x lower inference latency than an Nvidia A100 GPU for S4 and Liquid-S4 layers, and 250x latency and 45x energy improvements over a traditional systolic-array accelerator. The practical payoff would be that long-sequence state-space models could run on a compact, energy-efficient accelerator rather than a data-center GPU.

What carries the argument

The load-bearing piece is the LIMA-PE processing element with its four MAC modes: Fixed Recurrent Integration (FRI-MAC), Time-Varying Recurrent Integration (TRI-MAC), Banded Weight-Stationary (BWS-MAC), and Traditional Output-Stationary (TOS-MAC). FRI-MAC computes $x \leftarrow A \cdot x + B \cdot u(t)$ in a single cycle, TRI-MAC adds the input-dependent coefficient for Liquid-S4, and the multiplexer network lets any PE be reconfigured in place. ProDF then wires the dataflow by adding a northeast-to-southwest diagonal movement, so a single row of PEs handles the scalar-vector product and the recurrent update while the remaining rows perform the output matrix multiplication without intermediate writes to SRAM. That unification is what converts the SSM layer from a multi-step, memory-bound operation into one pipelined sweep through the array.

What would settle it

Run the same S4 and Liquid-S4 inference workloads on an Nvidia A100 using the optimized S4 CUDA kernels and measure wall-clock latency; if the real GPU latency is within a small multiple of EpochCore's simulated latency, the claimed 2000x collapses. Independently, recompute the Figure 13 latency breakdown, since the listed values do not obviously yield the claimed drop in the S4 layer's share from 95% to 7%.

Watch

Extended reading notes

Core claim

The paper's central claim is that the recurrent update of a structured state-space model is a first-class systolic-array operation, not an awkward special case. EpochCore's LIMA-PE implements a cardinal MAC of the form $x \leftarrow a \cdot x + b$, with a variant computing $x \leftarrow (a+b)\cdot x + b$ for time-varying coefficients, so each element of the state vector is updated in one cycle inside the array. Combined with the ProDF dataflow, which lets inputs move diagonally while partial results move vertically, the entire S4 or Liquid-S4 layer (input scaling, recurrent integration, and the output linear map) is evaluated in a single sweep through the array. The authors claim this is the first accelerator that executes multiple structured SSMs natively while preserving support for GEMM-based DNN layers, and they report the large speedups on LRA workloads against a GPU and against systolic-array baselines.

Load-bearing premise

The evaluation assumes the GPU and systolic-array baselines are near-optimally implemented and that the custom cycle simulator predicts real hardware behavior for EpochCore and the baselines alike, with the 2000x speedup claim resting on that equivalence.

Editorial extensions

If this is right

  • If the reported numbers hold, S4 and Liquid-S4 layers on LRA-scale sequences stop being the dominant latency contributor, falling from roughly 95% of GPU runtime to about 7% on EpochCore.
  • Because weights stay stationary in the array across an entire batch, EpochCore's on-chip SRAM bandwidth demand is concentrated in the initial weight load, so consecutive inferences reuse the loaded weights almost for free.
  • A single row of LIMA-PEs updates the whole state vector in one cycle per input token, so the per-token latency of the recurrent step does not grow with state-map size $N$.
  • For conventional GEMM layers, EpochCore matches the TPU-style systolic array cycle-for-cycle but pays a 2x area penalty and a 1.3x energy penalty, trading DNN-layer efficiency for SSM-layer efficiency.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The same single-cycle recurrent MAC pattern could be applied to other element-wise recurrences, such as gated recurrent units or diagonal linear RNNs, but the paper does not evaluate those models.
  • A direct way to test the 2000x figure is to run the public optimized S4 CUDA kernels on an A100 and compare measured latency to the paper's simulated EpochCore numbers; the paper does not report that comparison.
  • The diagonal banded-matrix dataflow suggests a general systolic-array template for sparse or structured matrix operations beyond SSMs, although the paper only demonstrates it on S4, Liquid-S4, and GEMM.
  • If the simulated energy numbers carry over to silicon, an EpochCore-like card could shift long-context inference from data-center GPUs to edge devices, but that extrapolation depends on simulator fidelity.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

5 major / 4 minor

Summary. The paper proposes EpochCore, a 2D systolic-array accelerator with a reconfigurable processing element (LIMA-PE) that supports fixed and time-varying recurrent integration, banded-matrix operations, and traditional GEMM dataflows. The authors also introduce ProDF, a programmable dataflow that pipelines scalar-vector multiplication, recurrent integration, and the linear output layer of S4 and Liquid-S4 models in a single array pass. The paper claims roughly 2000x speedup over an A100 GPU for S4/Liquid-S4 inference, 250x latency and 45x energy improvements over a sparse systolic array, and 25x speedup over a 1D FFT-based systolic array. The evaluation combines RTL synthesis of the PE in 45nm with a ScaleSim-based cycle simulator and CACTI-based memory modeling for the full accelerator.

Significance. If the quantitative claims were reliable, the paper would make a useful contribution: a unified systolic-array design that handles both SSM-specific recurrences and conventional DNN layers, with explicit microarchitectural support for complex-valued fixed-point arithmetic and gated-clock power management. The authors do provide concrete RTL-level PE synthesis results, a detailed dataflow mapping, and ablations over state-map size, SRAM capacity, and PE utilization. These are real strengths. However, the headline speedups are not yet established: the GPU baseline is unspecified, the simulator is unvalidated, and at least one presented latency figure is internally inconsistent with the claimed factor. The significance is therefore conditional on a substantially stronger evaluation.

major comments (5)
  1. [Section IV.A and abstract] The 2000x speedup over a GPU is not supported as written because the GPU baseline is never concretely specified. The methodology describes the EpochCore RTL synthesis and ScaleSim/CACTI simulation, but provides no A100 kernel description, no cuDNN/cuFFT settings, no measured wall-clock runtime, and no comparison with the public S4 or Liquid-S4 CUDA implementations. The headline claim is therefore a ratio between EpochCore's simulated cycle count and an unknown GPU number, and it cannot be independently checked or reproduced.
  2. [Section IV.D, Figure 13] The numeric latency labels in Figure 13 are inconsistent with the claimed 2000x improvement. The visible ratio between 174 ms and 1.28 ms is about 136x, not 2000x, and the sentence stating that EpochCore reduces S4 layer latency from approximately 95% to 7% appears to be comparing Sparse-SA with EpochCore rather than establishing the GPU speedup. The figure, its key, and the surrounding text need to be reconciled so that the reported speedup is reproducible from the plotted data.
  3. [Section IV.C and Table III] The 250x and 45x improvements over Sparse-SA are presented without accounting for EpochCore's own costs. Section III.B reports a 2x area increase, 1.3-1.6x power increase, and a 5% reduction in maximum frequency for the fully loaded LIMA-PE, and Section IV.C states a 2x area penalty, 1.3x energy penalty, and 5% latency increase for GEMM operations. A specialized dataflow is expected to beat a generic systolic array on SSM workloads, so the paper should also report area-normalized or throughput-per-area comparisons and show how the headline factors change when these overheads are included.
  4. [Section IV.A, Figures 10 and 13] The evaluation is entirely simulator-derived, but the ScaleSim-based cycle simulator and the custom memory-bandwidth simulator are not validated against real hardware or against published baseline measurements. No error bars, sensitivity analyses, or configuration sweeps are provided for the 2000x, 250x, and 45x factors. Because the quantitative conclusions depend on the simulator's fidelity, the authors should at least include a sensitivity analysis over clock frequency, SRAM bandwidth, batch size, and baseline optimization level.
  5. [Section IV.A and Section IV.D] There is a precision mismatch between EpochCore and the GPU baseline. EpochCore is evaluated with 32-bit fixed-point arithmetic and 16-bit complex fixed-point, while the GPU precision is unspecified and no accuracy comparison is provided. Since the central claim is about performing the same inference task, the paper needs to report whether 32-bit fixed-point achieves accuracy comparable to the floating-point references on the LRA benchmarks, or explicitly state the accuracy loss.
minor comments (4)
  1. [Figure 13] The bars in Figure 13 are not clearly keyed: it is difficult to determine which latency values correspond to the GPU, Sparse-SA, and EpochCore for the S4 versus DNN portions, and the labels are visually ambiguous.
  2. [Section IV.D, Figure 14] The latency numbers in Figure 14 (e.g., 10.5 ms, 4.4 ms, 38.4 ms, 0.37 ms, 0.73 ms, 5.9 ms, 0.0057 ms, 0.0015 ms, 0.0021 ms) are not explained in the caption or text; the reader cannot infer which value corresponds to which accelerator or dataset.
  3. [Abstract and Section VI] The abstract and conclusion state different speedup figures without qualification: the abstract says approximately 2000x over a GPU, while the conclusion says up to 250x over Sparse-SA and only mentions 2000x as a peak, and Table VII lists a 2000x speedup for Liquid-S4. These claims should be stated with the same baseline and the same range so that the reader is not left with contradictory numbers.
  4. [Introduction and Section VI] The introduction states that EpochCore achieves 30x lower memory bandwidth than the 1D FFT-based SA, while the conclusion says memory bandwidth usage is reduced by 3x. These two statements refer to different comparisons or different metrics and should be reconciled.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the claimed speedups are simulation-based comparisons against weakly specified baselines, but no derivation or prediction reduces to its own input by definition.

full rationale

I walked the paper's derivation chain from the S4/Liquid-S4 recurrence equations through the LIMA-PE MAC modes (FRI-MAC, TRI-MAC, BWS-MAC, TOS-MAC) and the ProDF dataflow to the reported speedups. The hardware operations are defined directly from the model equations (Eqs. 3, 5, 10, 11), and the latency claims (e.g., one new output token per cycle after an N+2 cycle fill) follow from the described systolic mapping rather than from a fitted parameter or a self-citation. There are no citations to the authors' own prior work serving as load-bearing evidence, no imported uniqueness theorem, and no attempt to justify a modeling choice by an unverified self-citation. The evaluation does rely on the authors' own ScaleSim-based cycle simulator and an unspecified GPU/TPU baseline, so the absolute 2000x/250x numbers are not independently checkable from the paper alone; however, that is a benchmarking and validation limitation, not a circularity. The statement that traditional WS/OS dataflows 'would require N clock cycles' is an analytical modeling assumption, not a reduction of the result to its own definition. I find no step where a 'prediction' is equivalent to an input by construction, and no self-referential derivation chain. Score 0.

Assumptions & free parameters 4 free parameters · 4 assumptions · 0 invented entities

The central claims rest on the S4/Liquid-S4 recurrences, fixed-point precision assumptions, and simulator fidelity, none of which are independently verified in this paper.

free parameters (4)
  • Systolic array dimensions (64x64) = 64x64
    All latency, PE utilization, and energy results use a 64x64 array; the claims do not show how speedups scale with array size.
  • Operating frequency (700 MHz) = 700 MHz
    Synthesis target for the 45nm PE; all throughput numbers scale with this clock.
  • On-chip SRAM capacities (16 MB input/output, 16 MB weights) = 16 MB
    Chosen to fit LRA workloads; affects feasible batch sizes and memory bandwidth results.
  • Data precision (32-bit fixed-point, 16-bit real/imag complex) = 32-bit / 16-bit
    The paper assumes this precision is sufficient for S4/Liquid-S4 accuracy but provides no accuracy measurement on the hardware.
assumptions (4)
  • domain assumption The S4 and Liquid-S4 discretizations (Eqs. 3 and 5) are the correct updates for the corresponding continuous ODEs as defined in [9] and [12].
    The hardware mapping implements these equations directly; if they are wrong, the accelerator computes the wrong recurrence.
  • domain assumption The diagonalized HiPPO matrix retains model accuracy, as proposed by DSS/S4 [11], [9].
    The diagonal form enables the FRI-MAC operation; non-diagonal SSMs would require a different dataflow.
  • ad hoc to paper Fixed-point arithmetic at 32-bit (real) or 16-bit (complex) is accurate enough for the LRA benchmarks.
    The paper does not report accuracy results from the fixed-point hardware, only the latency/energy.
  • ad hoc to paper The ScaleSim cycle simulator and CACTI memory models provide accurate estimates for the baseline TPU/GPU and EpochCore.
    No validation of the simulator against real silicon is provided.

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Pith. "Pith review of Systolic Array-based Accelerator for Structured State-Space Models." pith.science (2026). https://pith.science/paper/CWYBFGHU

@misc{pith2026250721394,
  author       = {Pith},
  title        = {Pith review of: Systolic Array-based Accelerator for Structured State-Space Models},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/CWYBFGHU}},
  note         = {Machine review of arXiv:2507.21394}
}
read the original abstract

Sequence modeling is crucial for AI to understand temporal data and detect complex time-dependent patterns. While recurrent neural networks (RNNs), convolutional neural networks (CNNs), and Transformers have advanced in capturing long-range dependencies, they struggle with achieving high accuracy with very long sequences due to limited memory retention (fixed context window). State-Space Models (SSMs) leverage exponentially decaying memory enabling lengthy context window and so they process very long data sequences more efficiently than recurrent and Transformer-based models. Unlike traditional neural models like CNNs and RNNs, SSM-based models require solving differential equations through continuous integration, making training and inference both compute- and memory-intensive on conventional CPUs and GPUs. In this paper we introduce a specialized hardware accelerator, EpochCore, for accelerating SSMs. EpochCore is based on systolic arrays (SAs) and is designed to enhance the energy efficiency and throughput of inference of SSM-based models for long-range sequence tasks. Within the SA, we propose a versatile processing element (PE) called LIMA-PE to perform traditional and specialized MAC operations to support traditional DNNs and SSMs. To complement the EpochCore microarchitecture, we propose a novel dataflow, ProDF, which enables highly efficient execution of SSM-based models. By leveraging the LIMA-PE microarchitecture and ProDF, EpochCore achieves on average 2000x improvement in performance on LRA datasets compared to a GPU and 250x gains in performance and 45x improvement in energy efficiency, over traditional SA-based accelerators (TPU).

Figures

Figures reproduced from arXiv: 2507.21394 by the authors.

Figure 1
Figure 1. (Left) GPU (Nvidia A100) latency of SSM models for recurrence vs [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. (a) S4- [11], (b) Liq-S4-based [12] model with input sequences [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 4
Figure 4. (a) Architecture of the full System that uses [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figures from the paper (13 more)
Figure 3
Figure 3. Figure 3: SSM-based models are multi-layered with interleaved SSM and [PITH_FULL_IMAGE:figures/full_fig_p004_3.png]
Figure 5
Figure 5. Figure 5: LIMA-PE Design: (a) Input flow directions. (b) Micro architecture details. (c) Gated clock circuitry for energy efficiency (d) Buffer for stationary and control inputs (e) Mode-specific MAC computation with a buffer for the partial result. for SSM recurrent computation…
Figure 6
Figure 6. Figure 6: Data flow under various MAC operating modes of LIMA-PE. The [PITH_FULL_IMAGE:figures/full_fig_p006_6.png]
Figure 7
Figure 7. Figure 7: (a) Example S4 network with state-map size [PITH_FULL_IMAGE:figures/full_fig_p008_7.png]
Figure 8
Figure 8. Figure 8: (a) S4 recurrence includes addition of linearily scaled input token [PITH_FULL_IMAGE:figures/full_fig_p009_8.png]
Figure 9
Figure 9. Figure 9: The EpochCore can be programmed to compute regular GEMM. An example usage for output-stationary (OS) GEMM data flow within EpochCore is shown. TABLE IV POWER ACROSS LIMA-PE MODES LIMA-PE Mode FixedPoint32 Power (mW) Int8 Power (mW) Sleep 3.8 0.54 Pass-Through 6.7 0.73 …
Figure 12
Figure 12. Figure 12: Energy/Inference for TPU and EpochCore for WS, OS and IS dataflows for various DNN datasets. Boston University Slideshow Title Goes Here 174ms 24ms 23.7ms 1.28ms 1.31ms 0.09ms [PITH_FULL_IMAGE:figures/full_fig_p011_12.png]
Figure 11
Figure 11. Figure 11 [PITH_FULL_IMAGE:figures/full_fig_p011_11.png]
Figure 14
Figure 14. Figure 14: Latency breakdown of inference of Liquid-S4 models for various [PITH_FULL_IMAGE:figures/full_fig_p012_14.png]
Figure 15
Figure 15. Figure 15: Latency/Inference of Liquid-S4 layers on GPU, TPU and [PITH_FULL_IMAGE:figures/full_fig_p012_15.png]
Figure 16
Figure 16. Figure 16: Accuracy of Liquid-S4 model training with different hidden state [PITH_FULL_IMAGE:figures/full_fig_p012_16.png]
Figure 17
Figure 17. Figure 17: The Weight and Input/Output on-chip SRAM access bandwidth is [PITH_FULL_IMAGE:figures/full_fig_p013_17.png]
Figure 18
Figure 18. Figure 18: The Weight and Input/Output SRAM memory sizes for various [PITH_FULL_IMAGE:figures/full_fig_p013_18.png]

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Pith tools

Reviewed August 6, 2026 · model on record in the stance chip above.