REVIEW 4 major objections 7 minor 44 references
SleepWalk: Exploiting Context Switching and Residual Power for Physical Side-Channel Attacks
T0 review · 4 major / 7 minor · reviewed 2026-08-06 · deepseek-v4-flash
Pith's one-line read A sleep call's power spike leaks cryptographic keys, the paper argues, by encoding both register state and residual power from prior computation.
desk verdict The sleep-spike leak observation is plausible and novel, but the AES attack is circular as written and the SIKE attack lacks statistics, so the paper overreaches. read the letter →
The pith
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
The reading
What carries the argument
The central object is the sleep-induced power spike, a single high-amplitude sampling point at the onset of a context switch triggered by the kernel's built-in sleep function (the call chain runs through nanosleep to schedule). The spike's amplitude is modeled as $P_{total} = P_{dyn} + P_{leak} + P_{sc}$, with dynamic power responding to Hamming weight and Hamming distance and leakage power growing with temperature; the thermal model $C_{th} \, dT/dt = P_{total} - (T - T_{amb})/R_{th}$ turns a burst of instruction activity into an elevated die temperature, so the residual signature of past work survives into the spike. This single-point amplitude is the mechanism that removes trace alignment, external triggers, and high-dimensional feature extraction, and it is what both the SIKE threshold classification and the AES byte-level Hamming-weight comparison exploit.
What would settle it
Run the same SIKE and AES key-recovery procedure on a second, unmodified BCM2711 board at a different ambient temperature without re-tuning the SEP_LIMIT threshold; if the separation between the anomalous-zero and normal cases reverses or vanishes, the claimed single-spike monotonicity fails. Separately, attempt to run Algorithm 2 without access to the AES key schedule; since Decrypt(C) requires the full round key, the chosen-plaintext key-recovery attack cannot even begin for an attacker who lacks the key.
Extended reading notes
Core claim
On a stock Raspberry Pi 4 with the Linux kernel's sleep function, the paper discovers that the power spike produced when the kernel enters a context switch contains two superimposed signals: the switching activity of saving and restoring registers (captured by the Hamming weight of register values present at that moment) and the residual power signature of instructions executed before the switch, which persists through elevated die temperature and leakage current. Because the spike is present and prominent for sleep, usleep, and nanosleep, and because its peak amplitude is the only measurement needed, the authors use it for key recovery: with specially crafted SIKE ciphertexts that force zero-valued intermediates in the Montgomery ladder, the spike amplitude cleanly separates cases where the key bit flips from cases where it does not, yielding the full SIKE key with a threshold-based bit-by-bit algorithm; and with 150,000 AES encryptions before each sleep call, the amplitude distinguishes byte-level Hamming weights in the final S-box output, recovering 10 of 16 AES-128 final round key bytes and lowering brute-force complexity from $2^{128}$ to $2^{48}$.
Load-bearing premise
The whole attack treats the average amplitude of the sleep-spike as a stable, monotone measure of register Hamming weight plus residual power and thermal history, and assumes this mapping and the locally tuned SEP_LIMIT threshold transfer across key bits and ciphertexts; if the mapping drifts with temperature, board, or program, the bit classification collapses.
Editorial extensions
If this is right
- An attacker with only a single power sample, taken after a sleep call, can distinguish which of several workloads ran before the sleep, including workloads that differ only in operand size.
- The SIKE key-recovery procedure extracts the full secret key bit by bit even when the sleep call is placed only after the entire decapsulation, using residual power amplified by four decapsulation runs.
- AES final-round key bytes are recoverable at byte granularity: ten of sixteen bytes are found, cutting exhaustive search from $2^{128}$ to $2^{48}$.
- Because usleep, nanosleep, and other user-accessible system calls produce the same spike, the channel generalizes to any kernel context-switch trigger the attacker can invoke.
- No external synchronization is needed because the spike is self-identifying and consistent, so trace collection reduces to peak-finding on a running average.
Reading between the lines
- If the spike amplitude's reliance on residual thermal history is as strong as the model suggests, the calibration (the SEP_LIMIT threshold) should be temperature-dependent: a fixed threshold may fail in a cooler or warmer room, which can be tested by repeating the SIKE attack at different ambient temperatures.
- The AES plaintext generator assumes the attacker can decrypt chosen ciphertexts under the victim key, which is only possible if the attacker already possesses the key schedule or can query the victim as a decryption oracle; a purely black-box chosen-plaintext attacker cannot run Algorithm 2 as written.
- The same single-point leakage could plausibly recover other secret-dependent data that ends in registers or in a sustained computation right before a sleep, such as DNN layer outputs or memory addresses, not just cryptographic keys.
- On other CPUs or kernels, the size and stability of the context-switch spike may differ; if the spike is small or masked by frequency scaling, the method's single-sample advantage would shrink, so cross-platform transfer is an open question.
Signed reviews
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. The paper introduces SleepWalk, a physical power side-channel based on the power spike observed when the Linux sleep() call triggers a context switch on a Raspberry Pi 4 (BCM2711). The authors report that the spike amplitude correlates with the Hamming weight of register contents and with residual power from previously executed instructions, and they develop a qualitative power-thermal model. They then present two end-to-end attacks: full secret-key recovery from the CIRCL SIKE decapsulation, exploiting zero-value states in the Montgomery ladder, and partial (10 out of 16 bytes) final-round key recovery from AES-128 using chosen plaintexts. The claimed advantages are that only a single power-spike amplitude is needed, eliminating trace alignment, external triggers, and complex preprocessing.
Significance. If the end-to-end claims were valid, SleepWalk would be a noteworthy simplification of physical power analysis: a single peak-amplitude measurement could leak both current register state and past computational activity, and the AES result would lower key-search complexity to 2^48. The controlled experiments in Section IV, showing monotone relationships between spike amplitude and register HWT, processed-data HWT/HD, and instruction count, are a plausible empirical contribution, and the anonymous code release and disclosure to Broadcom/ARM are positive practices. However, the AES attack's plaintext generator (Algorithm 2) requires the secret key or an unstated decryption oracle, making the reported key recovery circular in the stated chosen-plaintext model. The SIKE attack's threshold and success claims are also under-supported. As a result, the paper's central security claims are not established.
major comments (4)
- [Section VI, Algorithm 2] The instruction `P <- Decrypt(C)` is load-bearing and circular. In AES, decrypting a 128-bit ciphertext requires the full key schedule; setting a single ciphertext byte `C[T]` to a guessed key byte `k` does not make decryption possible without the secret key. An attacker in the stated chosen-plaintext threat model does not possess that key, and the paper does not state that a decryption oracle is available. If `Decrypt` is instead meant to be called with the victim's key, then the plaintexts that force a 0x00 final-round S-box output are generated using the very key the attack is supposed to recover. Levels 1-3 of the AES attack (Sections VI-A through VI-C) all depend on Algorithm 2, so the reported recovery of 10 key bytes is either circular or rests on an unstated, much stronger assumption.
- [Section V-B, Algorithm 1 and Figures 16-17] The key-recovery procedure hinges on `SEP_LIMIT`, which is "set by conducting multiple local experiments" rather than derived from the leakage model, and on the assumption that the mean peak power for anomalous-zero cases is always lower. The paper reports that the full SIKE key was recovered but gives no success rate, no number of independent trials, no error bars or confidence intervals for the means, and Figure 17 shows only the first ten key bits. The number of decapsulation iterations before sleep (four) is also a free parameter with no sensitivity analysis. These omissions make the full-key recovery claim impossible to verify.
- [Sections IV-A and VI-A] The claimed "single power-spike" / "single sampling point" advantage is not supported by the reported methodology. Every data point in Section IV is the average of 1,000 measured spikes, Section VI-A uses 10,000 traces per plaintext, and Section III-A applies a running-average window of 10 before peak extraction. The end-to-end attacks therefore depend on averaged and smoothed peak amplitudes, not on a single raw sampling point. The paper should either substantiate the single-point claim with single-trace results or soften the claim.
- [Section VI-C] The claim of recovering 10 out of 16 final-round key bytes is not accompanied by per-byte results for all positions, a success criterion, or an analysis of the failures. Figure 20 reports only bytes 15, 13, 3, and 1. Without knowing which bytes fail and why, the stated reduction from 2^128 to 2^48 cannot be assessed, and the reader cannot tell whether the attack is stable across keys.
minor comments (7)
- [Figure 13] The code uses the mnemonic `RSL` for a right shift; the ARM Cortex-A72 ISA has `LSR`, not `RSL`. Please correct or explain the macro.
- [Section IV-D] The text says HD = 4 x SHIFT_VALUE, while the Figure 14 caption says "the HD is always constant (4 x shift amount)"; these statements should be reconciled.
- [Section III-A] "GNU/Linux 12 Debian (Bookworm)" should read "Debian GNU/Linux 12 (Bookworm)".
- [Algorithm 2] The pseudocode overloads `C` for the ciphertext array and `T` for the target byte while `k` is both the loop variable and the key-byte guess; the notation is confusing and should be clarified.
- [Section V-B] The function `generate_ciphertext(K, t)` is never specified; since the zero-value ciphertext construction is central to the attack, the paper should provide pseudocode or a precise pointer to the construction in [44].
- [Section IV-E] The Cold and Hot tasks differ in both shift amount/HWT and instruction count, so the instruction-count effect is not cleanly isolated.
- [Section III-B] The claim that the spike is caused by the context switch rather than by syscall entry/exit or clock events is supported only by a call trace; an ablation that removes schedule() would strengthen the causal claim.
Circularity Check
AES plaintext generation is self-definitional: Algorithm 2's P ← Decrypt(C) requires the full AES key schedule (the target secret) or an unstated decryption oracle, so the chosen-plaintext AES key recovery cannot start as described; the SIKE attack and Section IV spike-correlation experiments are not circular.
-
self definitional
[Section VI-A, Algorithm 2 (Plaintext Generator), line 7: `P ← Decrypt(C)`]
"Ciphertext: C ← Rand() Key byte guess: k for k = 0to 255 do C[T ] ← k P ← Decrypt(C) end for"
Line 7 generates the 'chosen' plaintext by decrypting a ciphertext whose target byte has been set to the key guess k. AES decryption of a full 128-bit block requires the complete inverse key schedule, including the round-10 key byte at position T—the exact value the attack is supposed to recover. The paper describes the attack as a 'chosen plaintext approach' and never declares a decryption oracle, so as written the attacker must already possess the key (or an oracle that performs decryption under it) to run Algorithm 2. That makes the plaintexts that force the 0x00 SubBytes output depend on the target key; Levels 1-3 of the AES attack cannot start without this circular input, and the claimed 10-of-16-byte recovery is not a self-contained chosen-plaintext result.
full rationale
Section III-B and Section IV establish the sleep-induced spike empirically with controlled experiments using Hamming weight, Hamming distance, and instruction count; these are measurements rather than predictions derived from their own inputs, so they are not circular. The SIKE attack (Section V) is a known-ciphertext attack: Algorithm 1 builds ciphertexts from previously recovered key bits and measures two candidate cases; SEP_LIMIT is calibrated in separate local experiments, so it is a fitted threshold rather than a renamed output, and I do not count it as circular, though its robustness is a correctness concern. The only load-bearing circular step is the AES plaintext generator: Algorithm 2 defines P via Decrypt(C), which requires the AES key schedule or an undeclared decryption oracle and thus presupposes the key being recovered. Since AES key recovery is one of the two headline attacks and is the basis for the claimed reduction of key recovery complexity to 2^48, the paper is partially circular. The power-model and SIKE contributions remain independent, so the score is 6 rather than 8.
Assumptions & free parameters
free parameters (4)
- SEP_LIMIT (SIKE key recovery threshold) =
not reported
- running average window (trace smoothing) =
10
- number of decapsulation iterations before sleep (SIKE) =
4
- number of pre-sleep AES encryptions =
150000
assumptions (5)
- standard math CMOS power and thermal equations (Equations 1-3) describe total power as dynamic plus leakage plus short-circuit, with leakage growing with temperature.
- domain assumption The sleep() function leads to schedule() and a context switch on Linux arm64.
- domain assumption Hamming weight and Hamming distance power models apply to the ARM Cortex-A72.
- domain assumption The SIKE zero-value anomaly attack (De Feo et al., reference [44]) applies to the CIRCL implementation used here.
- ad hoc to paper The residual power signature persists long enough to affect a future context-switch spike and scales monotonically with instruction count, data HWT, and HD.
Cite this review
Pith. "Pith review of SleepWalk: Exploiting Context Switching and Residual Power for Physical Side-Channel Attacks." pith.science (2026). https://pith.science/paper/QVT2PJVN
@misc{pith2026250722306,
author = {Pith},
title = {Pith review of: SleepWalk: Exploiting Context Switching and Residual Power for Physical Side-Channel Attacks},
year = {2026},
howpublished = {\url{https://pith.science/paper/QVT2PJVN}},
note = {Machine review of arXiv:2507.22306}
}
read the original abstract
Context switching is utilized by operating systems to change the execution context between application programs. It involves saving and restoring the states of multiple registers and performing a pipeline flush to remove any pre-fetched instructions, leading to a higher instantaneous power consumption compared to typical program execution. In this paper, we introduce a physical power side-channel leakage source that exploits the power spike observed during a context switch, triggered by the inbuilt sleep function of the system kernel. We observed that this power spike directly correlates with both the power consumption during context switching and the residual power consumption of the previously executed program. Notably, the persistence of residual power signatures from previous workloads extends the scope of this side-channel beyond extracting the data in registers during the context switch. Unlike traditional approaches that require analyzing full power traces, applying complex preprocessing, or relying on external synchronization triggers, this novel technique leverages only the amplitude of a single power spike, significantly simplifying the attack. We developed a power model to illustrate the feasibility of mounting end-to-end side-channel attacks using the sleep-induced power spikes. Experimental evaluation demonstrates that our framework can successfully perform cryptographic key recovery for both AES and SIKE implementations on Broadcom BCM2711.
Figures
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