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arxiv: 2508.06236 · v1 · submitted 2025-08-08 · 🪐 quant-ph

Space and Time Cost of Continuous Rotations in Surface Codes

Zhu Sun , Balint Koczor This is my paper

Pith reviewed 2026-05-19 00:26 UTC · model grok-4.3

classification 🪐 quant-ph
keywords surface codescontinuous rotationscatalyst towersspacetime volumefault-tolerant quantum computingphase oracleoption pricing
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The pith

Catalyst towers can reduce both runtime and total spacetime volume for continuous rotations in surface codes at small and medium distances.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper compares methods for implementing continuous rotations in surface-code fault-tolerant quantum computers, where these gates form a major bottleneck. It focuses on catalyst towers, which add ancilla qubits to lower T-count and T-depth, versus standard Clifford plus T synthesis. Explicit surface-code layouts are built for two concrete cases from option pricing: phase oracle circuits and variational state preparation. The central finding is that catalyst towers shorten runtime and can shrink overall spacetime volume at low and medium code distances, while conventional synthesis regains the edge at large distances. This tradeoff matters for early fault-tolerant devices that run many circuit repetitions and must balance space against time.

Core claim

At small and medium code distances, catalyst towers not only reduce the runtime but can also decrease the total spacetime volume of rotations, as shown by explicit layouts for phase oracles and variational circuits; at large distances conventional Clifford plus T synthesis may prove more efficient.

What carries the argument

Catalyst towers, a layout of additional ancilla qubits arranged to implement rotations with reduced T-gate count and depth while fitting into surface-code patches.

If this is right

  • Phase oracle circuits for option pricing incur lower total spacetime cost when rotations use catalyst towers at small and medium distances.
  • Variational state preparation circuits show the same spacetime benefit from catalyst towers under the same distance regime.
  • High-repetition-count algorithms gain a runtime advantage from catalyst towers even when total volume is comparable.
  • At sufficiently large code distances the spacetime advantage reverses in favor of Clifford plus T synthesis.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Early fault-tolerant hardware with modest distances and high circuit repetition rates could adopt catalyst towers to shorten wall-clock time per run.
  • Real devices will require explicit checks for routing overheads that the abstract patch layouts omit.
  • Hybrid schemes mixing catalyst towers for some rotations and standard synthesis for others may emerge as distance grows.

Load-bearing premise

The modeling of space and time costs assumes that the overhead of additional ancilla qubits and the specific surface-code patch layouts for catalyst towers scale exactly as described, without hidden connectivity or routing costs that would appear in a full hardware implementation.

What would settle it

A resource count or circuit simulation at code distance 7 that measures the actual spacetime volume of a full rotation implemented via catalyst towers versus standard synthesis would directly test whether the volume reduction holds.

Figures

Figures reproduced from arXiv: 2508.06236 by Balint Koczor, Zhu Sun.

Figure 1
Figure 1. Figure 1: FIG. 1. An example of a 2-layer in-circuit tower with ‘CT block’ representation on the left and corresponding full circuit on [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2. An example of a 3-layer independent catalyst tower. [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. The layout scheme of the POC with in-circuit towers in surface code. The figure shows two towers and others are [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4. Layout of data qubits for gate synthesis and for the independent tower method, which supports massive parallel gate [PITH_FULL_IMAGE:figures/full_fig_p006_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5. The (a) physical qubit count and (b) spacetime volume of the gate synthesis method, in-circuit tower method and [PITH_FULL_IMAGE:figures/full_fig_p007_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: FIG. 6. A variational [PITH_FULL_IMAGE:figures/full_fig_p008_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: FIG. 7. Physical qubit count of conventional gate synthesis, [PITH_FULL_IMAGE:figures/full_fig_p008_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: FIG. 8. The circuit diagram for the ‘corner’ notation, repro [PITH_FULL_IMAGE:figures/full_fig_p010_8.png] view at source ↗
read the original abstract

While Clifford operations are relatively easy to implement in fault-tolerant quantum computers,continuous rotation gates remain a significant bottleneck in typical quantum algorithms. In this work, we ask the question: "What is the most efficient approach for implementing continuous rotations in a surface code architecture?" Several techniques have been developed to reduce the T-count or T-depth of rotations, such as Hamming weight phasing and catalyst towers. However, these methods often require additional a number of ancilla qubits, and thus the ultimate cost function one needs to optimise against should rather be the total runtime or the total space required for performing a rotation. We explicitly construct surface code layouts for catalyst towers in two practical application examples in the context of option pricing: (a) implementing a phase oracle circuit, which is a ubiquitous subroutine in many quantum algorithms, and (b) state preparation using a variational quantum circuit. Our analysis shows that, at small and medium code distances, catalyst towers not only reduce the runtime but can also decrease the total spacetime volume of rotations. However, at large code distances, conventional Clifford+T synthesis may prove more efficient. Additionally, we note that our conclusions are sensitive to specific application scenarios and the choices of various parameters. Nevertheless, catalyst towers may be particularly advantageous for early fault-tolerant quantum applications, where low and medium code distances are assumed and a spacetime tradeoff is needed to reduce the runtime of individual circuit runs, such as in scenarios involving high circuit repetition counts.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript examines space-time costs of continuous rotations in surface-code fault-tolerant architectures. It compares conventional Clifford+T synthesis against catalyst-tower constructions that trade additional ancilla qubits for reduced T-depth. Explicit surface-code patch layouts are given for two option-pricing subroutines (phase-oracle implementation and variational state preparation). The central claim is that, at small and medium code distances, catalyst towers can simultaneously lower runtime and total spacetime volume, while conventional synthesis becomes preferable at large distances; all conclusions are stated to be parameter-sensitive.

Significance. If the modeling holds, the work supplies concrete, application-level guidance for early fault-tolerant devices operating at modest code distances, where runtime reduction per shot can outweigh modest space overhead. The provision of explicit patch constructions and the explicit comparison of spacetime volume (rather than T-count alone) are positive features that make the trade-off analysis directly usable by circuit designers.

major comments (2)
  1. [§4] §4 (or equivalent section presenting the catalyst-tower layouts and volume formulas): the spacetime-volume comparison assumes that the ancilla overhead and inter-patch routing costs for the catalyst towers scale exactly as drawn in the surface-code patches, without additional stabilizer-measurement or connectivity overhead that would appear once the layout is embedded in a physical lattice. Because the claimed volume reduction at medium distance is load-bearing on this scaling, an explicit accounting (or bound) for routing and measurement overhead is required to substantiate the crossover point.
  2. [volume comparison figure/table] Table or figure reporting volume versus distance (e.g., the comparison plots): the error bars or sensitivity analysis on the ancilla-qubit count and patch-layout assumptions are not visible in the provided derivations; without them the statement that catalyst towers “can also decrease the total spacetime volume” at medium distance remains plausible but not yet quantitatively robust.
minor comments (2)
  1. [Abstract] The abstract states “a number of ancilla qubits”; rephrasing to “an additional number of ancilla qubits” would improve precision.
  2. [cost-model section] Notation for spacetime volume (e.g., whether it is measured in logical-qubit–time steps or physical-qubit–time steps) should be stated once at the beginning of the cost-model section and used consistently.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for their careful reading of the manuscript and for the constructive comments, which help clarify the assumptions underlying our spacetime-volume analysis. We address each major comment below.

read point-by-point responses

  1. Referee: [§4] §4 (or equivalent section presenting the catalyst-tower layouts and volume formulas): the spacetime-volume comparison assumes that the ancilla overhead and inter-patch routing costs for the catalyst towers scale exactly as drawn in the surface-code patches, without additional stabilizer-measurement or connectivity overhead that would appear once the layout is embedded in a physical lattice. Because the claimed volume reduction at medium distance is load-bearing on this scaling, an explicit accounting (or bound) for routing and measurement overhead is required to substantiate the crossover point.

    Authors: We agree that a more explicit discussion of embedding overhead is warranted. The layouts in §4 are given at the logical-patch level, with each patch sized according to the standard surface-code scaling (∼d² physical qubits) and inter-patch operations implemented via lattice surgery whose spacetime cost is already folded into the per-patch volume. Stabilizer measurements remain local to each patch and do not introduce additional long-range connectivity beyond the patch boundaries. Nevertheless, to strengthen the claim, we will revise the manuscript to include a short paragraph that states these assumptions explicitly and supplies a conservative upper bound (e.g., ≤25 % additional volume) on any residual routing overhead, showing that the reported crossover distance remains inside the medium-distance regime for the parameter sets considered. revision: yes

  2. Referee: [volume comparison figure/table] Table or figure reporting volume versus distance (e.g., the comparison plots): the error bars or sensitivity analysis on the ancilla-qubit count and patch-layout assumptions are not visible in the provided derivations; without them the statement that catalyst towers “can also decrease the total spacetime volume” at medium distance remains plausible but not yet quantitatively robust.

    Authors: We concur that quantitative robustness would benefit from explicit sensitivity information. In the revised manuscript we will augment the volume-versus-distance plots with error bars (or shaded bands) that reflect the range of ancilla counts and layout efficiencies arising from the concrete option-pricing circuits examined. These bands will be derived directly from the parameter choices already stated in the text, thereby making the region of spacetime-volume advantage at medium distances quantitatively visible. revision: yes

Circularity Check

0 steps flagged

No circularity: explicit constructions and standard cost models yield independent comparisons

full rationale

The paper derives its spacetime volume claims from explicit surface-code patch layouts and runtime calculations for catalyst towers in phase-oracle and variational state-preparation circuits, benchmarked against conventional Clifford+T synthesis using standard surface-code overhead models. No equations reduce a claimed advantage to a fitted parameter defined by the same data, and no load-bearing step relies on a self-citation chain or uniqueness theorem imported from the authors' prior work. The analysis is self-contained against external benchmarks such as T-count reductions and distance-dependent scaling, with parameter sensitivity explicitly noted rather than hidden by construction.

Axiom & Free-Parameter Ledger

2 free parameters · 1 axioms · 0 invented entities

The central claim rests on standard surface-code error-correction assumptions and on the modeling choice that ancilla overhead and T-gate costs dominate the spacetime volume; no new physical entities are introduced.

free parameters (2)
  • code distance
    The crossover between catalyst-tower and conventional advantages is stated to depend on the chosen code distance.
  • number of ancilla qubits in towers
    The space overhead of catalyst towers is a tunable parameter that affects the spacetime volume calculation.
axioms (1)
  • domain assumption Surface-code patches can be arranged with the connectivity and routing overhead assumed in the catalyst-tower layouts.
    Invoked when constructing the explicit layouts for the phase-oracle and variational circuits.

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Reference graph

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