Piano: A Multi-Constraint Pin Assignment-Aware Floorplanner

Feng Wu; Jie Wang; Kexin Zhou; Mingxuan Yuan; Shixiong Kai; Siyuan Xu; Zhexuan Xu; Zijie Geng

REVIEW 4 major objections 5 minor 17 references

Piano: A Multi-Constraint Pin Assignment-Aware Floorplanner

T0 review · 4 major / 5 minor · reviewed 2026-08-06 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗

Pith's one-line read Piano is a floorplanning framework that simultaneously optimizes module placement and pin assignment under fixed-outline, whitespace-removal, and pre-placed-module constraints, using a graph-based shortest-path approach to assign pins…

desk verdict Piano is a genuine step in co-optimizing floorplanning and pin assignment with fair relative comparisons, but its headline feedthrough and unplaced-pin reductions rest on a two-pin star decomposition whose physical meaning is unvalidated. read the letter →

arxiv 2508.13161 v1 pith:6YJ3O7TA submitted 2025-07-20 cs.AR cs.AI

Zhexuan Xu , Kexin Zhou , Jie Wang , Zijie Geng , Siyuan Xu , Shixiong Kai , Mingxuan Yuan , Feng Wu This is my paper

classification cs.ARcs.AI

keywords pinassignmentfloorplanningfeedthroughwhitespaceremovalpre-placedmodulesHPWLVLSIphysicaldesigngraph-basedoptimization

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper claims that pin assignment should be co-optimized with module placement during floorplanning rather than treated as an afterthought, and presents Piano, a framework that does both under fixed-outline, whitespace-removal, and pre-placed-module constraints. Piano builds a graph whose edge weights are the available pin-to-pin connection resources between adjacent modules, then routes each net along shortest paths through this graph, which simultaneously decides pin positions and detects feedthrough paths. The same graph machinery produces three layout-quality metrics — feedthrough wirelength, number of feedthrough modules, and unplaced pins — that guide a simulated-annealing refinement stage with three local operators and a whitespace-removal step. On MCNC and GSRC benchmarks, Piano reports an average 6.81% reduction in half-perimeter wirelength, a 13.39% decrease in feedthrough wirelength, a 16.36% reduction in feedthrough modules, and a 21.21% drop in unplaced pins, all at zero whitespace. A sympathetic reader would care because these are the metrics that determine whether a floorplan can actually be wired and timed in later physical-design stages.

What carries the argument

The central object is the resource graph $G_{\text{Res}}$, whose nodes are modules and whose edge weight between adjacent modules $M_i$ and $M_j$ is the pin-to-pin connection resource $\text{P2PRes}(M_i,M_j)=\lfloor \text{AvailEdge}_{ij}/u \rfloor$, the maximum number of pins that fit on their shared boundary given the pin spacing $u$. From it, Piano builds a mask graph with Euclidean center distances as edge weights, runs A* to find a shortest path for each net, and then chooses concrete pin locations along that path by beam search; whenever no path exists the net is counted as an unplaced pin. The same resource graph ties placement and pin assignment together, because the edges that carry feedthrough paths also indicate where adding boundary length or swapping modules would improve routability.

What would settle it

Run Piano on a real or synthetic netlist containing nets with multiple input pins (for instance a cell with several fan-in pins), keeping those nets intact rather than star-decomposing them, then route the final floorplan with a standard detailed router. If the declared feedthrough wirelength and unplaced-pin reductions do not translate into comparable post-routing wirelength or congestion improvements—or if the metrics change materially when the multi-input nets are handled differently—then the claimed gains are an artifact of the decomposition rather than the layout quality itself.

Watch

Extended reading notes

Core claim

On its own terms, the central discovery is that the pin-assignment problem can be solved as a shortest-path problem on a graph whose edges are the pin-capacity resources between adjacent module boundaries, and that the resulting paths are exactly the feedthrough routes a later router would need. Piano's contribution is to use this graph both as an evaluator—computing feedthrough wirelength, feedthrough module count, and unplaced pins—and as a guide for layout refinement, so that module placement and pin assignment are improved together rather than separately. The paper reports that on the MCNC and GSRC benchmarks this co-optimization, followed by whitespace removal and a simulated-annealing stage with three local operators, outperforms placement-only baselines across all five metrics, with zero whitespace in the final layouts.

Load-bearing premise

The netlist reorganization assumes every net has at most one input pin, so multi-pin nets are decomposed into a star of two-pin nets sharing that single input; if real nets have several inputs or timing-critical multi-fanout structures, the feedthrough and unplaced-pin counts may no longer describe the actual signal flow.

Editorial extensions

If this is right

A floorplan can be scored for routability at floorplanning time: feedthrough wirelength, feedthrough module count, and unplaced pins give a layout-level prediction of wire congestion and unroutable nets before detailed routing.
Piano works as an incremental optimizer: fed any legal layout it brings the same feedthrough and unplaced-pin reductions, so existing floorplanners can adopt it without replacing their placement engine.
Pre-placed modules occupying up to 30% of chip area can be respected while still reaching zero whitespace and fully assigned pins.
Zero-whitespace layouts do not have to degrade pin placement: the P2PRes enhancement operator creates extra boundary length exactly where nets need it, which is why unplaced pins drop by about a fifth.
The runtime cost stays close to the fastest baselines (for example, 1.51 seconds on the n10 design versus TOFU's 1.35 seconds), so the extra metrics do not require orders-of-magnitude more compute.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

If the graph-based resource view were applied during global placement rather than only at the floorplanning stage, the same shortest-path machinery could serve as a congestion-aware placement objective, potentially avoiding feedthrough hotspots before they form.
The star-like net decomposition limits the current results to single-input multi-fanout nets; extending the graph to multi-input Steiner routing would be a direct test of whether the feedthrough and unplaced-pin gains survive on real multi-input netlists.
Replacing the Euclidean-distance feedthrough estimate with pin-to-pin path lengths once internal module placements are known would let the same framework serve as a post-placement refinement pass, converting its floorplan-level predictions into exact wiring estimates.
The three operators (random exchange, adjacent exchange, and P2PRes enhancement) are generic enough that they could be dropped into any simulated-annealing-based physical design tool, not just floorplanning, wherever boundary pin capacity matters.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Short version: this paper is the first floorplanner I know to optimize placement and pin assignment together under fixed-outline, whitespace, and pre-placed-module constraints. The graph-based pin assignment with A* pathfinding and beam search for pin positions is a real new combination, and the authors run the same pin-assignment routine on top of all baseline layouts before comparing. That makes the relative comparisons fair, and the HPWL numbers are externally meaningful. HPWL improves in seven of eight benchmarks, and the incremental-optimization experiment starting from Corblivar's layouts shows practical value.

What is soft: the paper reports only means over five runs, no error bars or spreads. TOFU's layouts were obtained directly from the authors rather than reproduced, so one baseline is not independently verifiable. The bigger problem is Section IV-B2's netlist reorganization. Every multi-pin net is decomposed into a star of two-pin nets under the assumption that each net has at most one input pin. Real multi-pin nets are routed as Steiner trees, with branches sharing feedthrough segments, so the paper's FTlen, FTnum, and Unplacepin measure a different object than physical feedthrough as a router would see it. Since the simulated annealing objective directly optimizes these metrics, the reported gains in them are partly self-referential. The same decomposition is applied to all baselines, so the relative claims hold within the model, but the physical reductions are not established. A Steiner-tree rerouting test, or at least a sensitivity analysis varying the decomposition, would settle this.

One smaller absence: AVR and module regularity are treated as hyperparameters and not reported, so it is hard to tell whether zero-whitespace is achieved by distorting module shapes.

Bottom line: the paper supplies a missing capability — evaluating pin feasibility inside the floorplanning loop — and the mechanism is coherent. It is not ready as is: it needs error bars, code or layout release, and an honest treatment of the star-decomposition limitation. Those are addressable, so this deserves a serious referee rather than a desk reject.

Referee Report

4 major / 5 minor

Summary. The manuscript introduces Piano, a three-stage floorplanning framework that co-optimizes module placement and pin assignment under fixed-outline, whitespace-removal, and pre-placed-module constraints. Stage 1 legalizes a given or random layout through wiremask and position-mask construction; Stage 2 builds a graph of pin-capacity resources (P2PRes), assigns pins via A* and beam search, and computes feedthrough-length, feedthrough-module-count, and unplaced-pin metrics; Stage 3 removes whitespace and runs simulated annealing with three local operators. On eight MCNC/GSRC benchmarks the authors report average reductions of 6.81% (abstract; 6.84% in Section V-B) in HPWL, 13.39% in feedthrough wirelength, 16.36% in feedthrough module count, and 21.21% in unplaced pins relative to Corblivar, TOFU, and Wiremask-EA, while maintaining zero whitespace. An additional experiment evaluates Piano as an incremental optimizer on Corblivar outputs and gives a qualitative PPM-constraint refinement.

Significance. If the reported results are accepted, Piano is a useful contribution to floorplanning practice: it addresses pin assignment jointly with placement under realistic constraints, and the graph-based formulation with P2PRes, A* path search, and beam-search pin assignment is nontrivial. The authors take reasonable fairness steps: the same pin-assignment routine is applied to all baselines, and whitespace removal is applied to Corblivar and Wiremask-EA before comparison. HPWL is an externally defined metric, so the reported HPWL improvements are meaningful evidence of placement quality. However, the three feedthrough and unplaced-pin metrics are defined on a reorganized netlist and are exactly the quantities optimized by the SA objective, so the significance of those gains depends on validation against downstream routing or an independent multi-pin routing model. The current evidence is not yet sufficient in that respect.

major comments (4)

[Section IV-B2, Eq. (4)] The netlist-reorganization step decomposes every multi-pin net into a star of two-pin subnets under the condition that 'each net Ni has at most one input pin.' For standard digital netlists a net normally has one driver and multiple receivers, so the condition should at minimum be restated as 'at most one driver' and verified for the MCNC/GSRC benchmarks. If any net has multiple drivers, the star decomposition is undefined, and the FTlen/FTnum/Unplacepin values computed from Equation (4) are not physically meaningful. Since these three metrics account for a large part of the headline improvements (13.39%, 16.36%, 21.21%), this assumption is load-bearing. Please report driver/fanout statistics for the benchmark netlists and validate the feedthrough metrics on the original multi-pin nets, for example by comparing with a standard Steiner-tree routing model; until then, the reported percentages should be described as improvements on the star-decomposed netlist rather than on actual feedthrough or unplaced pins.
[Table I, Section V-A] All numerical results are reported as means over five runs, with no standard deviation, min/max, or per-run values. Several HPWL differences are small (for example, n10 Piano at 34435 versus TOFU at 35213 is about 2%, and n30 Piano at 109938 is actually worse than TOFU at 109189), so the aggregate average percentage gains could be within run-to-run noise. Add variance information or a significance test to support the claimed average reductions.
[Section V-A, Table I] The TOFU results were obtained directly from the authors and are not reproducible from public artifacts, as the paper states. Because the TOFU column is central to the comparison against state-of-the-art methods, the manuscript should either make the TOFU layout files (or an equivalent script) available, or clearly mark the TOFU comparison as based on author-provided data and soften the 'SOTA' claim accordingly. Without this, readers cannot independently verify the comparison.
[Section V-C, Figure 6] The pre-placed-module capability is demonstrated only by a qualitative example, with no quantitative metrics for HPWL, FTlen, FTnum, or Unplacepin under the PPM constraint. Since handling PPMs is one of the stated modern constraints, the claim is not yet supported. Add a quantitative evaluation of the PPM scenario, or explicitly limit the claim to a visual demonstration.

minor comments (5)

[Abstract vs Section V-B] The abstract reports an average HPWL reduction of 6.81% while Section V-B states 6.84%; please reconcile and specify exactly which baselines and averaging procedure produce this number.
[Section III-B, Eq. (3)] The symbol u is used for PinSpace in Eq. (3) without a prior definition; define u when it is introduced, or use the name PinSpace consistently.
[Section IV-C, Algorithm 1] In the pseudocode, the running average for FTlen in line 21 reuses the variable name FTlen for both the accumulator and the final metric; rename the accumulator to avoid confusion.
[Section V-A] The claim of zero whitespace is not accompanied by any measured whitespace-area ratio in Table I or elsewhere; please add the measured whitespace ratio for each method and benchmark.
[Introduction] There are minor typographical issues, e.g., 'pi n a ssignment-aware' and 'multi modern constraints'; these should be corrected.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: Piano's reported gains are direct optimization outcomes, and no prediction or first-principles claim reduces to its inputs.

full rationale

The paper's claimed contribution is a heuristic floorplanning and pin-assignment pipeline, not a predictive or first-principles derivation. The feedthrough metrics FTlen and FTnum defined in Equation (4) and the Unplacepin counter in Algorithm 1 are exactly the quantities that the simulated-annealing objective minimizes with weight ratio 1:50:2000:100, so the reported improvements in those metrics are expected consequences of optimizing the stated objective rather than circular reductions; the same metric definitions are applied uniformly to all baselines. The Section IV-B2 star decomposition of multi-pin nets is a modeling assumption that affects how feedthrough is measured, and it is a legitimate validity limitation, but it does not make any reported quantity equivalent by construction to the method's inputs. The self-citations (TOFU [4], JigsawPlanner [3], FTAFP [12]) are used only to motivate constraints and position related work; none is invoked as a load-bearing theorem or to forbid alternative approaches. HPWL, an externally standard metric not defined by Piano, improves in seven of eight benchmarks, providing independent evidence that the method is not merely reporting its own objective. Therefore no specific circular step can be exhibited.

Assumptions & free parameters 7 free parameters · 4 assumptions · 1 invented entities

The framework rests on several hand-set hyperparameters (PinSpace, SA weights, beam width, thresholds) and on domain simplifications about netlist topology and feedthrough length. None of these are fitted to data in a way that would force the headline numbers, but they are the reason the reported metrics are not directly comparable to routed wirelength.

free parameters (7)

PinSpace = ratio of average module perimeter to average nets per module
Defines P2PRes capacity in Eq. 3; chosen heuristically in Section V-A and directly controls feedthrough and unplaced-pin counts.
SA objective weights = 1:50:2000:100 for HPWL:FTlen:FTnum:Unplacepin
Set in Section V-A without sensitivity analysis; used in the annealing objective that drives the optimization.
AVR threshold = 5%
Limits area variation rate in Eq. 2; hand-set per design.
Max edge segments per module = 20
Limits jagged edges from Operator 3; set in Section V-A.
Beam search width k = 5
Balances physical feedthrough path search quality and runtime; hand-set.
SA cooling schedule = Tinit=100, Tend=0.01, cooling rate 0.9
Standard SA parameters selected in Section V-A.
Grid size = 224x224
Resolution for wiremask and position-mask; chosen as a model setting.

assumptions (4)

domain assumption Each net has at most one input pin, so multi-pin nets decompose into a star of two-pin nets from a single source.
Invoked in Section IV-B2; if real netlists contain multiple input pins or complex timing-critical fanout, the reorganized netlist misrepresents signal flow.
domain assumption Connected whitespace regions can be modeled as blank modules for pin assignment.
Introduced in Section IV-B2; assumes treating whitespace as a module with boundaries yields accurate pin capacity and feedthrough estimation.
domain assumption Euclidean distance between module centers approximates feedthrough length in expectation.
Stated in Section IV-C after Eq. 4; actual detour length depends on internal component placement, which is unknown at floorplanning time.
ad hoc to paper The P2PRes formula floor(AvailEdge/PinSpace) is a valid model of pin capacity on an adjacent edge.
Defined in Eq. 3; it is the paper's own capacity model and is not validated against electrical or routing constraints.

invented entities (1)

Blank module representing each connected whitespace region
purpose: Allows pins to be assigned on boundaries between whitespace and real modules, and enables feedthrough paths to traverse whitespace areas.
Introduced in Section IV-B2 as a modeling device; no external validation showing this accurately resembles routing over whitespace.

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Cite this review

Pith. "Pith review of Piano: A Multi-Constraint Pin Assignment-Aware Floorplanner." pith.science (2026). https://pith.science/paper/6YJ3O7TA

@misc{pith2026250813161,
  author       = {Pith},
  title        = {Pith review of: Piano: A Multi-Constraint Pin Assignment-Aware Floorplanner},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/6YJ3O7TA}},
  note         = {Machine review of arXiv:2508.13161}
}

read the original abstract

Floorplanning is a critical step in VLSI physical design, increasingly complicated by modern constraints such as fixed-outline requirements, whitespace removal, and the presence of pre-placed modules. In addition, the assignment of pins on module boundaries significantly impacts the performance of subsequent stages, including detailed placement and routing. However, traditional floorplanners often overlook pin assignment with modern constraints during the floorplanning stage. In this work, we introduce Piano, a floorplanning framework that simultaneously optimizes module placement and pin assignment under multiple constraints. Specifically, we construct a graph based on the geometric relationships among modules and their netlist connections, then iteratively search for shortest paths to determine pin assignments. This graph-based method also enables accurate evaluation of feedthrough and unplaced pins, thereby guiding overall layout quality. To further improve the design, we adopt a whitespace removal strategy and employ three local optimizers to enhance layout metrics under multi-constraint scenarios. Experimental results on widely used benchmark circuits demonstrate that Piano achieves an average 6.81% reduction in HPWL, a 13.39% decrease in feedthrough wirelength, a 16.36% reduction in the number of feedthrough modules, and a 21.21% drop in unplaced pins, while maintaining zero whitespace.

Figures

Figures reproduced from arXiv: 2508.13161 by the authors.

**Figure 2.** Framework of Piano. Piano consists of three stages. The first stage performs legalization with global optimization. The second stage conducts pin assignment and feedthrough path detection. The third stage applies a whitespace removal method and three operators to perform local optimization. M3 M1 M2 M3 (a) Position-mask (a) Position-mask 2 16 1 1 1 1 1 1 1 1 1 2 2 2 2 2 8 9 10 10 10 10 11 8 8 8 9 9 0 10 12 12 12 9 1… view at source ↗

**Figure 3.** Visualization of Position-mask and Wiremask. The position-mask identifies the legal grid, while the wiremask determines the HPWL increment when placing the module at each grid location. 2) Netlist Reorganization: Second, to accurately compute feedthrough, we reorganize the netlist by decomposing nets with three or more connections (e.g., Ni = {MI , MO1 , MO2 , . . .}) into multiple two-module nets based on their I… view at source ↗

Figures from the paper (3 more)

**Figure 4.** Figure 4: Visualization of Graph Construction and Pin Assignment. (a) shows the initial GRes, while (b) and (c) illustrate GRes and the corresponding floorplan during the routing of net N = {M1, M5}. Algorithm 1 Graph Construction 1: Input: Legal Canvas C, Reorganized Netlist N …

**Figure 5.** Figure 5: Floorplan of GSRC n50 design. 5a displays the results of Corblivar after processing with our whitespace removal algorithm. 5c and 5d illustrate the feedthrough paths in the layout results by Piano. optimizer using the layout generated by Corblivar as the initial soluti…

**Figure 6.** Figure 6: PPMs Constraint Refinement. (a) shows the initial solution generated by Corblivar, while (b) presents the incremental optimization under PPMs constraint performed by Piano. The PPMs are marked in grey. C. PPMs Constraint Refinement In this subsection, we demonstrate P…

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Reference graph

Works this paper leans on

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Pith tools

Reviewed August 6, 2026 · model on record in the stance chip above.

[1] [1]

Floorplanning with pin assignment,

M. P. M. M.-S. Emest and S. Kuh, “Floorplanning with pin assignment,”

work page

[2] [2]

Fixed-outline floorplanning: enabling hierarchi- cal design,

S. Adya and I. Markov, “Fixed-outline floorplanning: enabling hierarchi- cal design,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 6, pp. 1120–1135, 2003

work page 2003

[3] [3]

Jigsawplanner: Jigsaw-like floorplanner for eliminating whitespace and overlap among complex rectilinear modules,

X. Du, R. Zhong, S. Kai, Z. Tang, S. Xu, J. Hao, M. Yuan, and J. Yan, “Jigsawplanner: Jigsaw-like floorplanner for eliminating whitespace and overlap among complex rectilinear modules,” in 2024 IEEE/ACM International Conference on Computer Aided Design (ICCAD) , pp. 1–9, ACM, 2024

work page 2024

[4] [4]

Tofu: A two-step floorplan refinement framework for whitespace reduc- tion,

S. Kai, C.-W. Pui, F. Wang, S. Jiang, B. Wang, Y . Huang, and J. Hao, “Tofu: A two-step floorplan refinement framework for whitespace reduc- tion,” in 2023 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 1–5, 2023

work page 2023

[5] [5]

Modern floorplanning based on b/sup */-tree and fast simulated annealing,

T.-C. Chen and Y .-W. Chang, “Modern floorplanning based on b/sup */-tree and fast simulated annealing,” IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, vol. 25, no. 4, pp. 637– 650, 2006

work page 2006

[6] [6]

Vlsi module placement based on rectangle-packing by the sequence-pair,

H. Murata, K. Fujiyoshi, S. Nakatake, and Y . Kajitani, “Vlsi module placement based on rectangle-packing by the sequence-pair,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 12, pp. 1518–1524, 1996

work page 1996

[7] [7]

Corner block list: an effective and efficient topological representation of non-slicing floorplan,

X. Hong, G. Huang, Y . Cai, J. Gu, S. Dong, C.-K. Cheng, and J. Gu, “Corner block list: an effective and efficient topological representation of non-slicing floorplan,” in IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140), pp. 8–12, 2000

work page 2000

[8] [8]

eplace: Electrostatics-based placement using fast fourier transform and nesterov’s method,

J. Lu, P. Chen, C.-C. Chang, L. Sha, D. J.-H. Huang, C.-C. Teng, and C.-K. Cheng, “eplace: Electrostatics-based placement using fast fourier transform and nesterov’s method,” ACM Trans. Des. Autom. Electron. Syst., vol. 20, Mar. 2015

work page 2015