A 28nm 1.80Mb/mm2 Digital/Analog Hybrid SRAM-CIM Macro Using 2D-Weighted Capacitor Array for Complex Number Mac Operations

Arijit Raychowdhury; Che-Kai Liu; Samuel Spetalnick; Shota Konno; Sigang Ryu

A 28nm 1.80Mb/mm2 Digital/Analog Hybrid SRAM-CIM Macro Using 2D-Weighted Capacitor Array for Complex Number Mac Operations

T0 review · 3 major / 3 minor · reviewed 2026-08-05 · deepseek-v4-flash

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Pith's one-line read Complex-number MAC in SRAM: 1.80 Mb/mm2, 0.435% RMS error

desk verdict A plausible hybrid SRAM-CIM complex-MAC macro with a genuinely new capacitor-array topology and promising silicon numbers, but the abstract alone doesn't let anyone verify the headline accuracy claim. read the letter →

arxiv 2508.17562 v1 pith:NTLGOMLP submitted 2025-08-25 cs.AR

Shota Konno , Che-Kai Liu , Sigang Ryu , Samuel Spetalnick , Arijit Raychowdhury This is my paper · ORCID

classification cs.AR

keywords compute-in-memorySRAMcomplex-numberMACanalogcompute2D-weightedcapacitorarrayhybriddigital-analog28nmmacroedgeAI

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper claims a new way to make a memory chip that also performs complex-number multiply-accumulate (MAC) operations, by splitting the computation into two parts: digital circuits handle the upper (more significant) bits, and analog circuits built around a 2D-weighted capacitor array handle the lower bits. This removes the need for input digital-to-analog converters, which the authors say improves accuracy and lowers area overhead. The prototype macro in 28nm 6T-SRAM is reported to achieve 1.80 Mb/mm2 memory density and 0.435% RMS error, and it outputs the real and imaginary parts of each complex MAC in a single conversion step, reducing latency. A sympathetic reader would care because this is a concrete path to running complex-number workloads inside memory with near-digital accuracy and high density, which matter for on-device neural networks.

What carries the argument

The key mechanism is the 2D-weighted capacitor array, a capacitor network with weights varying in two dimensions that performs multi-bit analog multiply-accumulate on the lower bits of the inputs. It carries the analog half of the hybrid computation, and its compact layout is what allows the macro to dispense with input DACs—the upper bits are processed by the digital CIM path, the lower bits by this array, and the two results are combined. The array is also what enables the single-conversion output of the real and imaginary parts of a complex MAC.

What would settle it

Take a fabricated version of the macro and run complex MACs at several supply voltages and temperatures while sweeping input magnitudes; if RMS error exceeds 0.435% under nominal conditions or varies widely between chips, the accuracy claim as stated is not reproducible. Alternatively, compare against a fully digital complex MAC on identical data; the hybrid must stay within its claimed error bound to support the DAC-free accuracy advantage.

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Extended reading notes

Core claim

The central discovery claimed is that a hybrid digital/analog compute-in-memory design can avoid input DACs while keeping error low, by confining digital CIM to the upper bits and analog CIM to the lower bits. The 2D-weighted capacitor array is the enabler: it allows the analog path to handle the less significant bits directly from a 6T-SRAM array without conversion. On a 28nm prototype, the authors report 1.80 Mb/mm2 memory density and 0.435% RMS error for complex-number MAC operations, with both real and imaginary outputs available after a single conversion.

Load-bearing premise

The 0.435% RMS error assumes the 2D-weighted capacitor array maintains sufficient matching and tolerable parasitics across the operating conditions of the 28nm process; the abstract gives a single error number without supply voltage, temperature, input range, or chip count.

Editorial extensions

If this is right

Complex-number MAC operations run inside a 6T-SRAM array, so weights do not need to be moved out of memory to be multiplied.
Eliminating input DACs reduces the area overhead of analog CIM, contributing to the reported 1.80 Mb/mm2 density.
Outputting real and imaginary parts in one conversion lowers latency relative to designs that need separate conversions for each part.
The reported 0.435% RMS error suggests the hybrid path can approach digital accuracy, making it usable for inference workloads.
The digital/analog bit-split shows a design choice for balancing precision and density that could scale to other bit partitions.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

If the error stays near 0.435% across supply and temperature, this macro could serve as a compact building block for complex-valued neural networks in radio-frequency or beamforming applications, where complex arithmetic is native.
The hybrid bit-split suggests a generalizable rule: spend digital resources only where precision matters, and let analog handle the rest; the same principle might extend to other analog compute primitives beyond capacitor arrays.
A natural next test would be measuring how RMS error scales with the number of lower analog bits, input magnitudes, and array size; that would reveal where the analog path's matching limits begin.
If the density claim is compared against a fully digital CIM with the same MAC throughput, the hybrid approach could show an area advantage proportional to the number of upper bits kept digital.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

You should know this paper before the other CIM work you're tracking: it reports a 28nm 6T-SRAM compute-in-memory macro for complex-number MACs, and the hook is a 2D-weighted capacitor array that lets the design split MAC work into digital upper bits and analog lower bits without input DACs. That split, plus a single conversion that outputs both real and imaginary parts, is a real circuit contribution as far as I can tell from the abstract. The reported 1.80 Mb/mm2 density and 0.435% RMS error are the kind of numbers that make this worth a second look.

What the paper does well: the hybrid digital/analog scheme is a sensible way to trade accuracy against area, and the 2D-weighted capacitor array appears to be a new twist, not a restatement of prior hybrid CIM. Avoiding input DACs is also a legitimate area saver for complex MACs, which usually need heavy peripheral circuitry. If the measurement data holds up, this is a useful datapoint for baseband and edge AI accelerators.

The soft spots are real but mostly about the abstract, not necessarily the work. The 0.435% RMS error is load-bearing and the abstract gives no operating envelope: no bit split, no accumulation length, no supply/temperature corners, no chip count, no definition of what the error is normalized to. The stress-test note is right that this makes the claim unverifiable from the abstract. But that's an abstract-length problem, not evidence the paper is wrong. The same goes for the DAC-free claim: a binary-weighted capacitor array can behave like a charge-scaling DAC, so I'd want the full text to clarify how the input path differs from a conventional DAC. Those are the two questions a referee should push on.

I don't see circular derivation here. The error and density are measured outputs, not fitted predictions. The citation pattern is impossible to judge from an abstract that cites nothing, but that's normal for a conference-style report.

Bottom line: this is a paper for people building SRAM-CIM macros, especially for complex arithmetic. It deserves a serious referee if the full text includes the measurement details that the abstract omits. I'd want the reviewer to check the accuracy metric and the DAC-free claim closely. I wouldn't cite it on the abstract alone, but I'd read the full version and probably bring it to our next CIM reading group.

Recommendation: send it to peer review, with a strong request for measurement conditions and a baseline comparison.

Referee Report

3 major / 3 minor

Summary. This abstract-only submission reports a 28nm 6T-SRAM compute-in-memory (CIM) macro for complex-number MAC operations. The proposal is a hybrid digital/analog architecture in which digital CIM handles the upper bits and analog CIM handles the lower bits via a 2D-weighted capacitor array, with no separate input DACs. The abstract claims a measured memory density of 1.80 Mb/mm2 and 0.435% RMS error, and states that the complex CIM unit produces real and imaginary outputs in a single conversion. Because the full text was not supplied, this report evaluates only what the abstract itself supports.

Significance. If the full paper supports the headline numbers with proper measurement conditions, this would be a competitive density figure for 28nm CIM and the hybrid upper-digital/lower-analog split is an interesting area-accuracy trade-off. The single-conversion generation of real and imaginary parts is a useful latency feature. The abstract is plausible but not verifiable: the 0.435% RMS error has no defined operating envelope, the density metric is unspecified, and the 'without input DACs' claim is ambiguous. The result is potentially significant, but the abstract alone does not establish it.

major comments (3)

[Abstract] The central accuracy claim, '0.435% RMS error,' is not defined. The abstract does not state the normalization full-scale range, input bit width and the digital/analog bit split, the number of accumulated MAC terms, supply voltage and temperature corners, number of measured chips, or any comparison against a digital or full-analog baseline. Because this number is load-bearing for the paper's value proposition, the abstract makes it unfalsifiable. The full text must supply this measurement envelope before the claim can be assessed.
[Abstract] The density claim '1.80 Mb/mm2' is ambiguous. It is not clear whether this is bit-cell array density, macro-level density including peripherals, or another basis. CIM density claims are only meaningful when the area definition is specified; otherwise the headline figure cannot be checked against prior art.
[Abstract] The phrase 'without the need for input DACs' is ambiguous. A binary-weighted capacitor array that is charged or discharged based on input bits effectively performs charge-scaling DAC conversion. If the design uses the array itself as the DAC, the abstract should state that explicitly; as written, it invites the inference that no DAC-like function exists anywhere in the input path.

minor comments (3)

[Abstract] The line-break hyphen in 'num-ber' should be removed; the word should be 'number'.
[Abstract] The notation 'Digital(D)/Analog(A)' should be formatted as 'Digital/Analog' or with appropriate spacing for readability.
[Abstract] The abstract does not mention energy, throughput, or accuracy-versus-energy trade-offs, which would strengthen the comparison with other CIM macros.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity found in abstract-only review

full rationale

The manuscript is available only as an abstract. The abstract reports measured outcomes (1.80 Mb/mm2 density, 0.435% RMS error) and describes a design choice (hybrid digital/analog CIM with a 2D-weighted capacitor array). No derivation chain appears in the abstract, and no fitted parameter is renamed as a prediction. The accuracy figure is presented as a measurement result, not as an output of a model that was itself fit to that measurement. The hybrid bit-split is a design decision, not derived from the error number. There are no equations, no self-citations, and no uniqueness claims in the abstract. Concerns about the unstated operating envelope of the RMS error are correctness/verifiability issues, not circularity. Therefore the appropriate finding is no significant circularity, score 0.

Assumptions & free parameters 0 free parameters · 1 assumptions · 0 invented entities

The macro's measured claims rest on process-dependent analog behavior (capacitor matching, noise) that the abstract does not quantify. No free parameters are evident: density and RMS error are presented as measured outputs, not fitted values. No invented entities are introduced beyond the physical 2D-weighted capacitor array topology.

assumptions (1)

domain assumption Capacitor matching and analog noise in the 28nm process stay within the tolerances the design assumed.
The 0.435% RMS error and the DAC-free analog lower-bit path depend on matching and noise in the 2D-weighted capacitor array; the abstract gives no corner, temperature, or process data.

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Cite this review

Pith. "Pith review of A 28nm 1.80Mb/mm2 Digital/Analog Hybrid SRAM-CIM Macro Using 2D-Weighted Capacitor Array for Complex Number Mac Operations." pith.science (2026). https://pith.science/paper/NTLGOMLP

@misc{pith2026250817562,
  author       = {Pith},
  title        = {Pith review of: A 28nm 1.80Mb/mm2 Digital/Analog Hybrid SRAM-CIM Macro Using 2D-Weighted Capacitor Array for Complex Number Mac Operations},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/NTLGOMLP}},
  note         = {Machine review of arXiv:2508.17562}
}

read the original abstract

A 28nm dense 6T-SRAM Digital(D)/Analog(A) Hybrid compute-in-memory (CIM) macro supporting complex num-ber MAC operation is presented. By introducing a 2D-weighted Capacitor Array, a hybrid configuration is adopted where digital CIM is applied only to the upper bits and ana-log CIM is applied to the rest, without the need for input DACs resulting in improved accuracy and lower area overhead. The CIM prototype macro achieves 1.80 Mb/mm2 memory density and 0.435% RMS error. Complex CIM unit outputs real and imaginary part with a single conversion to reduce latency.

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Reviewed August 5, 2026 · model on record in the stance chip above.