REVIEW 4 major objections 5 minor 12 references
Electrical impedance tomography is demonstrated for the first time with a microfluidic chamber etched directly into a CMOS chip's wiring layers, imaging glass microspheres in 225 picoliters of water.
Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →
First demonstration of electrical impedance tomography with a fully integrated on-chip picoliter microfluidic chamber and 16-electrode array in 65 nm CMOS, validated against optical micrographs of glass microspheres.
T0 review reviewed 2026-08-05 challenge →
load-bearing objection A credible first-of-kind integration demo that would be much stronger with a water-only baseline and full EIDORS disclosure. the 4 major comments →
Electrical Impedance Tomography with an Integrated Picoliter-Volume Subtractive Microfluidic Chamber in 65 nm CMOS
The pith
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
The reading
Core claim
The paper asserts the first EIT system whose microfluidic chamber and electronics are fabricated together in one CMOS die. The chamber, roughly 150 µm by 150 µm in lateral extent and about 10 µm deep (≈225 pL), is created by alternating wet etches — Al Etch Type A for copper/aluminum and an EDTA/H2O2 mix for Ta/TaN or Ti/TiN barriers — that hollow out the interconnect metal while leaving inter-metal dielectrics as the chamber walls. A 16-electrode array spans the chamber floor at 66% fill factor, with electrodes also on several metal layers below; on-chip multiplexers reconfigure the electrodes as stimulator, ground, sense output, or floating, and a LO derived from the digital clock drives s
What carries the argument
Subtractive fabrication in the CMOS interconnect stack: alternating wet etches remove chosen copper/aluminum and barrier metals so that inter-metal dielectrics remain as chamber walls, channels, and exposed electrode surfaces, with no added fluidic layer. The electrical engine is a 16-electrode array connected through digitally reconfigurable multiplexers to on-chip stimulation and readout circuits, and the imaging engine is off-chip EIT reconstruction that converts boundary-voltage measurements into a conductivity map.
Load-bearing premise
The conductivity maps are only meaningful if the voltages at the 16 electrodes are actually set by the water-and-sphere conductivity distribution under the usual Laplace-equation forward model; the paper reports no electrode-interface impedance measurements, no empty-chamber baseline, and no error metric, so if etch damage, bubbles, or electrode-to-electrode variability — rather than the glass spheres — drive the voltage pattern, the 'low conductivity' patches could be artifa
What would settle it
Repeat the exact same measurement with the chamber filled only with water and no microspheres. If the same reconstruction software returns localized low-conductivity patches similar to those in Fig. 6, the correlation is an inverse-solver artifact rather than tomography. A second decisive check is to measure the impedance of each electrode in isolation: if the per-electrode spread predicts where low-conductivity regions appear, electrode non-uniformity — not the sample — is what is being imaged.
If this is right
- Single-chip fluidics-and-electronics: the subtractive route builds the sample container from the foundry's own interconnect layers, so no bonding, plastic, or silicon fluidic parts are needed.
- Picoliter-scale sample confinement: at ~225 pL the integrated chamber holds volumes an order of magnitude smaller than typical miniature EIT sensors, and the process already demonstrates sub-chambers down to ~20 fL.
- Dense electrode access: because electrodes are defined by the metal stack, 16 electrodes cover 66% of the chamber floor and additional metal layers face the chamber from the sides, naturally suited to arrays.
- Frequency-flexible operation: with the LO running 500 Hz–100 kHz and similar maps at 1 kHz and 100 kHz for the insulating spheres, the platform could support frequency-difference imaging.
- A direct corollary of the claimed first: subsequent integrated EIT designs can now assume the chamber does not have to be external, freeing the packaging to be optimized for the electronics.
Where Pith is reading between the lines
- The correlation in Fig. 6 is qualitative; a quantitative phantom study with known conductivity targets and an error metric would be the natural next step the paper does not itself supply.
- The same etch could carve channels, mixers, or traps connecting the chamber to the chip's photonic and electronic areas, making the paper's closing vision of biology-plus-electronics-plus-photonics on one die testable.
- Because the etch is a post-processing step, chip-to-chip uniformity may vary; per-chip electrode impedance calibration could turn this proof-of-concept into a quantitative bioimpedance instrument.
- The frequency-dependent measurement capability, though only used to confirm sphere-like behavior here, points toward dielectric-spectroscopy imaging that distinguishes cell types by their impedance signature rather than just locating insulating objects.
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. The paper reports a 65 nm CMOS chip in which a ~225 pL microfluidic chamber and 16 electrodes are formed in the interconnect layers by subtractive wet etching, with on-chip LO generation, multiplexing, and voltage readout. Electrical impedance tomography is performed by injecting an LO signal across pairs of electrodes and measuring the resulting voltages at the other electrodes; the data are transferred off-chip and processed with EIDORS. The central claim is that reconstructed conductivity maps for glass microspheres in a water-filled chamber visually track the microsphere positions (Fig. 6), constituting the first demonstration of fully integrated on-chip microfluidics with EIT. The paper also reports an SNR of 32--52 dB (Fig. 7) and shows reconstruction robustness between 1 kHz and 100 kHz (Fig. 8).
Significance. If the central claim is valid, this is a significant proof-of-concept: it would show that a standard CMOS process can host both picoliter-volume sample confinement and the electronics needed for EIT, without post-processing additions such as silicon or plastic microfluidics. The subtractive-etch fabrication route is already published for photonics by the same group (refs. 9--11), so the new contribution is the application to integrated EIT. The paper is commendably explicit about using EIDORS as an external, standard solver and about the system-level components. However, the evidence supporting the central tomography claim is currently visual and lacks the necessary controls, so the significance is conditional on closing that validation gap.
major comments (4)
- [Sec. IV, Fig. 6] The load-bearing evidence for the central claim is the visual 'strong correlation' between microsphere positions and reconstructed low-conductivity regions. No water-only (empty chamber) baseline reconstruction is reported, so the reader cannot distinguish genuine bulk-conductivity contrast from artifacts caused by per-electrode gain/phase mismatch, channel crosstalk, parasitic capacitances, or nonuniform electrode-electrolyte interface impedance. Because EIDORS solves an ill-posed inverse problem, an uncalibrated reconstruction can map such systematic measurement errors into smooth low-conductivity areas. A baseline reconstruction under identical conditions with only deionized water is essential; without it, Fig. 6 cannot support the claimed correlation.
- [Sec. IV, electrode characterization] The forward model used by EIDORS assumes that the measured boundary voltages are governed by the bulk conductivity distribution. This requires the electrode-electrolyte interface impedances and any fabrication-induced per-electrode variability to be negligible or uniform. The paper does not report any electrode impedance spectroscopy, calibration with known-conductivity solutions, or comparison of measured voltages against a simulated homogeneous-chamber model. A simple test would be to fill the chamber with two or three solutions of known conductivity and compare the recorded boundary voltages with EIDORS predictions; this would establish that the measurement chain is sensitive to bulk conductivity rather than to electrode non-idealities.
- [Sec. IV, Fig. 6 and reconstruction parameters] No quantitative metric is provided for the claimed correlation. The reconstructed maps in Fig. 6 display a colormap whose normalization and range are not specified, and there is no position error, contrast-to-noise ratio, or resolution measure. A quantitative comparison between microsphere centroids from the optical micrographs and the minima of the reconstructed low-conductivity regions (e.g., a table of centroid distances or a correlation coefficient) would make the claim falsifiable and not merely visual. Without such a metric, the statement 'strong correlation' is not supported by the data as presented.
- [Sec. IV, EIDORS setup] The EIDORS reconstruction is not reproducible as described. The paper does not state the electrode model (point vs. complete electrode model), the finite-element mesh resolution, the regularization method, the regularization hyperparameter, or the data normalization. These choices materially affect the output image, especially in a severely ill-posed problem with only 16 electrodes. Reporting this information is necessary both for reproducibility and for assessing whether the regularization itself could create spurious low-conductivity regions. This is a major omission for a measurement-only paper whose central result is an image.
minor comments (5)
- [Title and Abstract] The title contains 'V olume' with an intervening space; this should be corrected to 'Volume'.
- [Sec. II, Fig. 3 caption] Fig. 3 describes test structures with 20 µm × 20 µm chambers and capacities of 4.9 pL and 3.3 pL, while the actual EIT chamber in Sec. III is 150 µm × 150 µm and ~225 pL. Please clarify that Fig. 3 shows separate test structures, not the chamber used for the EIT measurements, to avoid reader confusion.
- [Sec. IV, Fig. 7] The SNR histograms should have labeled axes and error bars or a statement on the number of samples per bin. The text attributes the histogram shape to 'shifts in local temperature and fluid flow' without evidence; at minimum, show the raw amplitude time series or a spectral analysis to support this attribution.
- [Sec. IV, Fig. 8] The colormap scale and normalization are omitted from the reconstructed maps in Fig. 8 as well as Fig. 6. If the display range is not fixed, comparing maps across frequencies is difficult. Please specify whether the color scale is fixed per subfigure or globally.
- [References] Ref. [12] is the correct EIDORS reference, but a version number or software release would aid reproducibility. Some reference entries contain double spaces and inconsistent punctuation; a final copyedit would help.
Circularity Check
No circularity found; the reconstruction pipeline is an external inverse solver and the self-citations supply fabrication precedent, not the target result.
full rationale
The paper's central claim is an experimental demonstration: EIT with fully integrated on-chip microfluidics in 65 nm CMOS. The reconstruction chain is standard EIT: boundary voltages are measured from a 16-electrode array and fed to EIDORS, an external open-source solver (ref. 12), which inverts the Laplace-equation forward model. No parameter is fitted to the data and then renamed as a prediction; the conductivity maps are direct outputs of an independent solver. The self-citations (refs. 9–11) support the subtractive fabrication method used to create the chamber and electrodes, but that method is prior published work, not the EIT result, and no uniqueness theorem or ansatz is imported from those citations to force the reconstruction. The acknowledged limitations—ill-posedness, sensitivity to impurities, temperature/fluid-flow drift, SNR variation—are validation concerns, not circularity: they do not make the reconstructed image equal to the input voltages by construction. No quoted step reduces to its own input, so there is no circular derivation.
Axiom & Free-Parameter Ledger
free parameters (3)
- EIDORS regularization scheme and weight =
not reported
- Stimulation electrode pattern and LO frequency =
50 kHz (Fig. 6); 1-100 kHz (Fig. 8)
- Display conductivity range for reconstructed maps =
not reported
axioms (4)
- standard math Boundary voltages obey the Laplace-equation forward model with known electrode geometry.
- domain assumption Glass microspheres have substantially lower conductivity than the surrounding water.
- domain assumption Measured voltage differences are dominated by the chamber's conductivity distribution, with negligible or invariant electrode-electrolyte interface impedance.
- domain assumption The wet-etched chamber is fluid-tight and water-filled, and all 16 electrodes survive the alternating Al-etch and EDTA/H2O2 processing.
Cite this review
Pith. "Pith review of Electrical Impedance Tomography with an Integrated Picoliter-Volume Subtractive Microfluidic Chamber in 65 nm CMOS." pith.science (2026). https://pith.science/paper/ANHEBOCI
@misc{pith2026250820431,
author = {Pith},
title = {Pith review of: Electrical Impedance Tomography with an Integrated Picoliter-Volume Subtractive Microfluidic Chamber in 65 nm CMOS},
year = {2026},
howpublished = {\url{https://pith.science/paper/ANHEBOCI}},
note = {Machine review of arXiv:2508.20431}
}
read the original abstract
Electrical impedance tomography with fully integrated microfluidics and electronics is presented for the first time in a CMOS chip. Chambers and electrodes are fabricated in the interconnect layers of a 65 nm CMOS chip through post-processing, enabling picoliter-volumes to be processed and imaged. Tomography maps are reconstructed by reading out voltages from a 16-element electrode array and processing the data off-chip, and sources of variation in reconstruction are discussed. The EIT system presented in this work serves as a proof-of-concept towards using CMOS as a platform for co-integrated microfluidics and electronics.
Figures
Reference graph
Works this paper leans on
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This paper was first reviewed by deepseek-v4-flash on August 5, 2026.
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