REVIEW 2 major objections 4 minor 25 references
2.4-GHz Integrated CMOS Low-Noise Amplifier (English Version)
T0 review · 2 major / 4 minor · reviewed 2026-08-05 · deepseek-v4-flash
Pith's one-line read A 130 nm CMOS LNA for 2.4 GHz ZigBee meets the IEEE 802.15.4 RF specifications at 505 µW, with measured S-parameters consistent with post-layout simulations.
desk verdict A working 2.4-GHz CMOS LNA with honest measurements and no overclaiming, but the 'meets IEEE 802.15.4 specs' headline rests partly on an untested gain extrapolation. read the letter →
The pith
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
The reading
What carries the argument
The load-bearing structure is the common-source LNA with inductive degeneration: the source inductor Ls generates the resistive input match without adding thermal noise, the gate inductor Lg tunes it, the cascode transistor M2 cuts Miller effect and improves reverse isolation, and the drain inductor LD forms the output resonance. Its governing trade-off is captured in the gain relation G = Gm² RS / G'o with Gm ≈ 1/(2ω0Ls): gain is set mainly by Ls, while LD's quality factor determines output loss, so the design fixes LD first and then synthesizes the input passives. A sweep over bias current and M1 width then uses the moderate-inversion IIP3 peak, which appears at approximately one current d
What would settle it
Drive the fabricated LNA with a calibrated input below -20 dBm, for example by inserting a precision attenuator and correcting for the analyzer floor, and measure S21 at 2.45 GHz; if the gain falls below 10 dB, the claim that the LNA meets the 802.15.4 gain requirement under normal operation fails.
Extended reading notes
Core claim
On its own terms, the paper establishes that a common-source LNA with inductive degeneration can be systematically designed to satisfy all ZigBee/IEEE 802.15.4 RF requirements at sub-milliwatt power in a 130 nm process. The demonstration combines a design-space sweep over bias current and transistor width, a synthesis step that derives the passive elements for each candidate, and a sizing rule that uses the moderate-inversion IIP3 sweet spot. The selected point, ID = 0.4 mA and W1 = 40 µm, yields a post-layout gain of 10.7 dB, noise figure of 2.7 dB, IIP3 of 0.9 dBm, matching below -20 dB, and 505 µW consumption. Measurements of the fabricated die confirm the S-parameter behavior; the slight
Load-bearing premise
The specification-compliance claim depends on the assumption that the gain measured at -13 dBm, which is 0.5 dB below simulation, stays similarly close at the real operating inputs below -20 dBm; that low-level behavior was extrapolated, not measured.
Editorial extensions
If this is right
- A ZigBee receiver front-end can be implemented with a 505 µW LNA while still leaving gain margin above the standard's 10 dB minimum.
- The same design flow—sweep current and width, synthesize passives, then pick the point at the moderate-inversion IIP3 current density—yields compliant designs without iterative manual tuning.
- The measured S-parameter consistency means post-layout simulation including ESD pads is a reliable predictor for this topology at 2.4 GHz, provided the test signal stays in the linear range.
- Because gain at the analyzer's minimum drive is only 0.5 dB below simulation, the paper expects normal sub -20 dBm operation to meet the >10 dB gain specification.
Reading between the lines
- My inference: the same sizing recipe should transfer to the 868/915 MHz ZigBee bands by rescaling the passives, since the linearity sweet spot is tied to current density rather than frequency.
- My inference: the measured downward frequency shift in S22, attributed to parasitics and inductor coupling, is a testable target for an electromagnetic-extracted redesign; the paper gives a plausible cause, not a proven one.
- My inference: the 505 µW figure sets a concrete budget challenge for the rest of the receiver chain; a full 802.15.4 radio would need mixer, local oscillator, and baseband to fit in a similar or smaller fraction of the total power.
Signed reviews
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. The paper reports the analysis, design, fabrication, and measurement of a 2.4 GHz common-source CMOS LNA with inductive degeneration in 130 nm CMOS, targeting IEEE 802.15.4. A design-space exploration over bias current and M1 width, with passive values synthesized per candidate, yields a 505 µW LNA with post-layout simulated gain 10.7 dB, NF 2.7 dB, IIP3 0.9 dBm, S11=-24 dB, S22=-30 dB, and S12=-41 dB. On-wafer S-parameter measurements were performed at the analyzer's minimum drive of -13 dBm, i.e., outside the LNA's linear range; the paper compares these with large-signal (LSSP) simulations at the same drive and reports consistency, then extrapolates that gain exceeds 10 dB under normal operating input levels. The conclusions state that the fabricated LNA meets the IEEE 802.15.4 specifications.
Significance. If the claims are fully supported, this is a solid, low-power LNA data point for 2.4 GHz short-range receivers and a meaningful contribution to RF IC research infrastructure in Cuba. The paper's strengths include a systematic design-space exploration, post-layout simulations that include pads and ESD protection, and a transparent attempt to compare measured S-parameters with large-signal simulations at the actual measurement drive level rather than with idealized small-signal predictions. The manuscript also candidly discusses deviations attributed to parasitic capacitances and magnetic coupling. However, complete specification compliance of the fabricated chip is not directly demonstrated: NF and IIP3 are simulation-only, and the only measured forward gain was obtained under compression, so the key gain claim rests on an extrapolation. These issues are identifiable and addressable with wording changes or additional measurements.
major comments (2)
- [Section IV-B] The central claim that the fabricated LNA has gain ≥10 dB under normal IEEE 802.15.4 input levels rests on an untested extrapolation. The measured S21 at -13 dBm is 0.5 dB below the LSSP simulation at that drive, and the paper states: "Assuming a similar difference when the circuit operates with input levels below -20 dBm, the gain is expected to remain above 10 dB." The -13 dBm offset, however, is an aggregate of compression, forward-biased ESD diodes (0.6 V DC), parasitic capacitances, and magnetic coupling. Nothing in the manuscript guarantees that this aggregate remains a constant 0.5 dB in the linear regime; in fact, the paper attributes S21 roll-off to "parasitic capacitances higher than modeled" and S22/S12 deviations to unmodeled coupling. A direct low-level S21 measurement (for example, with an external attenuator to reach roughly -40 dBm) is required to support the gain specifi
- [Section IV-B and Conclusions] Only S-parameters were measured; NF and IIP3 appear exclusively as post-layout simulation results (Table III). The abstract carefully attributes NF and IIP3 to simulation, but the Conclusions state "Measurements confirmed simulations within expected deviations," which overstates the evidence. The measurements can confirm S-parameter behavior (and even that at a compressed drive), but they do not confirm the fabricated chip's NF or IIP3. The manuscript should either add on-wafer NF/IIP3 measurements or explicitly state in the conclusions that NF and IIP3 specifications are simulation-based and that the measured chip's compliance for those metrics is not experimentally verified.
minor comments (4)
- [Table I] The header "Frecuency" should read "Frequency."
- [Section II] The sentence beginning "balancing the criteria chosen by the designer (in addition to power, noise..." is duplicated verbatim in the same paragraph.
- [Section IV-B] The sentence about using free area between pads for decoupling capacitors is repeated verbatim in two consecutive paragraphs.
- [Section IV-B / Figure 7] For reproducibility and verification, a small table with the measured S-parameter values (S11, S21, S22, S12) at 2.45 GHz would be more useful than relying only on the plotted curves, whose quantitative values are hard to extract.
Circularity Check
No significant circularity: final LNA metrics come from PDK simulation and measured S-parameters, not from the simplified design equations or from self-citations.
full rationale
The paper's derivation chain is not circular. Section III presents simplified equations (G ≃ Gm^2 RS/G'o, Gm ≃ 1/(2ω0 LS)) but explicitly states they are 'not accurate enough to directly compute final design values' and are used only to provide a logical sequence for selecting passive components. The headline specifications (10.7 dB gain, 2.7 dB NF, 0.9 dBm IIP3, S11/S22 < -20 dB) come from post-layout PDK simulations, and the measured S-parameters are compared against large-signal (LSSP) simulations run at the same -13 dBm drive level as the measurement. This is a genuine benchmark, not a fitted parameter renamed as a prediction. The only notable extrapolation is in Section IV-B, where the authors assume that the 0.5 dB gain difference seen at -13 dBm will be 'similar' at input levels below -20 dBm, so that gain is expected to remain above 10 dB. That is an untested assumption and a correctness risk, but it is not circular: the measured offset is not fitted to the target gain, nor is the target gain defined in terms of the assumption. Self-citations [8], [9], and [24] are contextual (research-line history, process-variation attribution) and are not load-bearing for the central claim of specification compliance. The central results are validated against external measurements and PDK models, so no circular step can be exhibited. Score 0.
Assumptions & free parameters
free parameters (2)
- Bias current ID and transistor width W1 =
ID = 0.4 mA, W1 = 40 µm
- Passive component values (LS, CX, Lg, LD, C1, CP) =
1.8 nH, 246 fF, 13.5 nH, 9.5 nH, 441 fF, 1.24 pF
assumptions (4)
- domain assumption The 130 nm PDK device models accurately represent the fabricated process
- standard math The simplified small-signal input-stage model (Cgs, gm, ideal LS, Lg, CX) is adequate for setting the design sequence
- domain assumption Large-signal S-parameter (LSSP) simulation captures the nonlinear behavior at -13 dBm excitation
- domain assumption The observed S22 frequency shift and gain roll-off are caused by parasitic capacitances and magnetic coupling, not other unidentified effects
Cite this review
Pith. "Pith review of 2.4-GHz Integrated CMOS Low-Noise Amplifier (English Version)." pith.science (2026). https://pith.science/paper/5QQCSOYX
@misc{pith2026250902224,
author = {Pith},
title = {Pith review of: 2.4-GHz Integrated CMOS Low-Noise Amplifier (English Version)},
year = {2026},
howpublished = {\url{https://pith.science/paper/5QQCSOYX}},
note = {Machine review of arXiv:2509.02224}
}
abstract
This paper presents the analysis, design, fabrication, and measurement of an integrated low-noise amplifier (LNA) implemented using a 130 nm CMOS technology, operating in the 2.4 GHz band. The LNA is a crucial component in the performance of receivers, particularly in integrated receivers. The proposed LNA was designed to meet the specifications of the IEEE 802.15.4 standard. Post-layout simulation results, including pads with electrostatic discharge (ESD) protection, are as follows: gain of 10.7 dB, noise figure of 2.7 dB, third-order input intercept point (IIP3) of 0.9 dBm, input and output impedance matching better than -20 dB with respect to 50~$\Omega$ terminations, with a power consumption of 505 $\mu$W powered from a 1.2 V supply. The obtained results fall within the range of those recently reported for the same topology and operating frequency. The measured scattering parameters (S-parameters) are consistent with the simulation results. This work contributes to the development of a new research line in Cuba on the design of radio-frequency (RF) integrated circuits.
Figures
Figures from the paper (2 more)
Reference graph
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Reviewed August 5, 2026 · model on record in the stance chip above.
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