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REVIEW 5 major objections 6 minor 43 references

Guidance and Control Neural Network Acceleration using Memristors

T0 review · 5 major / 6 minor · reviewed 2026-08-05 · deepseek-v4-flash

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Pith's one-line read Simulated memristor hardware learns spacecraft guidance, but device noise keeps accuracy well below digital.

desk verdict Solid feasibility study of memristor-accelerated G&CNET; the abstract overstates retraining recovery and no radiation model backs the space claim, but the core simulations and code are worth a referee. read the letter →

arxiv 2509.02369 v1 pith:O56BLIMU submitted 2025-09-02 cs.AR cs.AIcs.SYeess.SY

Zacharia A. Rudge , Dario Izzo , Moritz Fieback , Anteneh Gebregiorgis , Said Hamdioui , Dominik Dold This is my paper · ORCID
classification cs.ARcs.AIcs.SYeess.SY
keywords memristorin-memorycomputingneuralnetworkacceleratorspacecraftguidanceandcontrolphase-changememoryRRAMhardware-awaretrainingradiationtolerance
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper asks whether memristor-based in-memory computing, using PCM and RRAM devices that store weights and compute in the analog domain, can run the neural networks needed for spacecraft guidance and control. Using the IBM AI Hardware Acceleration Kit, the authors simulate a G&CNET on memristor crossbars with realistic device non-idealities: programming noise, read noise, conductance drift, and stuck-at faults. They find the memristive accelerator can learn expert control actions, and that splitting each weight across more devices reduces loss by averaging noise. Retraining after device degradation restores performance to near-nominal levels for fault ratios up to about 10%. The main obstacle is noise: the best analog model's loss is still an order of magnitude higher than a digital baseline, so the paper positions memristors as a promising but not yet accurate-enough option for space.

What carries the argument

The central mechanism is the memristor crossbar array, which performs matrix-vector multiplication in the analog domain; each network weight is stored as a conductance value in a differential two-resistor (2R) configuration, optionally split across multiple devices per weight (bit-slicing) to average out noise. The simulation is built on the IBM Analog Hardware Acceleration Kit with calibrated PCM (about 2% read noise) and RRAM (about 1%) device models, plus DAC/ADC quantization, IR-drop, and peripheral noise. Hardware-aware training keeps the backward pass ideal and applies device non-idealities only in the forward pass, enabling the network to adapt to its own noise. Bit-slicing works by r

What would settle it

Run the same G&CNET on a real PCM or RRAM crossbar chip, measure its loss with 8 to 16 slices per weight, and compare with the simulated loss; if the real loss remains more than an order of magnitude above the digital baseline under calibrated noise, or if adding radiation exposure to the full chip (including DAC/ADC periphery) degrades performance beyond what retraining can recover, the paper's feasibility claim would be falsified.

Watch

Extended reading notes

Core claim

On its own terms, the paper claims that a guidance and control neural network (G&CNET), trained to map spacecraft state to optimal thrust, can be deployed on simulated memristor crossbars using both PCM and RRAM devices, and that the network can learn the expert actions despite device non-idealities. The load-bearing results are: bit-slicing reduces loss by averaging independent device noise (loss halves from roughly 0.14 to 0.07 with eight slices per weight); retraining after device faults restores performance up to about 10% faults; and conductance drift over 48 hours degrades PCM roughly twice as much as RRAM. The paper explicitly acknowledges that the best memristive model still has loss

Load-bearing premise

The simulation's noise and drift models, calibrated on existing PCM and RRAM chips, are assumed to match the behavior of real devices in a space radiation environment; if actual device noise is worse, the reported feasibility could reverse.

Editorial extensions

If this is right

  • If these results hold, RRAM-based accelerators are better suited than PCM for long-duration missions, since their drift over 48 hours is milder (about 1.5x vs 2x loss increase).
  • Retraining on hardware after device faults could keep a memristor-based controller flying even as devices degrade, as long as faults stay near 10%.
  • The order-of-magnitude loss gap means memristor-based G&CNETs are not yet ready for closed-loop control; noise mitigation is the limiting factor, not drift or faults.
  • The open-source simulation setup with bit-slicing gives mission designers a way to test other candidate networks before committing to hardware.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If real device noise in a space environment exceeds the 1–2% read-noise levels used here, the loss gap would widen; the next decisive test is a radiation test of a full crossbar chip including DAC/ADC periphery.
  • The paper does not quantify energy or area; a direct power comparison of the memristive accelerator against an embedded GPU or microcontroller could show whether the accuracy gap is an acceptable trade-off.
  • Low-pass filtering, ensemble averaging, or temporal redundancy—suggested but not tested in the paper—could close part of the noise gap without changing the hardware.
  • Because memristors also support in-situ update, applications requiring on-board learning (e.g., geodesy or adaptive compression) might see a bigger benefit than the inference-only G&CNET studied here.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

5 major / 6 minor

Summary. The paper presents a simulation study of a memristor-based in-memory computing accelerator for a guidance-and-control neural network (G&CNET). Using the IBM Analog Hardware Acceleration Kit, the authors simulate PCM and RRAM crossbar arrays with calibrated device non-idealities, and evaluate bit-slicing from 1 to 16 devices per weight, conductance drift up to 48 hours, device faults (stuck-at-Gmin from 1% to 80%), and retraining after degradation. They report that analog networks can learn the expert control actions, bit-slicing reduces loss with diminishing returns, retraining largely recovers performance at fault ratios up to about 10%, and the best analog loss remains roughly an order of magnitude above the digital baseline. The paper frames this as a first step toward radiation-tolerant on-board AI acceleration for small satellites.

Significance. If the results hold, this is one of the first demonstrations that a G&CNET can be deployed on simulated memristive hardware, with a realistic treatment of device noise, drift, and faults. Strengths include the use of externally calibrated device models (IBM 1M PCM array, Wan et al. RRAM), the open-source code and data repository, the bit-slicing implementation contributed to the IBM AI HW Kit, and an explicit acknowledgment of the simulation-to-reality gap. The retraining experiment is a practically relevant contribution. However, the space-specific feasibility claim is not yet grounded in a radiation-informed device model, and several experimental reporting gaps (no error bars, undertrained baseline, short drift horizon) limit the strength of the conclusions.

major comments (5)
  1. [Sec. 2.3, Sec. 3 (Fig. 4)] The space-specific feasibility claim rests on device non-ideality models calibrated to ambient measurements (IBM 1M PCM array; Wan et al. RRAM) and on arbitrary stuck-at-Gmin fault ratios with no link to radiation dose. Neither radiation-induced read-noise/drift acceleration nor radiation effects on peripheral ADCs/DACs are modeled. Since radiation tolerance is the stated motivation (Sec. 1), this is a load-bearing gap. Add radiation-informed device parameters or explicitly reframe the paper as a nominal-environment simulation and soften the 'radiation-tolerant' wording in the abstract.
  2. [Sec. 3, Figs. 3 and 4] All plotted results are single means without error bars, seed counts, or confidence intervals. Device noise is stochastic, so observed differences (e.g., RRAM vs PCM, 8 vs 16 slices, retraining recovery from 0.34 to 0.086) may be within run-to-run noise. Report the number of seeds and dispersion (e.g., standard deviation or confidence intervals) for each experiment, or justify with a statistical test that the differences are significant.
  3. [Secs. 2.3, 4.1] Training was limited to 150 epochs, whereas the authors note the original G&CNETs used at least 300 epochs. The digital baseline is therefore undertrained, and the 'order of magnitude' analog-digital gap in Sec. 4 conflates device effects with training length. Train both models to convergence or match epochs, and re-state the gap claim accordingly.
  4. [Sec. 3, Fig. 5] The only end-to-end evaluation is a single open-loop trajectory overlay and validation loss; no closed-loop rollout of the controlled spacecraft is reported. The text itself says noise 'complicates numerically solving the dynamics.' Because G&CNET is a feedback controller, add closed-loop Monte Carlo results (or at least quantify tracking error) before claiming the analog model 'is capable of performing transfers.'
  5. [Sec. 3, Fig. 3 (right)] Conductance drift is only simulated up to 48 hours, while space missions operate on year-long timescales. No extrapolation or long-term drift model is provided, so the conclusion in Sec. 4 that drift has 'negligible or easily compensated' effects is not supported for the intended application. Extend the time horizon or limit the claim explicitly to the tested range.
minor comments (6)
  1. [Sec. 2.3] Provide details on bit-slicing mapping and quantization (number of slices, bit positions, signed/unsigned representation, ADC range, and how the slices are combined) so the implementation is reproducible.
  2. [Sec. 3, Fig. 3 (left)] Clarify the legend ('mean pcm' vs 'pcm', 'mean rram' vs 'rram'). If symbols are individual seeds, state this; if they are means of different runs, explain the distinction.
  3. [Sec. 4.1] The note that 150 epochs is shorter than the original G&CNET training (at least 300 epochs) should be moved to Section 2, since it affects the interpretation of all results, not just future work.
  4. [Sec. 3] The noise-averaging expression should read n_w = n_s / sqrt(x); the current typesetting '1/sqrt(x)*n_s = n_w' is ambiguous.
  5. [Throughout] Typos and formatting: 'att' should be 'at' (Sec. 3); 'e ffect' should be 'effect' (Sec. 1); missing spaces in 'lossL' and 'similaritySC' (Sec. 3).
  6. [References] Consider citing specific radiation-test data for PCM and RRAM at relevant dose/energy ranges, rather than a general reference, to support the radiation-resilience motivation.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: simulation results are externally calibrated and not fitted to the target claims.

full rationale

The paper's central claims (memristive G&CNET feasibility, bit-slicing benefit, degradation and retraining recovery, drift impact) are measured simulation outputs from the IBM Analog Hardware Acceleration Kit, whose PCM and RRAM non-ideality models are calibrated to independent published device data (1M PCM array; Wan et al. Nature 2022). The loss values are not derived from any fitted constant in the paper: the digital baseline is an external reference, device noise/drift parameters come from the simulator's calibrated models, and the fault-ratio experiments inject stochastic stuck-at-Gmin states without tuning them to the reported outcomes. The 1/sqrt(x) noise-scaling comment in Section 3 is explicitly presented as an illustrative assumption ('if we assume... Still, this will have to be studied in more detail in future work'), not as the mechanism generating the loss curves. Self-citations such as G&CNET [23] and geodesyNets [39] supply benchmark networks and suggested future applications, but they are not load-bearing for the memristive acceleration results, and no uniqueness theorem or forced-choice argument imported from the authors' prior work appears. The acknowledged limitations—simulation-only validation, radiation-hardened periphery not modeled, and the gap between calibrated ambient-device models and real space radiation behavior—are fidelity and correctness concerns, not circularity. No prediction reduces by construction to its input, so the appropriate score is 0.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

The paper introduces no new fitted constants, entities, or parameters. It relies on externally calibrated simulator models (IBM AI HW Kit, Wan et al.) for PCM/RRAM noise and drift, and on a prior G&CNET dataset. The key assumptions are the fidelity of the simulator, the validity of the benchmark, and the ideal-backward-pass training model.

assumptions (4)
  • domain assumption The IBM AI HW Kit simulation provides a faithful representation of PCM and RRAM device behavior (noise, drift, faults) based on calibrated models from external arrays.
    Invoked in Section 2.3; the entire study is a simulation, so conclusions about real hardware depend on this.
  • domain assumption The G&CNET architecture and optimal state-action dataset from prior work (ref 23) represent a valid benchmark for space guidance and control.
    Stated in Section 2.1; the paper takes the network and data as given.
  • domain assumption Hardware-aware training with an ideal backward pass models the actual retraining process on memristive hardware.
    Section 2.3: 'an ideal backward pass is assumed, with the non-idealities only affecting the forward pass'.
  • domain assumption Memristors are radiation-resistant, and the peripheral circuits can be radiation-hardened, so the accelerator is suitable for space.
    Introduction cites refs 16 and 10; the paper does not simulate radiation effects on the peripheral DAC/ADC circuits.

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Cite this review

Pith. "Pith review of Guidance and Control Neural Network Acceleration using Memristors." pith.science (2026). https://pith.science/paper/O56BLIMU

@misc{pith2026250902369,
  author       = {Pith},
  title        = {Pith review of: Guidance and Control Neural Network Acceleration using Memristors},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/O56BLIMU}},
  note         = {Machine review of arXiv:2509.02369}
}
read the original abstract

In recent years, the space community has been exploring the possibilities of Artificial Intelligence (AI), specifically Artificial Neural Networks (ANNs), for a variety of on board applications. However, this development is limited by the restricted energy budget of smallsats and cubesats as well as radiation concerns plaguing modern chips. This necessitates research into neural network accelerators capable of meeting these requirements whilst satisfying the compute and performance needs of the application. This paper explores the use of Phase-Change Memory (PCM) and Resistive Random-Access Memory (RRAM) memristors for on-board in-memory computing AI acceleration in space applications. A guidance and control neural network (G\&CNET) accelerated using memristors is simulated in a variety of scenarios and with both device types to evaluate the performance of memristor-based accelerators, considering device non-idealities such as noise and conductance drift. We show that the memristive accelerator is able to learn the expert actions, though challenges remain with the impact of noise on accuracy. We also show that re-training after degradation is able to restore performance to nominal levels. This study provides a foundation for future research into memristor-based AI accelerators for space, highlighting their potential and the need for further investigation.

Figures

Figures reproduced from arXiv: 2509.02369 by the authors.

Figure 1
Figure 1. The architecture of the G&CNET studied. The network is composed of fully connected layers (L (x) ), input variables (state variables y, vy , z, vz and θ) and output vari￾ables (optimal control u1, u2). 2 Methods 2.1 G&CNETs To provide an appropriate algorithm for the evalua￾tion of the suitability of a memristor-based neural net￾work accelerator, several target applications were con￾sidered. Of these, G&CNETs were s… view at source ↗
Figure 2
Figure 2. Memristors arranged in crossbar arrays, capable of performing matrix-vector-multiplication (MVM). Memristor crossbars (shown in [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. (left) Loss of model predictions plotted against slices. Digital baseline is shown as a dashed line. (right) The effect of conductance drift on the accuracy of the network. slices per weight. In increasing the number of slices, we are in effect averaging the noise over multiple de￾vices. We also see diminishing returns in the loss re￾duction as the number of slices increases towards 16. This is likely due to the fac… view at source ↗
Figures from the paper (2 more)
Figure 4
Figure 4. Figure 4: shows the diminishing performance of the 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Fault ratio 10 1 10 0 Loss Type pcm retrained rram retrained rram pcm [PITH_FULL_IMAGE:figures/full_fig_p004_4.png]
Figure 5
Figure 5. Figure 5: The network prediction transformed into spher￾ical coordinates θ and φ (lines) compared to the optimal ground truth (points). Both the analog (RRAM, left) and digital (right) models are shown. 4 Discussion We provide – by way of extensive simulation – a first glimpse a…

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    https://www.nature.com/articles/s41586- 022- 04992-8 (2024) (Aug. 2022)

    2024

Pith tools

Reviewed August 5, 2026 · model on record in the stance chip above.