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REVIEW 3 major objections 6 minor 58 references

Characterizing and Optimizing Realistic Workloads on a Commercial Compute-in-SRAM Device

T0 review · 3 major / 6 minor · reviewed 2026-08-05 · deepseek-v4-flash

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Pith's one-line read This paper claims that on a commercial compute-in-SRAM device, three data-movement optimizations make retrieval-augmented-generation (RAG) retrieval 4.8x–6.6x faster than an optimized CPU and as fast as an NVIDIA A6000 GPU while using 54.4x

desk verdict First credible end-to-end evaluation of a commercial compute-in-SRAM device; measured Phoenix/APU data are solid, but the RAG speedup and energy claims depend on simulated HBM and should be read as provisional. read the letter →

arxiv 2509.05451 v1 pith:HBB3N446 submitted 2025-09-05 cs.AR cs.PF

Niansong Zhang , Wenbo Zhu , Courtney Golden , Dan Ilan , Hongzheng Chen , Christopher Batten , Zhiru Zhang This is my paper · ORCID
classification cs.ARcs.PF
keywords compute-in-SRAMGSIAPUanalyticalmodelingretrieval-augmentedgenerationexactnearestneighborsearchdata-movementoptimizationenergyefficiencyvectorregisterreduction
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Compute-in-SRAM promises to save energy by computing where data sits, but most evidence so far has come from simulators or small prototypes. This paper measures a commercial device, the GSI APU, under realistic workloads and argues that its bottleneck is not arithmetic but data movement inside vector registers and across memory levels. It introduces an analytical framework that predicts this behavior and uses it to develop three optimizations—communication-aware reduction mapping, coalesced DMA, and broadcast-friendly data layouts—that speed binary matrix multiplication 18.9x and make exact nearest-neighbor retrieval for RAG 4.8x–6.6x faster than an optimized CPU. In the paper's setup, where the off-chip HBM2e memory is simulated and all other components are measured on real hardware, the optimized system serves RAG queries with GPU-level latency while consuming roughly 1% of the GPU's energy.

What carries the argument

The operative object is the APU's vector register (VR): 32,768 16-bit elements stored bit-sliced across 16 banks with a bit processor per column. Because every element of a VR is processed in parallel, element-wise (inter-VR) operations are cheap, while moving data within a single VR—shifts, subgroup reductions, scattered stores—is serialized through global latch lines and scales with shift distance or group size. The analytical framework converts each data-movement and computation operation into a cycle cost, and the three optimizations are exactly the transformations that move work from the expensive intra-VR class to the cheap inter-VR class and replace PIO with DMA or smaller lookup tabl

What would settle it

Connect a GSI APU to real HBM2e-class memory (or a cycle-accurate emulator of it) and run the paper's optimized exact-nearest-neighbor inner-product kernel on the 10/50/200GB corpora, measuring retrieval latency with the same cycle counters. If the measured latency diverges from the Ramulator 2 + DRAMPower prediction by more than the ~6% modeling error reported for Phoenix, or if the 4.8x–6.6x CPU speedup and GPU parity do not reproduce, the central claim fails.

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Extended reading notes

Core claim

On a commercial compute-in-SRAM accelerator, realistic workloads are governed less by peak TOPS than by where data is placed and how it moves: reductions within one vector register ('intra-VR') cost roughly an order of magnitude more than element-wise operations spanning registers ('inter-VR'), PIO transfers are far costlier than DMA, and lookup bandwidth grows with table size. The three proposed optimizations—communication-aware reduction mapping (turning spatial intra-VR reductions into temporal inter-VR ones), coalesced DMA (merging duplicate transfers via subgroup copies), and broadcast-friendly data layouts (shrinking lookup table spans)—compound to take a 1024x1024 binary matrix multip

Load-bearing premise

The load-bearing premise is that the simulated HBM2e off-chip memory behaves like a real 380–420 GB/s HBM; the on-chip parts are measured, but the headline RAG retrieval and energy results combine those measurements with modeled memory timing.

Editorial extensions

If this is right

  • Exact nearest-neighbor RAG becomes practical without the accuracy loss of approximate search: corpora of 10–200GB can be scanned at GPU-level latency, so LLM answers can cite from full corpora rather than a pruned index.
  • For compute-in-SRAM devices generally, the paper implies that data-layout and data-movement optimization can be worth more than increasing raw TOPS, and future designs that support cheap intra-VR reduction and flexible DMA would inherit these gains.
  • The 54.4x–117.9x energy gap suggests that energy-hungry retrieval serving could be offloaded to compute-in-SRAM devices, with system-level savings in power and cooling infrastructure beyond the chip's own 60W TDP.
  • The analytical framework predicts Phoenix benchmark latencies within an average of 97.3%, meaning developers can evaluate candidate mappings before programming the device, shortening the optimization loop.
  • The workload characterization shows compute-in-SRAM is not a universal accelerator: applications with frequent intra-VR operations, such as histogram, matrix multiply, and reverse index, gain less, so target selection matters.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • An extension the paper leaves implicit: the RAG speedup is sensitive to achieved off-chip bandwidth, so a useful next experiment is a sensitivity sweep of retrieval latency against HBM bandwidth and latency to see where the APU loses its CPU-beating and GPU-matching advantage.
  • The energy breakdown, where static power is about 71% of the 200GB retrieval energy, suggests that the largest energy win for in-memory retrieval may come from faster time-to-sleep and lower standby power, not from per-operation compute efficiency; power gating could multiply the reported advantage.
  • The binary matrix multiplication recipe—scalar-vector product mapping, spatial unrolling, DMA coalescing, and broadcast-friendly layout—likely transfers to other bit-parallel kernels, such as binarized transformers, which share the same popcount-accumulate structure.
  • The same exact-nearest-neighbor inner-product kernel underlies recommendation, semantic caching, and agent-memory retrieval, so the measured 4.8x–6.6x retrieval speedup is a plausible template for those workloads too.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. This paper presents a measurement-based study of the GSI APU, a commercial compute-in-SRAM accelerator with 2M bit processors. The contributions are: (i) a latency/energy characterization of Phoenix workloads and binary matrix multiplication on the real device; (ii) an analytical latency model built from measured data-movement and computation costs; (iii) three optimizations—communication-aware reduction mapping, coalesced DMA, and broadcast-friendly data layouts; and (iv) an end-to-end retrieval-augmented generation (RAG) comparison against CPU and GPU. The on-chip RAG components are measured on the APU, but the off-chip memory system is replaced by a Ramulator 2 / DRAMPower simulation of HBM2e. This simulated HBM2e directly supports the headline claims of 4.8x–6.6x retrieval acceleration and 1.1x–1.8x end-to-end speedup over CPU, as well as the claim of matching an NVIDIA A6000.

Significance. If the claims are sustained, this is a valuable data point: it is one of the first realistic-workload evaluations on a commercial compute-in-SRAM device, with unusually detailed cycle-level measurements and on-board energy telemetry. The analytical model's maximum 6.2% error on eight Phoenix benchmarks is a genuine validation, and the 1024x1024 binary matrix multiplication case study (226.3 ms to 12.0 ms) is concrete and well explained. However, the most prominent RAG claims are not measured on the device as it exists: the real 23.8 GB/s DDR4 is replaced by a simulated 380–420 GB/s HBM2e, and the simulation is not validated against the APU's actual DMA behavior. The energy comparison in the same section is also ambiguous about which memory system was measured. These issues are load-bearing for the abstract's headline numbers, but they are fixable with sensitivity analysis and clarification, so the underlying contribution remains credible.

major comments (3)
  1. [Section 5.3.1, Table 8, Fig. 14] The RAG retrieval speedups reported in the abstract and §5.3.3 (6.3x/4.8x/6.6x retrieval; 1.05x/1.15x/1.75x end-to-end) depend on replacing the device's 23.8 GB/s DDR4 with a Ramulator 2 / DRAMPower-simulated HBM2e. In Table 8, the 'Load Embedding' row is the only component using the simulated memory: at 200 GB, 2.4 GB of embeddings completes in 6.1 ms, corresponding to ~393 GB/s. At the device's real DDR4 bandwidth, the same transfer would take ~101 ms, so the optimized 200 GB retrieval would be approximately 179 ms rather than 84.2 ms. This would lower the CPU retrieval speedup from ~6.6x to ~3.1x and the end-to-end gain from ~1.75x to ~1.5x. The paper should either report RAG results at the actual DDR4 bandwidth as the primary numbers or provide validation (e.g., a bandwidth sensitivity sweep, measured DMA efficiency, and a description of how Ramulator timings were coupled to the meas
  2. [Section 5.3.5, Figure 15] The 54.4x–117.9x energy-efficiency claim is presented as applying to the optimized APU RAG system, but the energy measurements use the on-board UCD9090/ISL8273M telemetry of the actual Leda-E board (Section 5), which contains DDR4, while the latency results in the same evaluation use the simulated HBM2e. The paper does not state whether the reported 'APU energy' includes the simulated HBM's energy (e.g., via a DRAMPower HBM power model) or only the measured DDR4 system. If it is the latter, the energy claim is for a different configuration than the latency claim; if it is the former, the HBM energy model must be described. This distinction matters for the headline comparison with the A6000 and should be clarified in a revision.
  3. [Section 3.3, Eq. (1)] The reduction latency model is a cubic polynomial in log2(subgroup size) with eight experimentally fitted coefficients (alpha_i, beta_i). The paper does not report the fitting procedure, the number of measurements, residuals, or confidence intervals. The aggregate validation in Table 7 does not isolate Eq. (1) from the rest of the framework, so a good aggregate error does not establish that the polynomial form generalizes. Since the paper advertises the framework as a flexible tool for design-space exploration, the model needs a more rigorous fit/validation narrative: data points used, residuals per subgroup size, and ideally an out-of-sample check (e.g., leave-one-benchmark-out). The current presentation is under-specified for assessing how much of the 97.3% accuracy comes from the polynomial form versus the measured constants in Table 4.
minor comments (6)
  1. [Section 5.3.1] The text mentions 'two GPUs (one dedicated to generation and the other to retrieval)' but the subsequent comparison is unclear about the memory bandwidth and model of the retrieval GPU. Please state whether the retrieval GPU is the same A6000 model or a different one.
  2. [Table 4] The column header 'Analytical Meas.' is ambiguous; clarify that the two columns are modeled and measured cycles, and state the units explicitly.
  3. [Eq. (10)] The printed formula appears to be missing a multiplication operator ('...· 𝑀 ⌊𝑙/𝑁⌋ ·𝐾'); check the rendering.
  4. [Figure 13] The legend defines Opt1/2/3 only in the text; add the definitions to the caption for readability.
  5. [Section 2.1.1] The phrase '16-bit IEEE floating point' should be 'IEEE binary16' to avoid ambiguity; the following sentence mentions a 'custom GSI floating point format with a 6-bit exponent and a 9-bit mantissa,' which is non-standard and should be flagged as such.
  6. [Section 5.3.1] The simulated HBM2e configuration ('16 GB, 2 ranks, 8 channels, 1.6 GHz') is described in one sentence; please provide the key timing parameters (tCK, tRCD, tCL, tRP) or cite the Ramulator 2 configuration file so the results are reproducible.

Circularity Check

0 steps flagged · score 2.0 of 10

No circular derivation: headline results are measured on hardware (plus explicitly simulated HBM), not derived from the fitted analytical framework; self-citations are not load-bearing.

full rationale

The paper's central claims (Phoenix speedups, RAG speedups, energy ratios) come from direct measurement on the GSI APU or from combining measured on-chip times with Ramulator-2/DRAMPower-simulated HBM2e timings; they are not obtained by plugging the conclusion back into the analytical model. The framework's constants (Tables 4–5) are empirically measured microbenchmark latencies, and Table 7 composes those latencies to predict Phoenix runtimes with ≤6.2% error. That is a compositional sanity check on the same device, not a self-validating derivation. No parameter is fitted to the RAG result and then renamed as a prediction: the RAG speedups are hardware measurements, and the load-embedding component is simulated under an explicitly disclosed assumption. Table 8 states: 'Load embedding latency reflects simulated HBM2e performance; all other values are measured on GSI APU hardware.' The abstract similarly says: 'The shared off-chip memory bandwidth is modeled using a simulated HBM, while all other components are measured on the real compute-in-SRAM device.' This makes the 4.8–6.6x retrieval and 1.1–1.8x end-to-end numbers conditional on the HBM simulation being representative — a validity/correctness caveat, not a circularity. Self-citations to prior APU work by the same group ([18], [19], [33]) are background examples and are not load-bearing; the paper imports no uniqueness theorem or ansatz from them. The score of 2 reflects the minor self-citations and the disclosed simulation condition, not an identified circular step.

Assumptions & free parameters 4 free parameters · 4 assumptions · 0 invented entities

The paper is an empirical characterization, so its 'free parameters' are measured hardware constants rather than theoretical fits. The most consequential assumptions are the representativeness of the simulated HBM and the comparability of the two energy measurement methods. No new physical entities are postulated.

free parameters (4)
  • Reduction polynomial coefficients alpha_i, beta_i (i=0..3) = 8 values, not all listed; fitted to microbenchmarked subgroup reduction latencies
    Equation 1 models reduction latency as a cubic polynomial in log2(subgroup size) with coefficients linear in log2(group size). The 8 coefficients (alpha_i, beta_i) are determined experimentally from measured APU latencies, so they are fitted parameters central to the analytical framework.
  • DMA bandwidth and init overhead constants = e.g., 0.19d+411, 0.63d+548, 22272 cycles for L4->L1
    Table 4 lists linear latency models for DMA transfers with measured slope and intercept. These constants are fitted to device measurements and used directly in the framework's predictions.
  • Lookup table coefficient C and init overhead = 7.15 cycles/entry, 629 cycles init
    The lookup latency model T_lookup = C*sigma + T_init uses C=7.15 measured on the APU. This constant affects the broadcast-friendly layout optimization analysis.
  • Shift cost constant = 373 cycles per element for shift_e(k)
    The intra-VR shift model assumes latency proportional to shift magnitude with a measured constant C=373. This parameter affects the reduction cost model.
assumptions (4)
  • domain assumption The GSI APU is a representative instance of the general-purpose compute-in-SRAM abstraction in Figure 1.
    Section 3.1 assumes the target system matches the PCIe-based multi-level memory hierarchy and vector processor abstraction. The paper generalizes its findings from the APU to other CIM systems, which requires this representativeness assumption.
  • domain assumption The simulated HBM2e memory system, built with Ramulator 2 and DRAMPower, accurately models off-chip memory for the RAG evaluation.
    Section 5.3.1 replaces the APU's real DDR4 (23.8 GB/s) with a simulated HBM2e at 380-420 GB/s. All RAG performance and energy claims depend on this simulation matching a real HBM system's behavior.
  • domain assumption nvidia-smi GPU power readings and on-board APU point-of-load power monitors measure comparable device-level energy.
    Section 5.3.5 compares GPU energy from nvidia-smi with APU energy from on-board UCD9090/ISL8273M monitors. The 54.4x-117.9x energy-efficiency claim assumes these different measurement methods are consistent.
  • ad hoc to paper Subgroup reduction latency follows the cubic-in-log-subgroup-size polynomial form of Equation 1.
    Equation 1 asserts that reduction cost is a degree-3 polynomial in log2(s) with coefficients that are linear in log2(r). This functional form is assumed based on observed hierarchical behavior, not derived from first principles, and the coefficients are fitted.

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Pith. "Pith review of Characterizing and Optimizing Realistic Workloads on a Commercial Compute-in-SRAM Device." pith.science (2026). https://pith.science/paper/HBB3N446

@misc{pith2026250905451,
  author       = {Pith},
  title        = {Pith review of: Characterizing and Optimizing Realistic Workloads on a Commercial Compute-in-SRAM Device},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/HBB3N446}},
  note         = {Machine review of arXiv:2509.05451}
}
abstract

Compute-in-SRAM architectures offer a promising approach to achieving higher performance and energy efficiency across a range of data-intensive applications. However, prior evaluations have largely relied on simulators or small prototypes, limiting the understanding of their real-world potential. In this work, we present a comprehensive performance and energy characterization of a commercial compute-in-SRAM device, the GSI APU, under realistic workloads. We compare the GSI APU against established architectures, including CPUs and GPUs, to quantify its energy efficiency and performance potential. We introduce an analytical framework for general-purpose compute-in-SRAM devices that reveals fundamental optimization principles by modeling performance trade-offs, thereby guiding program optimizations. Exploiting the fine-grained parallelism of tightly integrated memory-compute architectures requires careful data management. We address this by proposing three optimizations: communication-aware reduction mapping, coalesced DMA, and broadcast-friendly data layouts. When applied to retrieval-augmented generation (RAG) over large corpora (10GB--200GB), these optimizations enable our compute-in-SRAM system to accelerate retrieval by 4.8$\times$--6.6$\times$ over an optimized CPU baseline, improving end-to-end RAG latency by 1.1$\times$--1.8$\times$. The shared off-chip memory bandwidth is modeled using a simulated HBM, while all other components are measured on the real compute-in-SRAM device. Critically, this system matches the performance of an NVIDIA A6000 GPU for RAG while being significantly more energy-efficient (54.4$\times$-117.9$\times$ reduction). These findings validate the viability of compute-in-SRAM for complex, real-world applications and provide guidance for advancing the technology.

Figures

Figures reproduced from arXiv: 2509.05451 by the authors.

Figure 2
Figure 2. Performance of various matrix multiplication ker [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. The GSI APU system and APU core logic view, the memory hierarchy is highlighted in [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. The physical bank organization of one GSI APU core and the [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗
Figures from the paper (11 more)
Figure 5
Figure 5. Figure 5: Simple vector addition code demonstrating APU [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 6
Figure 6. Figure 6: An example of modeling application latency with the analytical framework. We developed a Python function library with an interface similar to the GSI-provided C++ API. This example models the latency of the Histogram applica￾tion from the Phoenix benchmark suite [41]. …
Figure 7
Figure 7. Figure 7: Motivating example: binary matrix multiply implemented as an inner-product algorithm on APU. [PITH_FULL_IMAGE:figures/full_fig_p008_7.png]
Figure 8
Figure 8. Figure 8: Reduction axis spatial vs. temporal mapping. [PITH_FULL_IMAGE:figures/full_fig_p008_8.png]
Figure 9
Figure 9. Figure 9: Spatially unrolling 𝑖-axis fully utilizes the VR, en￾ables inter-VR reduction, and achieves a contiguous layout of results. 𝑂𝐼 = 𝑀 · 𝑁 · 𝐾 · 𝛼 (𝑀𝐾 + 𝑁𝐾 · ⌊𝑙/𝑁⌋ + 𝑀𝑁) · sf(u16) (9) Assuming matrix 𝐴 is stored in row-major order, the run-time cost of moving it involves t…
Figure 10
Figure 10. Figure 10: Coalescing DMA – leverage subgroup copy to re [PITH_FULL_IMAGE:figures/full_fig_p009_10.png]
Figure 11
Figure 11. Figure 11: Broadcast-friendly data layout example – (a) a row-major data layout requires a lookup table of size 18. (b) A [PITH_FULL_IMAGE:figures/full_fig_p010_11.png]
Figure 12
Figure 12. Figure 12: Binary matrix multiplication runtime breakdown with different optimizations. Opt1: communication-aware reduction mapping. Opt2: DMA Coalescing. Opt3: broadcast￾friendly data layout [PITH_FULL_IMAGE:figures/full_fig_p010_12.png]
Figure 13
Figure 13. Figure 13: Latency comparison across workloads from the Phoenix Benchmark Suite, normalized to the single-threaded Intel Xeon Gold CPU baseline. Opt1: communication-aware reduction mapping. Opt2: DMA Coalescing. Opt3: broadcast-friendly data layout. The primary source of error a…
Figure 14
Figure 14. Figure 14: Inference time breakdown of CPU, GPU, vs. compute-in-SRAM with and without optimizations. The Llama3.1-8B generative model runs on a dedicated GPU. Opt1: communication-aware reduction mapping. Opt2: DMA Coa￾lescing. Opt3: broadcast-friendly data layout. 5.3.3 End-to-E…
Figure 15
Figure 15. Figure 15: Top-5 retrieval process energy comparison with GPU. Results are measured on GSI Leda-E APU and NVIDIA A6000 GPU. at 200 GB). We optimize inner-product search on the compute-in￾SRAM accelerator via communication-aware reduction mapping and a broadcast-friendly query la…

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Pith tools

Reviewed August 5, 2026 · model on record in the stance chip above.