REVIEW 4 major objections 5 minor 57 references
Synthesis of Sound and Precise Leakage Contracts for Open-Source RISC-V Processors
T0 review · 4 major / 5 minor · reviewed 2026-08-04 · deepseek-v4-flash
Pith's one-line read LeaSyn automatically synthesizes leakage contracts that are both sound and precise for RISC-V processors, directly from register-transfer-level designs.
desk verdict A real step forward in leakage-contract synthesis, with a couple of addressable warts: a precision-formula typo and an honest but under-specified dependence on template completeness. read the letter →
The pith
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
The reading
What carries the argument
The load-bearing object is the contract template: a finite set of contract atoms, each an applicability predicate over architectural states and a leakage function that maps a state to an observation. Any subset of atoms is a candidate contract. The paper introduces two notions that make template-based synthesis tractable: strongly-distinguishing atoms and xor-distinguishing pairs, which together fully characterize when any contract distinguishes a test case (Proposition 1). This characterization feeds an ILP whose objective minimizes false positives while forcing all empirically attacker-distinguishable tests to be contract-distinguishable. A stuttering product circuit built from two copies
What would settle it
Take a processor with a known timing leak that is absent from the supplied template, for example a cache whose timing depends on whether two consecutive accesses hit the same line when the template only exposes addresses. Running LeaSyn should fail to produce a sound contract, or should return a contract with low precision, as the Ibex-cache experiment already shows. More directly, one could take a synthesized contract and search by black-box differential testing on random program pairs for a pair of executions with identical contract traces but different retirement times; finding one would fa
Extended reading notes
Core claim
The central claim is that LeaSyn is the first tool to automatically synthesize leakage contracts that are both sound and precise from register-transfer-level processor designs. Soundness means any two executions an attacker can tell apart by observing instruction retirement must produce different contract traces; precision means the contract over-approximates actual leakage as little as possible. The paper formalizes contracts as subsets of a user-provided template of atoms, each an applicability predicate paired with a leakage function. LeaSyn first characterizes leakage empirically on generated test cases, solves an integer-linear program to pick a minimal atom set that distinguishes all a
Load-bearing premise
LeaSyn's soundness guarantee holds only if the user-supplied contract template already contains an atom capable of expressing every leak the processor actually has; if some leak has no matching atom, no contract in the search space is sound.
Editorial extensions
If this is right
- A user who can write or reuse a template no longer needs to reverse-engineer timing leaks manually; the tool returns a machine-checked contract from RTL.
- Software-level constant-time reasoning can be tied to a specific processor: programs can be checked against the synthesized contract instead of against a generic, overly conservative policy.
- The alternating loop is guaranteed to terminate because each bounded counterexample rules out at least one candidate contract, so the search is finite.
- The precision measurements indicate that contracts synthesized by LeaSyn distinguish far fewer attacker-indistinguishable executions than contracts from prior sound synthesis approaches, so fewer secure programs would be rejected as leaky.
- The bounded-verification step with a dynamic instruction bound can serve as a fast pre-filter before expensive unbounded verification, reducing total synthesis time.
Reading between the lines
- Because the guarantee in Proposition 6 is relative to the test cases explored during synthesis, the claimed precision is an empirical property of those tests, not a mathematical optimum over all possible programs; different test sets could yield different optimal contracts.
- The single-line-cache case suggests the main practical bottleneck is template expressiveness: richer atoms encoding something like 'same address as the immediately preceding access' could probably restore high precision for cores with small caches.
- The same synthesis loop could in principle be applied to other attacker models and instruction sets, since the formal model is not RISC-V-specific; the RISC-V formal interface is only the implementation substrate.
- If templates were extended with atoms that expose sequences of instructions or speculation-related events, the method might generalize to speculative-leak contracts, though the paper explicitly leaves that to future work.
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. The paper presents LeaSyn, a tool and methodology for synthesizing leakage contracts for RISC-V processors directly from RTL. The user provides a contract template consisting of atoms; LeaSyn simulates generated test cases to characterize attacker-visible and contract-distinguishable behavior, uses an ILP to pick the most precise subset of atoms, alternates synthesis with bounded model checking to discover missed leaks, and finally invokes the LeaVe verifier for an unbounded soundness check. The authors evaluate on six open-source RISC-V cores and report contracts that are more precise than those from prior tools (LeaVe, Mohr et al., ConjunCT, VeloCT, RTL2MμPATH). The formal development includes propositions connecting the ILP constraints to distinguishability, the bounded verification to a bounded soundness guarantee, and the final Phase 3 to soundness of the synthesized contract.
Significance. If the results hold, this is a useful step toward automating a labor-intensive hardware-security task: deriving sound and precise ISA-level leakage contracts. The paper's strengths are its explicit formal model, the combination of empirical characterization with bounded and unbounded verification, the open-source implementation, and a broad evaluation over multiple core families with comparisons to several prior approaches. The central insight—using strongly-distinguishing atoms and xor-distinguishing pairs to characterize template distinguishability—is clean and well suited to the ILP formulation. The significance is somewhat qualified by the dependence on user-provided templates and on manually supplied invariants for the final unbounded verification, both acknowledged in the paper but relevant to the "automatic" claim.
major comments (4)
- [§6.1 (Evaluating precision)] The definition of precision as "FP/(TP+FP)" contradicts every reported value. With that formula, a perfect contract would have precision 0 and the Ibex-cache result 0.579 would be better than 0.999. Table 1, Table 2, Table 3, and Figure 2(b) are all consistent with the standard definition precision = TP/(TP+FP). This is a load-bearing error for the RQ1/RQ4 conclusions and must be corrected in the formula and in any accompanying prose.
- [§4.4, §5, §6.1] The unbounded soundness guarantee is not obtained by LeaSyn alone: Phase 3 relies on the LeaVe verifier with user-supplied relational invariants, and the evaluation explicitly re-uses manually constructed invariants from Wang et al. [50]. The paper presents LeaSyn as "automatically synthesizing" sound contracts, but for a new core a user may need to hand-craft these invariants. The manuscript should state this dependency in the main contributions and clarify which parts of the pipeline are automatic and which require expert input.
- [§4.3 and §7] The soundness of any output contract is conditional on the user-provided template being expressive enough to capture all leaks of the target. Section 7 acknowledges this, and RQ3 shows templates I, R, M alone admit no sound contract. However, the paper does not specify what LeaSyn does when the ILP in Eq. (1) becomes infeasible or when Phase 2b keeps producing counterexamples that no subset of T can distinguish. Since the termination argument in §4.3 only says each iteration rules out at least one contract, the behavior in the no-sound-contract case should be described explicitly, including the diagnostic returned to the user.
- [Proposition 6] The theorem states that the synthesized contract "distinguishes as few attacker-distinguishable test cases as possible," but the ILP objective in §4.2 minimizes false positives among attacker-indistinguishable test cases, and the surrounding text in §1 and §4.2 uses "attacker-indistinguishable." As written, Proposition 6 is either a typo or a different, unproved claim. Please correct the wording so the formal guarantee matches the synthesis objective.
minor comments (5)
- [§4.3] The retirement predicate is denoted φ in §3.1 and ψ in §4.3 and Appendix C; please unify the notation.
- [§6.1] The precision metric should be defined with enough context to distinguish TP and FP (e.g., TP = contract- and attacker-distinguishable, FP = contract-distinguishable but attacker-indistinguishable). The current sentence is also unclear about whether the validation set is balanced or whether TP+FP is always nonzero.
- [§2.4] In the example, Ctr2 is written both as { (div, "Reg[RS2]") } and then later as { (div, "Reg[RS2]=0?") } in the same section; this is confusing even though the template has changed. Consider renaming the contracts across template revisions.
- [§6.2 (RQ4)] The table labels "same-programs" and "different-programs" are used inconsistently with a hyphen and as separate words; please make them consistent.
- [§A.2] In the proof of Proposition 2, Lemmas 1–3 are stated after Lemma 1 references them; reordering or forward-referencing would improve readability.
Circularity Check
No significant circularity: the synthesis objective is explicitly scoped to explored test cases, soundness is checked by an independent unbounded verifier, and the template dependence is an acknowledged limitation rather than a circular step.
full rationale
LeaSyn's derivation chain separates three distinct activities. (1) Empirical characterization (§4.1) simulates test cases to obtain attacker distinguishability and template distinguishability; this is input data, not an output claim. (2) ILP synthesis (§4.2) selects atoms to satisfy Eq. (1) while minimizing false positives; Proposition 3 is a correctness statement about that optimization, and Proposition 6 explicitly limits the precision guarantee to 'test cases explored during the synthesis process', so it does not pass off a fitted objective as an external prediction. (3) Soundness is not claimed by construction: the paper alternates with bounded BMC (§4.3) and then invokes the LeaVe unbounded verifier (§4.4), relying on Wang et al. [50, Theorem 2]. That citation is to a separately published, peer-reviewed tool and theorem by the same research group; it is load-bearing but it is independent prior evidence, not an output of this paper, and the paper does not fit parameters to make that theorem true. The main limitation—that soundness and precision depend on the user-supplied template containing atoms able to express the processor's leaks—is stated explicitly in Section 7 ('Our approach critically relies on user-provided contract atoms...') and is demonstrated in RQ3, where isolated I, R, and M templates admit no sound contract. This is a search-space limitation, not a self-referential definition: the tool can fail or return less precise contracts when the template is inadequate, and the paper says so. No equation is defined in terms of the result it claims to prove, and no prior-work citation is used to forbid alternative choices. The comparison contracts from prior work are either taken from the respective papers or reconstructed with disclosed templates; this affects fairness, not circularity. Overall, the central claim is independently checkable: the synthesized contract is tested on held-out validation sets, and the unbounded verification is an external proof obligation.
Assumptions & free parameters
free parameters (1)
- BMC bound k, attacker bound b, instruction bound i =
k=51, b=12, i=1 for most Ibex runs; e.g., DarkRISCV-2: k=15, b=10, i=1
assumptions (5)
- domain assumption Architectures and microarchitectures are deterministic state machines; ISA compliance connects architectural and microarchitectural traces via a retirement predicate (Section 3.1).
- domain assumption The attacker model is a deterministic function Atk mapping each microarchitectural state to an observation; the considered attacker observes retirement timing (Section 3.3, Section 6.1).
- ad hoc to paper Contract templates satisfy mutual exclusivity of applicability predicates for atoms sharing a leakage function and disjoint images of different leakage functions (Section 3.2).
- domain assumption LeaVe unbounded verification is sound and the manually constructed invariants from [50] are sufficient for the six cores (Section 4.4, Section 6.1).
- domain assumption The synthesis loop terminates because the template is finite and each counterexample rules out at least one contract (Section 7, 'Termination of the synthesis loop').
Cite this review
Pith. "Pith review of Synthesis of Sound and Precise Leakage Contracts for Open-Source RISC-V Processors." pith.science (2026). https://pith.science/paper/7FR4F5YC
@misc{pith2026250906509,
author = {Pith},
title = {Pith review of: Synthesis of Sound and Precise Leakage Contracts for Open-Source RISC-V Processors},
year = {2026},
howpublished = {\url{https://pith.science/paper/7FR4F5YC}},
note = {Machine review of arXiv:2509.06509}
}
read the original abstract
Leakage contracts have been proposed as a new security abstraction at the instruction set architecture level. Leakage contracts aim to capture the information that processors may leak via microarchitectural side channels. Recently, the first tools have emerged to verify whether a processor satisfies a given contract. However, coming up with a contract that is both sound and precise for a given processor is challenging, time-consuming, and error-prone, as it requires in-depth knowledge of the timing side channels introduced by microarchitectural optimizations. In this paper, we address this challenge by proposing LeaSyn, the first tool for automatically synthesizing leakage contracts that are both sound and precise for processor designs at register-transfer level. Starting from a user-provided contract template that captures the space of possible contracts, LeaSyn automatically constructs a contract, alternating between contract synthesis, which ensures precision based on an empirical characterization of the processor's leaks, and contract verification, which ensures soundness. Using LeaSyn, we automatically synthesize contracts for six open-source RISC-V CPUs for a variety of contract templates. Our experiments indicate that LeaSyn's contracts are sound and more precise (i.e., represent the actual leaks in the target processor more faithfully) than contracts constructed by existing approaches.
Figures
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