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REVIEW 3 major objections 4 minor 26 references

Feeding a robust frequency estimate into a standard three-phase phase-locked loop cuts phase-locking error dramatically during frequency ramps and load steps.

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

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2026-08-04 15:26 UTC pith:2ELE5ZSB

load-bearing objection Useful incremental PLL paper with genuine hardware data, but the headline comparison is against zero feedforward, not the standard constant-feedforward SRF-PLL, so the claimed advantage is overstated. the 3 major comments →

arxiv 2509.19111 v2 pith:2ELE5ZSB submitted 2025-09-23 eess.SY cs.SY

Robust Synchronous Reference Frame Phase-Looked Loop (PLL) with Feed-Forward Frequency Estimation

Michael Ruderman , Elia Brescia , Paolo Roberto Massenio , Giuseppe Leonardo Cascella , David Naso This is my paper
classification eess.SY cs.SY
keywords phase-locked loopSRF-PLLfrequency estimationfeedforward controlsymmetrical optimumPMSM drivephase synchronizationpower-invariant normalization
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper tries to establish that a conventional synchronous-reference-frame PLL can be made substantially more accurate during frequency ramps and load transients by injecting an online, model-free frequency estimate as a feedforward signal, without increasing the loop order or adding filters. It shows that the absolute mean phase error drops roughly 6.9-fold during a frequency ramp (from 0.9205 rad to 0.1327 rad) and improves by roughly 35–40% under torque-varying operation at 50 rad/s and 150 rad/s. The authors also propose a power-invariant normalization that makes the loop insensitive to input amplitude changes, plus a symmetrical-optimum PI tuning rule with a single design parameter. Experimental evidence comes from three-phase currents of inverters-fed PMSM drives under realistic disturbances: PWM notching, subharmonics, load steps, and a 0.05 s data loss.

Core claim

The central claim is that a robust, one-parameter frequency estimator, running in parallel on the three phase currents and averaged, can supply the SRF-PLL with an accurate feedforward frequency. This converts a frequency ramp into an equivalent step input, eliminating steady-state frequency error that a type-2 PLL would otherwise exhibit. The paper demonstrates experimentally that this feed-forward extension (SRF-PLL-FF) locks phase faster and with lower error than the identical SRF-PLL without feedforward, while preserving the loop's phase margin and robustness. The design also uses a power-invariant normalization of the three-phase signal so the loop gain no longer depends on input amplit

What carries the argument

The load-bearing mechanism is the feedforward path built around a second-order robust frequency estimator: for each phase n, the estimator dynamics are (η̇₁, η̇₂)ᵀ = (0,1; -ω̃², -2ω̃)(η₁,η₂)ᵀ + (0, 2ω̃)ᵀ Zₙ, ν = η₂, with the adaptation law ˙ω̃ = -γ sign(η₁)(Zₙ - ν). The averaged estimate ω̃ = (ω̃ₐ + ω̃_b + ω̃_c)/3 is injected into the PLL's frequency path, effectively replacing the nominal frequency entry. This shifts the loop's equivalent input from a ramp (κ/s²) to a step (const/s), so the final-value theorem gives zero steady-state frequency error. The secondary machinery is the power-invariant normalization factor N = √(Zₐ² + Z_b² + Z_c²) that keeps the normalized amplitude at √(2/3) reg

Load-bearing premise

The frequency estimator converges on the actual PWM-notched, subharmonic-tainted, occasionally missing current signals quickly enough that the feedforward term stays accurate during transients; the convergence proof is deferred to an earlier paper, not re-established here.

What would settle it

Run the estimator alone on the same experimental data starting from an initial frequency near the 3rd harmonic (e.g., 3ω) and observe whether it converges to the fundamental rather than latching onto the subharmonic, or introduce a data-loss interval longer than 0.05 s and measure whether the phase error grows beyond a few periods instead of recovering. If the estimator locks onto a subharmonic or the loop loses lock after longer dropouts, the claimed robustness and the feedforward advantage collapse.

Watch this falsifier. Get emailed when new claim-graph text bears on it.

If this is right

  • Frequency ramps can be tracked with zero steady-state error without raising the PLL loop order, so phase margin and noise immunity are preserved.
  • The loop becomes insensitive to input amplitude variations, making the PI tuning valid across a wide range of signal magnitudes.
  • The entire scheme is real-time executable with no extra filters or pre/post-processing; only one additional tuning parameter (γ) is needed for the estimator.
  • Phase lock is maintained through temporary data loss and PWM notching, recovering within a few periods.
  • The same architecture should transfer to other three-phase harmonic signals, such as grid voltages, where ramp-like frequency events occur during disturbances.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • A natural generalization is to apply the same feedforward-estimator concept to other PLL variants (e.g., SOGI-based or DSOGI-PLL), potentially reducing their tuning complexity while improving ramp tracking.
  • Because the frequency estimator is model-free and exponentially convergent (per Theorem 1), one might formally analyze the combined loop as a slow-fast system and derive a guaranteed phase-lock margin; the paper does not perform this stability analysis.
  • The large ramp-error reduction suggests the scheme could enable sensorless PMSM drives to use faster acceleration ramps than feedback-only PLLs allow, a direct but unexplored operational benefit.
  • A concrete testable extension is to evaluate the same SRF-PLL-FF on a grid-connected converter under unbalanced or harmonically distorted voltages; the paper's subharmonic-robustness claims imply it should hold, but experimental evidence here is limited to motor currents.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

3 major / 4 minor

Summary. The paper proposes an SRF-PLL augmented by a feed-forward frequency estimator previously introduced by the first author in [18]. The feedback loop is tuned by the symmetrical optimum method, and a normalization scheme is used to make the loop gain independent of signal amplitude. The feed-forward signal is the averaged output of three parallel robust frequency estimators operating on the three phase currents. The main experimental claim is that the SRF-PLL-FF achieves substantially lower phase errors than the same SRF-PLL without feed-forward in torque-varying and frequency-ramp PMSM drive tests.

Significance. If the claimed improvement is real, the contribution is practically significant: a one-parameter, model-free frequency estimator that removes ramp-induced phase error without raising the loop order would be a useful addition to SRF-PLL design. The paper also demonstrates a real-time implementation on inverter-fed PMSM currents, which is a relevant and nontrivial testbed. The strength of the paper is its experimental grounding; the main weakness is that the comparison baseline is not the standard SRF-PLL with a nominal feed-forward term, so the incremental value of the adaptive estimator over a constant feed-forward is not established.

major comments (3)
  1. [Section IV-B, Table I, Fig. 9] The central comparison uses an SRF-PLL with the feed-forward input set to zero (Fig. 9 caption: 'SRF-PLL without feed-forward i.e. ˜ω = 0'). The paper itself notes in Section II-A that knowledge of a nominal ˜ω drives the PLL closer to the operating point and facilitates the regulator. The standard SRF-PLL of [14] includes a nominal feed-forward. Thus Table I compares 'any feed-forward' versus 'no feed-forward', not the proposed adaptive estimator versus a constant nominal feed-forward. A control condition with a constant ˜ω (e.g., 50 rad/s and 150 rad/s in the corresponding tests, and a mid-ramp value in the ramp test) is needed to support the claim that the robust estimator provides clear superiority.
  2. [Section III, Theorem 1] Theorem 1 states asymptotic convergence of the estimator under an unbiased harmonic plus band-limited zero-mean noise, with proof deferred to [18]. The experimental conditions include PWM notch distortion, persistent subharmonics, and a 0.05 s data loss that are not covered by the theorem's assumptions. The paper claims robustness to subharmonics (Section III, final paragraph) but reports no supporting results. The feed-forward benefit depends entirely on the estimator converging in these conditions; the paper should either provide a supporting analysis or explicitly limit the theoretical claim and rely on repeated experimental validation.
  3. [Section IV-C, Tables I and II] The error metrics are computed from single experimental records, and the paper acknowledges that the phase-wrap induced peaks make EΣ and EME only relative values. Without repeated trials or confidence intervals, the magnitudes of the improvements (e.g., 0.0584 vs. 0.0376 at 50 rad/s) may not be statistically robust. Adding multiple runs or a sensitivity analysis would strengthen the conclusion, particularly because the claim of 'clear superiority' is the paper's main result.
minor comments (4)
  1. [Title and Abstract] 'Phase-Looked Loop' should be 'Phase-Locked Loop' in the title and abstract.
  2. [Equation (10)] The factor '√3/2 κ/ki' is ambiguous; from the derivation with U=√(2/3), the coefficient should be √(3/2)κ/ki. Please disambiguate and correct if needed.
  3. [Section III, last paragraph] Typo: 'It it also worth noting' should be 'It is also worth noting'.
  4. [Tables and text] The abbreviation 'PLL-FF' is used in the tables but the text defines 'SRF-PLL-FF'; please make the notation consistent.

Circularity Check

0 steps flagged

No significant circularity: the main claim is an experimental ablation with independent error metrics, not a derivation that reduces to its inputs.

full rationale

The paper's central claim is that SRF-PLL-FF outperforms SRF-PLL, supported by Table I and Table II computed from recorded PMSM current data under identical conditions. No parameter of the estimator or PI controller is fitted to the reported error metrics: kp and ki follow from the symmetrical optimum design (Section II-C), and the estimator gain γ is fixed in advance. The feed-forward estimator is imported from the first author's prior work [18], and Theorem 1's proof is deferred to that reference; this is a self-citation, but the paper independently demonstrates convergence on experimental data (Figs. 3 and 8), so the claimed advantage does not reduce to the citation. The baseline is run with ω~ = 0 (Fig. 9 caption), so the comparison shows any-feedforward vs. none rather than adaptive vs. constant feedforward; this is a concern about the strength and external benchmarking of the comparison, not a circular reduction of the claimed result to its inputs. The paper also acknowledges that EΣ and EME are relative values due to 2π resets (Section IV-C), and the subharmonic-robustness claim is asserted via [18] without new experimental evidence; these are support/validity gaps, not circularity. No load-bearing step in the derivation chain is definitionally equivalent to its inputs, and no fitted parameter is renamed as a prediction.

Axiom & Free-Parameter Ledger

3 free parameters · 5 axioms · 0 invented entities

The paper introduces no new physical entities. The robust estimator is a prior algorithm from [18], and the design uses standard control-theory assumptions adapted to the SRF-PLL context. The main external reliance is the unproved convergence theorem of the estimator.

free parameters (3)
  • gamma (frequency estimator gain) = 4000
    Single tuning parameter of the estimator, assigned by the authors and used in all experiments; no sensitivity analysis is reported.
  • alpha (symmetrical optimum factor) = 40 (implied by kp=122, ki=306, tau=0.00025 s)
    Design parameter of the symmetrical optimum tuning rule, chosen to set the crossover frequency and phase margin.
  • omega_tilde(0) (initial frequency estimate) = 120 rad/s for load-varying experiments; 90 rad/s for the ramp experiment
    Initial condition recommended by [18] to be above the true frequency; hand-chosen per experiment.
axioms (5)
  • domain assumption Small-signal linearization sin(Delta_theta) ~= Delta_theta for the SRF-PLL loop
    The open-loop transfer function (7), the final-value analysis (10), and the symmetrical optimum tuning all rely on the PLL operating near Delta_theta~=0 (Section II-B).
  • domain assumption Sampling delay is a first-order lag with time constant tau << kp/ki
    This standard approximation is used to derive H(s) and the tuning rule; the actual implementation may have additional computation delays not modeled.
  • domain assumption Input signal is an unbiased harmonic plus band-limited zero-mean noise, and frequency variations are slow relative to estimator convergence
    The robust estimator in [18] is cited for this class of signals (Section III, eq. 16); the paper acknowledges notching and subharmonics are present but does not prove convergence under those distortions.
  • domain assumption Theorem 1 from [18] (exponential convergence of the frequency estimator)
    The proof is deferred entirely to [18]; the paper's feed-forward benefit depends on this theorem being true for the experimental signals.
  • domain assumption The encoder-based phase angle is a valid reference for the true electrical phase
    The authors note it is 'not strictly identical' under transients (Section IV), yet it is used as ground truth for the phase error metrics.

pith-pipeline@v1.3.0-alltime-deepseek · 11488 in / 11050 out tokens · 181978 ms · 2026-08-04T15:26:52.602411+00:00 · methodology

0 comments
read the original abstract

Synchronous reference frame phase-locked loop (SRF-PLL) techniques are widely used for interfacing and control applications in the power systems and energy conversion at large. Since a PLL system synchronizes its output with an exogenous harmonic signal, often 3-phases voltage or current, the locking of the frequency and phase angle depends on the performance of the feedback loop with at least two integrator terms, and on the distortions of the measured input quantities. For the conventional SRF-PLL with a proportional-integral (PI) control in feedback, we are providing a robust design which maximizes the phase margin and uses the normalization scheme for yielding the loop insensitive to the input amplitude variations. The main improvement in the transient behavior and also in tracking of frequency ramps is achieved by using the robust feed-forward frequency estimator, which is model-free and suitable for the noisy and time-varying harmonic signals. The proposed feed-forward-feedback SRF-PLL scheme is experimentally evaluated on the 3-phases harmonic currents from a standard PMSM drive with the varying angular speeds and loads. Both, the tracked angular frequency and locked phase angle are assessed as performance indicators of the proposed SRF-PLL with feedforwarding.

Figures

Figures reproduced from arXiv: 2509.19111 by David Naso, Elia Brescia, Giuseppe Leonardo Cascella, Michael Ruderman, Paolo Roberto Massenio.

Figure 1
Figure 1. Figure 1: Block diagram of conventional SRF-PLL. Assuming the three-phase input signals1 Z{a,b,c} = Z   cos θ  cos θ − 2π 3  cos θ − 4π 3    , (1) with Z to be the magnitude (which can be often unknown or time-varying) of the three-phase electric signals, the abc￾dq nonlinear transfer block provides the standard Clarke’s and Park’s transformations [19], [20]. Following to that, the output quantities… view at source ↗
Figure 2
Figure 2. Figure 2: Open-loop transfer function around crossover frequ [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: (a) measured and estimated (starting from [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Frequency tracking excerpts during the convergence [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Experimental setup (laboratory view). The assigned estimator gain parameter is γ = 4000 for both, the torque-varying operation (cf. section IV-A) and frequency￾ramp operation (cf. section IV-B). The PI gains are designed to be the same setting in both experiments by means of the symmetrical optimum approach (cf. section II-C): kp = 122 and ki = 306. The sampling time is τ = 0.00025 sec, and no additional l… view at source ↗
Figure 7
Figure 7. Figure 7: Comparison of the measurement and SRF-PLL-FF estima [PITH_FULL_IMAGE:figures/full_fig_p006_7.png] view at source ↗
Figure 6
Figure 6. Figure 6: Comparison of the measurement and SRF-PLL-FF estima [PITH_FULL_IMAGE:figures/full_fig_p006_6.png] view at source ↗
Figure 8
Figure 8. Figure 8: (a) measured and estimated (starting from [PITH_FULL_IMAGE:figures/full_fig_p006_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Comparison of the measurement and PLL estimation dur [PITH_FULL_IMAGE:figures/full_fig_p007_9.png] view at source ↗

discussion (0)

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