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arxiv: 2510.19783 · v4 · submitted 2025-10-22 · 💻 cs.NI · cs.PF

On the Power Saving in High-Speed Ethernet-based Networks for Supercomputers and Data Centers

Miguel S\'anchez de La Rosa , Francisco J. and\'ujar , Jesus Escudero-Sahuquillo , Jos\'e L. S\'anchez , Francisco J. Alfaro-Cort\'es This is my paper

Pith reviewed 2026-05-18 04:28 UTC · model grok-4.3

classification 💻 cs.NI cs.PF
keywords Energy Efficient Ethernetpower savingPerfBoundHPC networksdata centerssupercomputersdynamic power-downpost-exascale networks
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0 comments X

The pith

An enhanced PerfBound mechanism reduces energy use in high-speed Ethernet networks for supercomputers and data centers with minimal or no performance penalty.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper examines power-saving techniques for HPC and datacenter networks based on the Energy Efficient Ethernet protocol and its flexibility for conventional or upcoming interconnects. It identifies weaknesses in dynamic power-down methods and proposes enhancements to PerfBound that deliver greater energy reduction. Simulations using traffic patterns from HPC and machine learning applications measure the effects on both performance and energy consumption. A sympathetic reader would care because large-scale systems face rising sustainability and cost pressures, and techniques that cut power without slowing computations could ease those pressures in post-exascale deployments.

Core claim

The central claim is that dynamic power-down mechanisms contain identifiable weaknesses that an enhancement to the PerfBound technique can address, yielding improved energy reduction with minimal or no performance penalty; this is shown through modeling in a simulation framework and experiments on traffic generated by selected HPC and machine learning applications, while targeting emerging post-exascale networks.

What carries the argument

The PerfBound power-saving mechanism, analyzed for weaknesses in dynamic power-down and then extended to improve the energy-performance trade-off.

If this is right

  • The enhanced technique applies across conventional Ethernet and upcoming versions such as BXI and Omnipath.
  • Energy consumption varies with the specific traffic patterns of HPC and machine learning applications.
  • System and network energy use can be lowered while keeping performance degradation at minimal or zero levels.
  • The approach supports analysis of post-exascale network scales.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If the simulation results hold on physical hardware, data-center operators could adopt the enhancement to lower operational energy costs.
  • Similar analysis of dynamic power-down weaknesses might extend to other high-speed interconnect families beyond Ethernet derivatives.
  • Broader workload testing could reveal whether the energy gains remain stable under mixed or bursty traffic not covered in the selected patterns.

Load-bearing premise

The simulation framework and selected traffic patterns from HPC and machine learning applications accurately represent real hardware behavior and workloads in supercomputers and data centers.

What would settle it

A hardware measurement on real high-speed Ethernet interconnects running the same workloads that shows substantially larger performance penalties than the simulations predict would disprove the minimal-penalty claim.

Figures

Figures reproduced from arXiv: 2510.19783 by Francisco J. Alfaro-Cort\'es, Francisco J. and\'ujar, Jesus Escudero-Sahuquillo, Jos\'e L. S\'anchez, Miguel S\'anchez de La Rosa.

Figure 1
Figure 1. Figure 1: Inactivity histogram for a port when executing different applications. [PITH_FULL_IMAGE:figures/full_fig_p005_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Port switching between Wake and Sleep states due to packet transmissions. This figure shows that the link state starts at Sleep, and at a certain time, it starts transitioning to its Wake state. After tw, the link is active and able to send several packets. Once the link has finished the transmission, it returns to Sleep. Note that every packet burst happening while the link is in Sleep state spends tw wai… view at source ↗
Figure 3
Figure 3. Figure 3: Visual representation of Deep Sleep and Fast Wake power states. The different link power levels are a basis for implementing LPI, included in the EEE standard [11]. This has led to several proposals tailored for HPC so that end-to-end latency is not greatly increased by the overhead of turning links on [25, 4]. The idea for HPC environments is to employ Fast Wake so that latency is not greatly affected by … view at source ↗
Figure 4
Figure 4. Figure 4: Diagram of LPI using PDT. ready to send them. Meanwhile, for inactivity periods that are on the order of seconds, the overhead on latency for state transitioning is irrelevant. A tP DT value of microseconds is also insignificant compared to the inactivity period in terms of power saving. The issue, as we have mentioned, is the intermittent nature of network activity during communication. When the tP DT is … view at source ↗
Figure 5
Figure 5. Figure 5: Port state synchronization between two switch ports. [PITH_FULL_IMAGE:figures/full_fig_p015_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Network efficiency for the LAMMPS application. [PITH_FULL_IMAGE:figures/full_fig_p023_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Impact of different tPDT values for LAMMPS. savings with smaller tP DT values. Finally, note that with fixed tP DT values larger than 1ms there are barely energy savings. 4.1.2. Results using PerfBound and PerfBoundCorrect As shown in Figure 8a, we can see the overhead on the application when using PerfBound and PerfBoundCorrect techniques. Just like with a fixed tP DT , the difference between Fast Wake an… view at source ↗
Figure 8
Figure 8. Figure 8: Impact of PerfBound and PerfBoundCorrect on the LAMMPS trace. [PITH_FULL_IMAGE:figures/full_fig_p025_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Network efficiency for the PATMOS application. [PITH_FULL_IMAGE:figures/full_fig_p027_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Impact of different tPDT values for PATMOS. Regarding the total energy consumed, leaving links operational after transmission is potentially beneficial for future outgoing packets at the cost of more energy consumed over time. Figure 10b shows the effect each PDT value has on the total energy consumed by the system. As is the case with execution time, the ports experience few transitions because of the tr… view at source ↗
Figure 11
Figure 11. Figure 11: Impact of PerfBound and PerfBoundCorrect on the PATMOS trace. [PITH_FULL_IMAGE:figures/full_fig_p028_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Network efficiency for the MLWF application. [PITH_FULL_IMAGE:figures/full_fig_p029_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: Impact of different tPDT values for MLWF. we increase tP DT values, the latency starts dropping to lower, more acceptable values. The results for energy saving for this application are shown in Figure 13c. As shown, tP DT values of 10 and 100 µs increase the energy saved in both power-saving states. Lower values provide marginal power-saving values or even increased energy usage in that proportion. Indeed… view at source ↗
Figure 14
Figure 14. Figure 14: Impact of PerfBound and PerfBoundCorrect on the MLWF trace. [PITH_FULL_IMAGE:figures/full_fig_p031_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: Network efficiency for the ALEXNET application. [PITH_FULL_IMAGE:figures/full_fig_p032_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: Impact of different tPDT values for ALEXNET. Circular Hist. Regular Hist. Self-clearing Hist. 1     1 1   "!        !        !        !         !      !     (a) Execution time increase. 1       [PITH_FULL_IMAGE:figures/full_fig_p033_16.png] view at source ↗
Figure 17
Figure 17. Figure 17: Impact of PerfBound and PerfBoundCorrect on the ALEXNET trace. [PITH_FULL_IMAGE:figures/full_fig_p033_17.png] view at source ↗
read the original abstract

The increase in computation and storage has led to a significant growth in the scale of systems powering applications and services, raising concerns about sustainability and operational costs. In this paper, we explore power-saving techniques in high-performance computing (HPC) and datacenter networks, and their relation with performance degradation. From this premise, we propose leveraging Energy Efficient Ethernet (EEE) protocol, with the flexibility to extend to conventional Ethernet or upcoming Ethernet-derived interconnect versions of BXI and Omnipath. We analyze the PerfBound power-saving mechanism, identifying possible improvements and modeling it into a simulation framework. Through different experiments, we examine its impact on performance and determine the most appropriate interconnect. We also study traffic patterns generated by selected HPC and machine learning applications to evaluate the behavior of power-saving techniques. From these experiments, we provide an analysis of how applications affect system and network energy consumption. Based on this, we disclose the weakness of dynamic power-down mechanisms and propose an approach that improves energy reduction with minimal or no performance penalty. To the best of our knowledge, this work presents the first thorough analysis of PerfBound and an enhancement to the technique, while also targeting emerging post-exascale networks.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper claims that dynamic power-down mechanisms in Energy Efficient Ethernet (EEE) for high-speed interconnects in supercomputers and data centers have weaknesses that can be addressed by analyzing and enhancing the PerfBound technique. Using a simulation framework, the authors evaluate its performance and energy impacts on traffic patterns from selected HPC and machine learning applications, identify limitations of existing approaches, and propose an enhancement that achieves greater energy reduction with minimal or no performance penalty. They position this as the first thorough analysis of PerfBound and extend the scope to emerging post-exascale networks based on Ethernet derivatives such as BXI and OmniPath.

Significance. If the simulation-based findings hold under real hardware conditions, the work could inform practical energy-saving strategies for large-scale networks where interconnect power is a growing fraction of total consumption. The emphasis on application-specific traffic analysis and post-exascale relevance addresses a timely sustainability concern, though the absence of hardware anchoring limits immediate deployability.

major comments (2)
  1. [Simulation framework] Simulation framework section: The central claim that the proposed PerfBound enhancement yields improved energy reduction with minimal/no performance penalty rests on simulation results, yet the manuscript provides no hardware measurements or analytical bounds to validate EEE state transition latencies, wake-up overheads, or per-port power draw against real devices. This leaves the generalization to supercomputers and data centers unsupported.
  2. [Experiments and traffic analysis] Traffic patterns and experiments section: The selected HPC and ML application traces are described as representative, but the paper offers no quantitative analysis or proof that they reproduce production-level burstiness, synchronization effects, or idle-period distributions at scale. Without this, the observed performance-energy trade-offs cannot be shown to generalize.
minor comments (2)
  1. [Abstract] Abstract and introduction: The claim of presenting the 'first thorough analysis' of PerfBound would benefit from explicit comparison to prior EEE studies in the related-work section to substantiate novelty.
  2. [Throughout] Notation: Consistent use of abbreviations (e.g., EEE, PerfBound) and clear definition of simulation parameters (e.g., idle thresholds) would improve readability.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback on our manuscript. We address each major comment below and have revised the paper to improve clarity on simulation assumptions and traffic pattern justification.

read point-by-point responses

  1. Referee: [Simulation framework] Simulation framework section: The central claim that the proposed PerfBound enhancement yields improved energy reduction with minimal/no performance penalty rests on simulation results, yet the manuscript provides no hardware measurements or analytical bounds to validate EEE state transition latencies, wake-up overheads, or per-port power draw against real devices. This leaves the generalization to supercomputers and data centers unsupported.

    Authors: We agree that hardware measurements would strengthen the validation. The simulation parameters are drawn from IEEE 802.3az specifications, vendor datasheets, and prior EEE studies; we have now added explicit citations and derived analytical bounds for transition latencies in the revised Simulation Framework section. We have also inserted a Limitations subsection that qualifies the generalization to production systems and notes the simulation-based nature of the results. Direct hardware experiments are outside the current scope but are identified as future work. revision: partial

  2. Referee: [Experiments and traffic analysis] Traffic patterns and experiments section: The selected HPC and ML application traces are described as representative, but the paper offers no quantitative analysis or proof that they reproduce production-level burstiness, synchronization effects, or idle-period distributions at scale. Without this, the observed performance-energy trade-offs cannot be shown to generalize.

    Authors: The traces originate from publicly documented HPC and ML workloads with citations in the manuscript. In the revision we have added quantitative statistics, including idle-period histograms, burst-size distributions, and comparisons to metrics from prior large-scale network studies. While these additions provide stronger justification, a complete proof of representativeness for every production environment would require proprietary traces beyond our access; we therefore frame the results as indicative for the studied application classes rather than universally generalizable. revision: yes

Circularity Check

0 steps flagged

No circularity: claims rest on independent simulation experiments

full rationale

The paper conducts a simulation-based study of PerfBound and EEE power-saving mechanisms using traffic patterns from selected HPC and ML applications. No mathematical derivations, equations, or predictions appear that reduce by construction to fitted parameters, self-definitions, or self-citation chains. The proposed enhancement is evaluated directly through experiments in the described framework, with conclusions drawn from observed performance and energy impacts rather than any self-referential logic. This structure is self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Based on the abstract alone, no explicit free parameters, axioms, or invented entities are identifiable. The approach builds on the existing EEE protocol and PerfBound mechanism without introducing new postulated entities.

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Reference graph

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