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arxiv: 2511.02901 · v2 · submitted 2025-11-04 · 🪐 quant-ph

Zero-Noise Extrapolation via Cyclic Permutations of Quantum Circuit Layouts

Zahar Sayapin , Daniil Rabinovich , Nikita Korolev , Kirill Lakhmanskiy This is my paper

Pith reviewed 2026-05-18 00:48 UTC · model grok-4.3

classification 🪐 quant-ph
keywords zero-noise extrapolationquantum error mitigationNISQ devicescircuit layout permutationquantum circuit mappingIBM quantum hardware
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The pith

Cyclic permutations of circuit layouts let zero-noise extrapolation use only O(n) executions while cutting typical errors by an order of magnitude.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents CLP-ZNE, which averages expectation values over cyclic permutations of the qubit layout on the hardware graph and then extrapolates the average to the zero-noise limit. The method turns the natural variation in gate error rates across different placements into a set of effective noise strengths that can be treated as a continuous scaling parameter. For one-dimensional connectivity this requires only O(n) distinct layouts; for general connectivity the number stays at most O(n squared). Benchmarks on noise models of the IBM Torino processor show that the approach reduces typical errors in twelve-qubit circuits by roughly a factor of ten and beats standard unitary-folding zero-noise extrapolation.

Core claim

By executing the same circuit on a small number of cyclically shifted layouts and averaging the measured expectation values, one obtains data points at distinct effective noise levels whose linear or polynomial extrapolation reaches the zero-noise value; the non-uniformity of real-device gate errors supplies the required spread in noise strengths without artificial folding.

What carries the argument

Cyclic layout permutations that map the logical circuit onto successive rotations of the physical qubit chain or graph, thereby sampling different effective noise realizations while keeping the logical connectivity fixed.

If this is right

  • For linear-connectivity circuits the overhead stays linear in qubit number instead of quadratic or higher.
  • The method works under both depolarizing and T1/T2 relaxation channels that match current hardware.
  • Averaging over the cyclic shifts already supplies the noise-scaling axis, removing the need for additional unitary folding layers.
  • The same permutation set can be reused across many different circuits that share the same connectivity pattern.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Hardware graphs whose error rates vary smoothly along cycles may yield even tighter extrapolations than the tested Torino model.
  • Combining cyclic permutations with existing symmetry-based mitigations could further reduce the number of shots required.
  • The approach suggests that non-uniform error maps, usually viewed as a drawback, can be systematically converted into a resource for extrapolation.

Load-bearing premise

The noise levels realized by the different cyclic permutations are diverse enough to be treated as samples of a continuous scaling parameter suitable for extrapolation.

What would settle it

Run the same twelve-qubit circuit on actual IBM Torino hardware, compute the CLP-ZNE extrapolated value, and check whether it lies closer to a high-fidelity reference (obtained by classical simulation or by a much deeper circuit) than the raw noisy value or the standard ZNE value.

Figures

Figures reproduced from arXiv: 2511.02901 by Daniil Rabinovich, Kirill Lakhmanskiy, Nikita Korolev, Zahar Sayapin.

Figure 1
Figure 1. Figure 1: FIG. 1 [PITH_FULL_IMAGE:figures/full_fig_p005_1.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. A typical example of CLP-ZNE for one of the in [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2. The distributions of errors before and after the mit [PITH_FULL_IMAGE:figures/full_fig_p006_2.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4. CLP-ZNE realization for rescaled amplitude damping [PITH_FULL_IMAGE:figures/full_fig_p007_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5. Noisy and mitigated energies obtained for different [PITH_FULL_IMAGE:figures/full_fig_p007_5.png] view at source ↗
read the original abstract

Increasing the utility of currently available Noisy Intermediate-Scale Quantum (NISQ) devices requires developing efficient methods to mitigate hardware errors. In this work we propose a novel Cyclic Layout Permutations based Zero Noise Extrapolation (CLP-ZNE) protocol for such a task. The method leverages the inherent non-uniformity of gate errors in NISQ hardware to extrapolate the expectation value, averaged over cyclic circuit layout permutations, to the level of zero noise. In contrast to the previous layout permutation based approaches, for $n$ qubit circuit CLP-ZNE requires execution of only $O(n)$ and at most $O(n^2)$ different circuit layouts for circuits of one-dimensional and arbitrary connectivity, respectively. When benchmarked against noise channels modeling the IBM Torino quantum computer, the method reduces a typical error in expectation values of $n=12$ qubit circuits by an order of magnitude, outperforming standard unitary folding ZNE. By demonstrating the ability to mitigate noise of real hardware specifications, including both depolarizing and $T_1/T_2$ relaxation processes, these results give evidence for the applicability of CLP-ZNE to present-day NISQ processors.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper proposes Cyclic Layout Permutations based Zero-Noise Extrapolation (CLP-ZNE), which exploits non-uniform gate errors on NISQ hardware by averaging expectation values over O(n) cyclic permutations for 1D connectivity (or O(n^2) for arbitrary) and extrapolating the result to zero noise. Benchmarks against depolarizing plus T1/T2 noise models for the IBM Torino device report an order-of-magnitude error reduction for n=12 qubit circuits relative to standard unitary folding ZNE.

Significance. If the extrapolation procedure is robust, the method offers a low-overhead ZNE variant that avoids artificial noise scaling and instead samples natural hardware inhomogeneities, potentially lowering the execution cost for error mitigation on near-term devices. The inclusion of realistic relaxation processes in the model adds practical relevance, though the absence of real-hardware runs limits immediate claims of applicability.

major comments (2)
  1. [§4] §4 (Numerical results): The order-of-magnitude error reduction for n=12 circuits is reported without specifying the number of cyclic layouts used, the range of effective noise strengths obtained, the polynomial degree or fitting function employed for extrapolation, or error bars on the zero-noise estimate. These details are load-bearing for validating that the discrete permutation-induced variations function as a usable continuous scaling axis.
  2. [§3] §3 (CLP-ZNE protocol): The assumption that expectation values averaged over cyclic permutations can be extrapolated to zero noise by treating layout-induced error-rate variations as samples along a single effective noise-strength parameter is not accompanied by explicit checks for monotonicity, sufficient span, or absence of clustering/non-monotonicity under the IBM Torino noise model. This directly affects whether the reported improvement over unitary folding is general or benchmark-specific.
minor comments (2)
  1. [Abstract] The abstract states that the method 'leverages the inherent non-uniformity of gate errors' but does not define how the effective noise strength is quantified from each permutation; an explicit formula relating layout choice to the scaling parameter would improve clarity.
  2. [Figures] Figure captions and axis labels in the benchmark plots should explicitly state the number of shots, the exact noise-model parameters, and the number of permutations per data point to allow reproduction.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for their careful reading and constructive comments on our manuscript. We address the major comments point by point below and will revise the manuscript to incorporate additional details and validation where appropriate.

read point-by-point responses

  1. Referee: [§4] §4 (Numerical results): The order-of-magnitude error reduction for n=12 circuits is reported without specifying the number of cyclic layouts used, the range of effective noise strengths obtained, the polynomial degree or fitting function employed for extrapolation, or error bars on the zero-noise estimate. These details are load-bearing for validating that the discrete permutation-induced variations function as a usable continuous scaling axis.

    Authors: We agree that these implementation details are necessary for full reproducibility and to substantiate the scaling axis. In the revised manuscript we will explicitly report that 12 cyclic layouts were used for the n=12 1D-connectivity benchmarks, provide the observed range of effective noise strengths induced by the permutations, state that linear extrapolation was employed, and include error bars on the zero-noise estimates obtained via repeated sampling. These additions will directly address the concern that the discrete variations constitute a usable continuous axis. revision: yes

  2. Referee: [§3] §3 (CLP-ZNE protocol): The assumption that expectation values averaged over cyclic permutations can be extrapolated to zero noise by treating layout-induced error-rate variations as samples along a single effective noise-strength parameter is not accompanied by explicit checks for monotonicity, sufficient span, or absence of clustering/non-monotonicity under the IBM Torino noise model. This directly affects whether the reported improvement over unitary folding is general or benchmark-specific.

    Authors: We acknowledge that explicit verification strengthens the claim. In the revision we will add supplementary plots and quantitative checks (under the same IBM Torino noise model) demonstrating that the expectation values vary monotonically with the effective noise strength, span a sufficient interval, and exhibit no clustering or non-monotonicity. These checks will support that the observed order-of-magnitude improvement is not an artifact of the specific benchmark but follows from the protocol's design. revision: yes

Circularity Check

0 steps flagged

CLP-ZNE derivation is self-contained; no reductions to inputs by construction.

full rationale

The paper introduces CLP-ZNE as a protocol that samples expectation values over O(n) or O(n^2) cyclic layout permutations to obtain discrete effective noise levels arising from hardware non-uniformity, then performs standard polynomial or similar extrapolation to the zero-noise limit. This procedure is benchmarked directly against external noise models (depolarizing plus T1/T2 for IBM Torino) for n=12 circuits, demonstrating order-of-magnitude error reduction versus unitary folding ZNE. No equation equates the extrapolated value to a fitted parameter defined from the identical data set, no uniqueness theorem is imported via self-citation, and no ansatz is smuggled through prior work by the same authors. The central performance claim therefore rests on empirical comparison to independent hardware noise specifications rather than internal definitional equivalence.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The central claim rests on the assumption that cyclic layout changes produce sufficiently independent effective noise strengths for reliable extrapolation; no free parameters or new entities are introduced in the abstract.

axioms (1)
  • domain assumption Gate errors exhibit inherent non-uniformity across different physical layouts on NISQ hardware
    This non-uniformity is invoked to justify that cyclic permutations sample distinct noise levels usable for extrapolation.

pith-pipeline@v0.9.0 · 5746 in / 1334 out tokens · 32707 ms · 2026-05-18T00:48:20.030866+00:00 · methodology

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