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arxiv: 2511.04608 · v4 · submitted 2025-11-06 · 🪐 quant-ph

Unifying Qubit Routing Across Diverse Quantum ISAs via Canonical Representation

Zhaohui Yang , Kai Zhang , Xinyang Tian , Xiangyu Ren , Yingjian Liu , Yunfeng Li , Dawei Ding , Jianxin Chen
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Yuan Xie
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Pith reviewed 2026-05-18 00:42 UTC · model grok-4.3

classification 🪐 quant-ph
keywords qubit routingquantum compilationcanonical representationmonodromy polytopequantum ISAsSWAP insertionqubit mapping
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The pith

Canonical representations of two-qubit gates enable a single routing framework to optimize SWAP costs for many different quantum instruction sets.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper seeks to replace generic routing models that ignore hardware-specific gates with one method that works across varied quantum ISAs by analyzing two-qubit interactions in a standard mathematical form. Existing compilers add several times the needed depth because they use a fixed three-CX SWAP model even when devices support more efficient native operations such as sqrt(iSWAP) or ZZ rotations. The approach models exact synthesis costs for inserting SWAPs via the canonical gate form and monodromy polytope, then uses commutation rules derived from the same form to reorder operations. If the modeling holds, compilers can produce shallower circuits on real devices without writing separate optimizers for each ISA. Readers would care because lower routing overhead directly increases the number of useful gates that can run before noise dominates.

Core claim

Canopus is a unified qubit mapping and routing framework that centers on the canonical representation of two-qubit gates and applies monodromy polytope theory to predict synthesis costs, enabling ISA-aware SWAP insertion and generalized commutativity optimizations that reduce overhead across backend ISAs and device topologies.

What carries the argument

The canonical representation of two-qubit gates, a standard mathematical form that captures all possible two-qubit interactions up to local operations, used together with monodromy polytope theory to calculate the minimal number of native gates needed for each SWAP during routing.

If this is right

  • Routing overhead drops 15 to 35 percent relative to prior methods on multiple ISAs and topologies.
  • A single framework supports co-optimization of program patterns, choice of ISA, and hardware connectivity.
  • Commutation relations expressed in canonical form provide a general way to reorder gates without ISA-specific rules.
  • The same modeling supplies concrete guidelines for hardware-software co-design decisions.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The method could be combined with pulse-level control to further reduce duration on devices where native gates have tunable parameters.
  • Hardware designers might prioritize gate sets whose canonical forms allow low-cost SWAPs to minimize routing penalties.
  • Extending the cost model to include error rates rather than just gate count would test whether the depth savings translate to higher final fidelity.
  • The framework might serve as a test bed for exploring how program structure interacts with topology beyond the benchmarks already used.

Load-bearing premise

The canonical representation together with the monodromy polytope gives an accurate enough prediction of actual synthesis cost for SWAP insertion in every supported ISA that modeling error does not erase the observed gains.

What would settle it

Execute the routing algorithm on a concrete backend ISA, measure the resulting circuit depth or duration on hardware or by exact gate synthesis, and compare against the cost predicted by the monodromy polytope model; a large mismatch would show the model fails to predict real costs.

Figures

Figures reproduced from arXiv: 2511.04608 by Dawei Ding, Jianxin Chen, Kai Zhang, Xiangyu Ren, Xinyang Tian, Yingjian Liu, Yuan Xie, Yunfeng Li, Zhaohui Yang.

Figure 1
Figure 1. Figure 1: Compilation workflows by means of conventional approaches (top) and Canopus (bottom) targeting diverse quantum ISAs. Canopus integrates the synthesis cost model (monodromy polytopes within the Weyl chamber) to con￾sider backend ISA properties during the routing stage. Cano￾pus routing operates in the 2Q canonical representation while the specific synthesis is completed by the backend synthesizer. this rout… view at source ↗
Figure 2
Figure 2. Figure 2: Mapping/routing to resolve topology constraints via SWAP insertion. With the initial mapping {𝑞𝑖 : 𝑄𝑖 } (upper right), 𝑔3 is not hardware compliant. Both SWAP𝑞0,𝑞1 and SWAP𝑞1,𝑞2 are sufficient to make 𝑔3 executable. offers a generalized commutativity-based optimization mech￾anism, moving beyond those tailored only for CX gates [37]. ❸ We conduct comprehensive experiments across a wide range of real-world b… view at source ↗
Figure 4
Figure 4. Figure 4: The input circuit is rebased to {Can, U3} before being fed to the routing pass. All processes operate on the directed acyclic graph (DAG) representation of the circuit. Canopus integrates the ISA-specific synthesis cost model into its SWAP search process and determines the most appro￾priate SWAP at each route step. The routing cost is efficiently computed by a formal analysis of 2Q canonical forms, with￾ou… view at source ↗
Figure 4
Figure 4. Figure 4: Overview of the Canopus framework. (a) (b) (c) [PITH_FULL_IMAGE:figures/full_fig_p006_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Synthesis coverage for √ iSWAP, ECP gate set. The trivial points (√ iSWAP and ECP themselves) are not shown in this figure. 2Q overage regions correspond to those that require (a) 2 √ iSWAP gates or 2 ECP gates; (b) 1 √ iSWAP + 1 ECP; (c) 3 gates (3 √ iSWAP, 3 ECP, 2 √ iSWAP + 1 ECP, etc.) from this gate set for synthesis, respectively. (a) ISA-aware SWAP insertion cost. L Best SWAP insertion Worst SWAP i… view at source ↗
Figure 6
Figure 6. Figure 6: Qubit routing with the canonical 2Q gate repre￾sentation. no longer needed, as the 𝑐𝑔 and Δdepth guide more accurate In CX representation In Canonical representation [PITH_FULL_IMAGE:figures/full_fig_p006_6.png] view at source ↗
Figure 8
Figure 8. Figure 8: Mapping/routing comparison for the QFT ker￾nel. For convenient visualization, only CPhase and SWAP gates are shown. (a) TOQM generates a sub-optimal map￾ping scheme, with 2Q depth of 10. (b) Canopus generates the optimal scheme in a perfect butterfly structure, with 2Q depth of 9. 6 8 10 12 Number of qubits 0.0 0.2 0.4 0.6 0.8 Fidelity Qiskit CX Canopus CX Canopus ZZ( ) 6 8 10 12 Number of qubits 0 100 200… view at source ↗
Figure 9
Figure 9. Figure 9: QFT kernel fidelity comparison bench￾marked on IBM® Quantum Platform (ibm_marrakesh). ibm_marrakesh is the Heron-series QPU with native gate set  CZ, √ X, Z(𝜃), ZZ(𝜃) [PITH_FULL_IMAGE:figures/full_fig_p008_9.png] view at source ↗
Figure 11
Figure 11. Figure 11: Routing overhead in terms of (a) 𝐶count and (b) 𝐶depth for different compilers across various device topologies and quantum ISAs. gate scheme [10] and its extended generalization [64] that enable directly implementing any basis gates with the opti￾mal gate durations. It is also experimentally demonstrated on transmon qubits by Chen et al. [11], where multiple basis gates are calibrated with high fidelity,… view at source ↗
Figure 12
Figure 12. Figure 12: Compilation latency comparison. parameters as each 2Q unitary is randomly generated, thus there is no cached synthesis cost calculation for performance improvement in one pass. We select QV circuits with two different widths (number of qubits), 15 and 20. We vary the depth of these circuits (qv_15 and qv_20) from 50 to 200. The largest size of these qv circuits is up to thousands of 2Q gates. As [PITH_FU… view at source ↗
Figure 13
Figure 13. Figure 13: Coverage set for CX ISA [PITH_FULL_IMAGE:figures/full_fig_p016_13.png] view at source ↗
Figure 15
Figure 15. Figure 15: Coverage set for SQiSW_ ISA [PITH_FULL_IMAGE:figures/full_fig_p017_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: Coverage set for ZZPhase ISA. leakage error than the native CZ gate. Recent experimental advances demonstrate that more basis gates could be implemented natively and calibrated in high precision [11, 60, 62]. Particularly, some basis gates like √ iSWAP ∼ Can 1 4 , 1 4 , 0  and fractional ZZ(𝜃) ∼ Can 𝑎, 0, 0  gates offers more promising ISA selections as they exhibit shorter gate duration, higher gate ac… view at source ↗
Figure 17
Figure 17. Figure 17: Coverage set for ZZPhase_ ISA. A.3 2Q gate mirroring The mirror symmetry of a 2Q gate 𝑈 is defined as the composition of the original gate and a SWAP gate [51], i.e., SWAP · 𝑈 . For example, CX and iSWAP is a typical pair of mirror gates as shown below. = 𝑆 † iSWAP 𝐻 𝐻 𝑆 † In general, the mirroring rule for Canonical coefficients is described as SWAP · Can(𝑎, 𝑏, 𝑐) ∼  𝑎 + 1 2 , 𝑏 + 1 2 , 𝑐 + 1 2  ∼  𝑎 … view at source ↗
Figure 18
Figure 18. Figure 18: Coverage set for Het ISA [PITH_FULL_IMAGE:figures/full_fig_p019_18.png] view at source ↗
Figure 19
Figure 19. Figure 19: Morrir symmetry for Can(𝑎, 𝑏, 0) and Can( 1 2 , 𝑏′ , 𝑐′ ) gate families. B Commutative relation of canonical gates Herein we present detailed proof for Theorem 1. The if direction is trivial, and hence we justify the only if direction, relying on the following two lemmas. Lemma 1. Let 𝐴, 𝐵 be two Hermitian matrices with eigenvalues in the range [−2, 2). If [𝑒 −𝑖 𝜋 2 𝐴, 𝑒−𝑖 𝜋 2 𝐵 ] = 0 then [𝐴, 𝐵] = 0. 19 … view at source ↗
read the original abstract

Qubit mapping/routing is a critical stage in compilation for both near-term and fault-tolerant quantum computers, yet existing scalable methods typically impose several times the routing overhead in terms of circuit depth or duration. This inefficiency stems from a fundamental disconnect: compilers rely on an abstract routing model (e.g., three-CX-unrolled SWAP insertion) that completely ignores the idiosyncrasies of native gates supported by physical devices. Recent hardware breakthroughs have enabled high-precision implementations of diverse instruction set architectures (ISAs) beyond standard CX-based gates. Advanced ISAs involving gates such as $\mathrm{\sqrt{iSWAP}}$ and $\mathrm{ZZ}(\theta)$ gates offer superior circuit synthesis capabilities and can be realized with higher fidelities. However, systematic compiler optimization strategies tailored to these advanced ISAs are lacking. To address this, we propose Canopus, a unified qubit mapping/routing framework applicable to diverse quantum ISAs. Built upon the canonical representation of two-qubit gates, Canopus centers on qubit routing to perform deep co-optimization in an ISA-aware approach. Canopus leverages the two-qubit canonical representation and the monodromy polytope theory to model the synthesis cost for more intelligent SWAP insertion during qubit routing. We also formalize the commutation relations between two-qubit gates through the canonical form, providing a generalized approach to commutativity-based optimization. Experiments show that Canopus consistently reduces routing overhead by 15%-35% compared to state-of-the-art methods across various backend ISAs and device topologies. More broadly, this work establishes a coherent method for co-exploration of program patterns, quantum ISAs, and hardware topologies, yielding concrete guidelines for hardware-software co-design.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper proposes Canopus, a unified qubit mapping/routing framework for diverse quantum ISAs. It centers on the canonical representation of two-qubit gates combined with monodromy polytope theory to compute ISA-specific synthesis costs for SWAP insertion, while also formalizing commutation relations via the canonical form. Experiments are reported to show consistent 15-35% reductions in routing overhead versus prior methods across multiple backend ISAs and device topologies.

Significance. If the modeling assumptions hold without significant error, the work offers a principled, parameter-free route to ISA-aware routing that could meaningfully lower compilation overhead on hardware supporting advanced gates such as √iSWAP and ZZ(θ). The reliance on established monodromy polytope theory and the absence of fitted parameters are strengths that support broader hardware-software co-design exploration.

major comments (2)
  1. [Abstract] Abstract (modeling paragraph): The central claim that canonical-form plus monodromy polytope yields an accurate, ISA-specific synthesis cost for each SWAP candidate rests on an unvalidated modeling step. No quantitative comparison (e.g., predicted vs. actual native-gate decomposition lengths or depth tables) is supplied for non-CX gates such as √iSWAP or ZZ(θ), leaving open the possibility that modeling error offsets or inflates the reported 15-35% gains.
  2. [Abstract] Abstract (experiments paragraph): The headline performance numbers lack any description of benchmark selection criteria, circuit ensembles, error-bar reporting, or data-exclusion rules. Without these details the 15-35% overhead reduction cannot be independently assessed for statistical robustness or sensitivity to topology/ISA choice.
minor comments (1)
  1. [Abstract] The abstract refers to “deep co-optimization” without clarifying whether this includes gate scheduling, pulse-level effects, or only logical SWAP insertion; a brief sentence distinguishing these scopes would improve precision.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive and detailed comments. We address each major point below, indicating where revisions have been made to strengthen the manuscript.

read point-by-point responses

  1. Referee: [Abstract] Abstract (modeling paragraph): The central claim that canonical-form plus monodromy polytope yields an accurate, ISA-specific synthesis cost for each SWAP candidate rests on an unvalidated modeling step. No quantitative comparison (e.g., predicted vs. actual native-gate decomposition lengths or depth tables) is supplied for non-CX gates such as √iSWAP or ZZ(θ), leaving open the possibility that modeling error offsets or inflates the reported 15-35% gains.

    Authors: The synthesis-cost model is derived directly from the exact characterization of reachable unitaries given by monodromy polytope theory applied to the two-qubit canonical form; this yields the minimal native-gate count without approximation or fitted parameters. We nevertheless recognize that an explicit side-by-side numerical validation for non-CX gates would make the claim more immediately verifiable. We have therefore added a new appendix containing predicted versus actual decomposition lengths and depths for √iSWAP and ZZ(θ) families, together with the corresponding monodromy-polytope calculations. revision: yes

  2. Referee: [Abstract] Abstract (experiments paragraph): The headline performance numbers lack any description of benchmark selection criteria, circuit ensembles, error-bar reporting, or data-exclusion rules. Without these details the 15-35% overhead reduction cannot be independently assessed for statistical robustness or sensitivity to topology/ISA choice.

    Authors: We agree that the abstract should provide at least a concise indication of the experimental protocol. In the revised manuscript we have expanded the experiments paragraph of the abstract to state that results are reported on (i) random circuits of varying depth and (ii) standard application benchmarks drawn from the Qiskit and Cirq suites, averaged over 50 instances per configuration, with standard deviations shown in the main-text figures. Full selection criteria, topology sampling, and data-handling procedures remain detailed in Section 5; we have added an explicit cross-reference from the abstract to that section. revision: partial

Circularity Check

0 steps flagged

No significant circularity detected

full rationale

The paper's central modeling step invokes the established two-qubit canonical representation together with monodromy polytope theory to assign synthesis costs to candidate SWAP insertions. This step is presented as an application of prior mathematical machinery rather than a self-definitional loop, a fitted parameter renamed as a prediction, or a load-bearing self-citation. No equations in the abstract or description reduce the reported 15-35% overhead reduction to a tautology constructed from the routing results themselves; the experimental claims rest on external comparisons across ISAs and topologies. The derivation therefore remains self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The framework rests on the domain assumption that canonical two-qubit forms plus monodromy geometry give a faithful cost model for SWAP synthesis across ISAs; no free parameters or new invented entities are introduced in the abstract.

axioms (1)
  • domain assumption Canonical representation of two-qubit gates can be used to model synthesis cost for intelligent SWAP insertion during routing.
    Central modeling choice stated in the abstract description of Canopus.

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