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arxiv: 2511.10249 · v3 · submitted 2025-11-13 · 💻 cs.NI

P4-TAS: P4-Based Time-Aware Shaper for Time-Sensitive Networking

Fabian Ihle , Moritz Fl\"uchter , Michael Menth This is my paper

Pith reviewed 2026-05-17 22:12 UTC · model grok-4.3

classification 💻 cs.NI
keywords Time-Sensitive NetworkingTime-Aware ShaperP4Programmable ASICDeterministic NetworkingTSNInternal DelayGate Control
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The pith

P4-TAS implements time-aware shaping on a programmable ASIC using internal control frames and measures 86 ns accumulated delay.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper establishes that the time-aware shaper can be realized in P4 on the Intel Tofino 2 ASIC for the first time by generating a continuous stream of internal control frames that open and close egress queues at scheduled intervals. This approach protects time-sensitive traffic while supporting per-stream filtering, PTP synchronization, and an MPLS/TSN translation layer at up to 400 Gb/s line rates. The authors also isolate three sources of internal delay and report a worst-case total of 86 ns between time slices, along with a new measurement method and gate switching intervals to reduce slice overlap. A sympathetic reader cares because this moves deterministic queue control from closed commercial hardware into reconfigurable switches, giving network operators direct knowledge of timing behavior inside the device.

Core claim

The central claim is that a novel mechanism of continuous internally generated control frames enables periodic time-triggered queue state updates on a P4-programmable ASIC, providing the first TAS implementation on such hardware. The work quantifies three internal delay sources that affect gate transition precision and demonstrates a worst-case accumulated delay of 86 ns. It further supplies an external measurement methodology for time slice accuracy and introduces gate switching intervals to mitigate overlap between consecutive slices while supporting DetNet integration via MPLS/TSN translation.

What carries the argument

The continuous stream of internally generated control frames that perform time-triggered updates to egress queue states without variable latency or interference with data-plane traffic.

If this is right

  • TSN-compliant time-based shaping becomes feasible on programmable ASICs at 400 Gb/s per port.
  • Designers obtain quantified internal delays that allow more accurate TAS gate schedule configuration.
  • MPLS/TSN translation supports application of time-based shaping at the boundary between TSN and DetNet domains.
  • Gate switching intervals reduce overlap between consecutive time slices.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Programmable switches could replace fixed-function TSN hardware in networks that need frequent schedule changes.
  • The external measurement method for slice accuracy could be applied to other traffic shapers or priority mechanisms.
  • Low internal delays open the possibility of tighter end-to-end latency bounds in mixed TSN-DetNet deployments.

Load-bearing premise

Internally generated control frames can update queue states at precise intervals without introducing variable latency or interfering with data-plane traffic at 400 Gb/s.

What would settle it

A direct measurement of queue update latency that varies by more than a few nanoseconds or an accumulated internal delay exceeding 86 ns at full line rate would contradict the reported timing precision.

Figures

Figures reproduced from arXiv: 2511.10249 by Fabian Ihle, Michael Menth, Moritz Fl\"uchter.

Figure 1
Figure 1. Figure 1: The Time-Aware Shaper (TAS) shapes scheduled traffic by gating [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: The pipeline of the TNA. The TNA consists of an ingress block and an egress block, each with a programmable parser, control blocks, and a deparser. After processing frames in the ingress control block, frames are queued in the traffic manager component of the TNA. This component is configurable but not pro￾grammable [19]. Control blocks in a P4 program define the logic of the algorithm. They leverage metad… view at source ↗
Figure 3
Figure 3. Figure 3: Concept of MATs in P4. In a MAT, selected packet header fields and metadata form a composite key. Each packet is matched in the MAT according to the selected key fields. On a match in the table, an associated [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Placement of P4-TAS in a DetNet environment using a TSN sub-layer. [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: The tGCL of the TAS is modeled as a MAT. The generated TAS [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Overview of the P4-TAS pipeline. egress block while drops must occur in the ingress block. Thus, recirculation is necessary, adding a known constant delay. For P4-TAS, we ported the implementation of P4-PSFP from Intel Tofino™ to Tofino™ 2 where the larger pipeline allows the GCL position to be computed in one pass. We also removed the optional maximum frame size filter, eliminating the need for recirculat… view at source ↗
Figure 7
Figure 7. Figure 7: Example of range-to-ternary mappings for three different ranges [ [PITH_FULL_IMAGE:figures/full_fig_p007_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Packet generator deviation δˆ TG for different configured periods. Although these deviations are small, they can impact the periodicity computation. If a period-completion frame arrives late, the computed relative position within the current GCL cycle may exceed the period h, which would index an out￾of-period entry. To ensure that all frames are assigned to a valid tGCL entry, P4-TAS clamps any calculated… view at source ↗
Figure 9
Figure 9. Figure 9: Measurement of the queue opening delay in the data plane of P4-TAS. [PITH_FULL_IMAGE:figures/full_fig_p009_9.png] view at source ↗
Figure 11
Figure 11. Figure 11: Measured TAS control traffic delay. The measured median is ˆδcontrol,M = 9 ns, with only a few frames showing a slightly higher delay of up to 12 ns. Thus, transmission gate states can be updated only every 9 ns. Because frames are generated sequentially in batches of eight, updates for different priority queues are offset sequentially by 9 ns and cannot occur simultaneously. Further, this means that the … view at source ↗
Figure 10
Figure 10. Figure 10: CCDF of measured queue opening delay. Most delays are below ˆδqueue = 11 ns with a tail extending up to 63 ns and a mean of µ( ˆδqueue) = 14.63 ns. These results reveal small but measurable internal delays. In particular, the queue opening delay can cause transitional behavior at tGCL boundaries where frames from the previous entry may still be transmitted briefly after the next entry has started. The imp… view at source ↗
Figure 12
Figure 12. Figure 12: Worst case effect of the internal delay ∆internal on the tGCL entry duration. The internal delay ∆internal may reduce or extend the dura￾tion of a tGCL entry [PITH_FULL_IMAGE:figures/full_fig_p010_12.png] view at source ↗
Figure 14
Figure 14. Figure 14: Measurement procedure in the dedicated P4 program of the third [PITH_FULL_IMAGE:figures/full_fig_p010_14.png] view at source ↗
Figure 16
Figure 16. Figure 16: Normalized histogram of the deviation between configured and [PITH_FULL_IMAGE:figures/full_fig_p011_16.png] view at source ↗
Figure 15
Figure 15. Figure 15: Gate switching intervals (GSIs) mitigate transitional behavior of [PITH_FULL_IMAGE:figures/full_fig_p011_15.png] view at source ↗
read the original abstract

Time-sensitive networking (TSN) is a set of IEEE standards that extends Ethernet with real-time capabilities. Among its mechanisms, the time-aware shaper (TAS) periodically opens and closes egress queues to protect scheduled traffic from lower-priority flows, ensuring low latency and bounded delay. Deterministic networking (DetNet), standardized by the IETF, provides similar guarantees at Layer 3 and can leverage TSN mechanisms such as the TAS. Commercially available TSN-capable switches implement TAS in hardware but rarely disclose internal delays in the TAS mechanism itself. Such delays directly affect scheduling precision, yet information about them is largely unavailable to system designers. In this work, we present P4-TAS, a P4-based implementation of the TAS on the Intel Tofino 2 switching ASIC that additionally supports per-stream filtering and policing (PSFP) and PTP time synchronization. First, we design a novel mechanism for periodic queue control that uses a continuous stream of internally generated control frames for time-triggered queue state updates. To the best of our knowledge, this enables TAS on a P4-programmable ASIC for the first time. P4-TAS additionally provides an MPLS/TSN translation layer that enables TSN time-based shaping to be applied at the boundary between TSN and DetNet domains, supporting line rates up to 400 Gb/s per port. Second, we identify and quantify three sources of internal delay that affect the precision of TAS gate transitions, providing transparency that enables more accurate TAS configuration. Our evaluation demonstrates a worst-case accumulated internal delay of 86 ns between time slices, which is well below values reported for commercial switches. Third, we propose a measurement methodology to externally measure TAS time slice accuracy, and introduce gate switching intervals (GSIs) to mitigate overlap between consecutive time slices.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript presents P4-TAS, a P4-based implementation of the Time-Aware Shaper (TAS) on the Intel Tofino 2 ASIC for TSN, with support for PSFP and PTP. It introduces a novel mechanism using continuous internally generated control frames for time-triggered queue state updates, claims this enables TAS on a P4-programmable ASIC for the first time, quantifies three sources of internal delay, reports a worst-case accumulated internal delay of 86 ns, supports line rates up to 400 Gb/s, includes an MPLS/TSN translation layer for DetNet boundaries, and proposes a measurement methodology plus gate switching intervals (GSIs) to mitigate time-slice overlaps.

Significance. If the timing and mechanism claims hold, the work is significant for providing the first documented open TAS implementation on a programmable ASIC, along with quantified internal delays that commercial switches do not disclose. This transparency, combined with 400 Gb/s support and cross-domain translation, could improve scheduling precision in TSN/DetNet systems. The external measurement methodology and GSI concept are practical additions that enhance reproducibility and usability for system designers.

major comments (2)
  1. [Mechanism for periodic queue control] Mechanism for periodic queue control (design section): The novel approach of using a continuous stream of internally generated control frames to update queue states at precise intervals is load-bearing for both the 'first TAS on P4 ASIC' claim and the reported 86 ns precision advantage. The manuscript should provide explicit analysis or measurements demonstrating that control-frame generation (via recirculation or equivalent) introduces no variable latency, pipeline contention, register jitter, or self-queuing interference under 400 Gb/s mixed TSN/DetNet traffic. The existing quantification of three internal delay sources does not appear to cover these effects.
  2. [Evaluation] Evaluation section reporting the 86 ns worst-case accumulated internal delay: The central timing result requires a fuller description of the experimental setup, including hardware configuration details, traffic patterns and loads used during testing, isolation of the three delay sources, and any error bars or repeated measurements. Without this, the robustness of the delay bound and its comparison to commercial switches cannot be fully assessed.
minor comments (2)
  1. [Abstract] The abstract could briefly note the high-level approach taken for the MPLS/TSN translation layer to give readers an immediate sense of its scope.
  2. Figures illustrating control-frame flow or time-slice measurements would benefit from explicit scale bars or annotations highlighting the 86 ns bound and GSI intervals for clarity.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive review and for recognizing the potential impact of P4-TAS in providing an open implementation with quantified delays for TSN/DetNet systems. We address each major comment below and plan to incorporate revisions to strengthen the manuscript.

read point-by-point responses

  1. Referee: Mechanism for periodic queue control (design section): The novel approach of using a continuous stream of internally generated control frames to update queue states at precise intervals is load-bearing for both the 'first TAS on P4 ASIC' claim and the reported 86 ns precision advantage. The manuscript should provide explicit analysis or measurements demonstrating that control-frame generation (via recirculation or equivalent) introduces no variable latency, pipeline contention, register jitter, or self-queuing interference under 400 Gb/s mixed TSN/DetNet traffic. The existing quantification of three internal delay sources does not appear to cover these effects.

    Authors: We appreciate the referee's emphasis on validating the control-frame mechanism's determinism. Our design ensures that control frames are generated via a dedicated recirculation port with a fixed cycle time, independent of data traffic. The three quantified delay sources encompass the recirculation path latency. Nevertheless, to explicitly demonstrate the absence of variable latency, contention, or jitter under full 400 Gb/s load with mixed traffic, we will add targeted measurements and analysis in the revised manuscript. This will include latency histograms and interference tests. revision: yes

  2. Referee: Evaluation section reporting the 86 ns worst-case accumulated internal delay: The central timing result requires a fuller description of the experimental setup, including hardware configuration details, traffic patterns and loads used during testing, isolation of the three delay sources, and any error bars or repeated measurements. Without this, the robustness of the delay bound and its comparison to commercial switches cannot be fully assessed.

    Authors: We agree that additional details are required to substantiate the 86 ns worst-case delay result. In the revised evaluation section, we will provide: (1) complete hardware setup including the specific Tofino 2 switch model, port speeds, and synchronization method; (2) traffic generation details, including packet sizes, rates, and the composition of TSN and DetNet flows at 400 Gb/s; (3) methodology for isolating each of the three delay sources; and (4) results from multiple measurement runs with statistical measures such as mean, standard deviation, and maximum observed values. These additions will enable a more rigorous assessment of the bound and comparisons to commercial implementations. revision: yes

Circularity Check

0 steps flagged

No circularity: implementation and external measurement are self-contained

full rationale

The paper describes a P4-based TAS implementation on Tofino 2 using internally generated control frames for queue updates, identifies three internal delay sources, and reports an externally measured worst-case accumulated delay of 86 ns. No equations, fitted parameters, or derivations are present that reduce the reported delay or the 'first TAS on P4 ASIC' claim to a self-defined quantity by construction. The evaluation relies on direct measurement and comparison to commercial-switch literature rather than any self-citation chain, ansatz smuggling, or renaming of known results. The central claims rest on the described mechanism and empirical results, which are independent of the inputs.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The implementation rests on standard IEEE TSN and PTP specifications plus the P4 programming model; no free parameters are fitted to data and no new physical entities are postulated.

axioms (1)
  • domain assumption IEEE 802.1Qbv time-aware shaper semantics and PTP time synchronization hold on the target ASIC.
    Invoked when the design assumes periodic gate control and precise time references.

pith-pipeline@v0.9.0 · 5641 in / 1195 out tokens · 31330 ms · 2026-05-17T22:12:36.292969+00:00 · methodology

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Forward citations

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