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REVIEW 5 major objections 5 minor 1 cited by

A Linear Implementation of an Analog Resonate-and-Fire Neuron

T0 review · 5 major / 5 minor · reviewed 2026-08-03 · deepseek-v4-flash

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Pith's one-line read An analog circuit in 22nm FDSOI implements a resonate-and-fire neuron with linear state coupling, matching state-space-model dynamics while consuming as little as 1.6 nW.

desk verdict Simulation-only RAF circuit with a plausible topology and a genuine forward SHD test, but the headline 500 kHz tuning range is contradicted by the reported bias/power curve. read the letter →

arxiv 2511.12297 v1 pith:IXJY3L4R submitted 2025-11-15 eess.SP

Angqi Liu , Filippo Moro , Sebastian Billaudelle , Melika Payvand This is my paper
classification eess.SP
keywords resonate-and-fireneuronstate-spacemodelsanalogcircuitdesign22nmFDSOItransconductanceamplifierswitched-capacitorkeywordspottingneuromorphichardware
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims that an analog circuit in 22 nm FDSOI can implement a resonate-and-fire (RAF) neuron whose two internal states are coupled linearly, exactly matching the continuous-time dynamics of modern state-space models. The design uses a bulk-driven transconductance amplifier for the off-diagonal coupling and switched-capacitor leakage for the diagonal decay, giving independent, wide-range tuning of resonance frequency (100 Hz–500 kHz) and time constants (~1–500 ms) while consuming only 1.6–132.6 nW. The authors further show, through a hardware-calibrated behavioral simulation, that the circuit's non-idealities (nonlinearity, mismatch, noise) reduce keyword-spotting accuracy on the SHD benchmark by only about 1.5%, from 93.4% to 91.9%. The result matters because it points to a path where energy-efficient spiking neurons retain the expressivity of linear oscillatory recurrences used in machine learning.

What carries the argument

The central mechanism is the pairing of (1) a bulk-driven, cascoded transconductance amplifier (TCA), which acts as a linear voltage-to-current converter for the cross-coupling terms ωu,v in the state matrix, and (2) switched-capacitor (SC) leakage circuits, which implement the diagonal decay terms τu,v with an equivalent conductance proportional to f_SC·C_fringe/C. The TCA's linearity over the full 0–0.8 V swing preserves the linear SSM form, while the cascode output stage raises output impedance to suppress parasitic leakage. The resonance frequency is set by the TCA bias current (ω≈gm), and the time constants are set independently by two switching frequencies f_SC.

What would settle it

Fabricate the 22 nm FDSOI circuit and measure the resonance frequency vs bias current, time constant vs switched-capacitor clock frequency, and power vs bias current, then run the same SHD keyword-spotting task with the measured device characteristics. A frequency or time-constant deviation beyond the simulated Monte Carlo spread, or a hardware-calibrated accuracy drop greater than 1.5%, would refute the paper's central claim of simulation-faithful linear RAF dynamics.

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Extended reading notes

Core claim

The paper demonstrates that a linear RAF neuron can be built without the nonlinear coupling of earlier analog implementations. In the proposed 22 nm FDSOI circuit, two state voltages u and v on capacitors are cross-coupled by bulk-driven cascoded transconductance amplifiers, so the circuit follows Eq. (1) with ωu,v ≈ gm and τu,v set by the switched-capacitor clock frequency. Transient simulations show a damped oscillation with the expected 90° phase shift, a linear dependence of resonance frequency on bias current, and time constants tunable over two decades. A compact hardware-calibrated model, built from Monte Carlo and transient-noise simulation, captures the main non-idealities, and SHD

Load-bearing premise

Every quantitative claim — the 100 Hz–500 kHz range, the 1.6–132.6 nW power, the ~1.5% accuracy drop — comes from circuit simulation, and the paper never reports a fabricated chip; if real-device effects such as switch charge injection, bulk leakage, or layout parasitics differ from the models, these numbers shift.

Editorial extensions

If this is right

  • Analog spiking neurons can implement the same linear recurrences as state-space models, giving neuromorphic hardware access to SSM-style temporal processing.
  • The independent tuning of resonance frequency and time constant covers 100 Hz–500 kHz and ~1–500 ms, spanning speech, biomedical, and robotic control timescales.
  • Because power scales almost linearly with bias current (16.5 nW/nA), the circuit offers a predictable frequency-versus-energy trade-off for edge deployments.
  • Hardware-aware co-design, where the circuit's simulated non-idealities are embedded in the system model, yields only a 1.5% accuracy drop on keyword spotting, suggesting non-ideal analog circuits can still be used directly in ML pipelines.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the design is fabricated, the most likely failure points are charge injection in the switched-capacitor switches and leakage at the lowest clock frequencies; measuring the time-constant floor at f_SC ≈ 100 Hz would test the simulated 500 ms ceiling.
  • The linear coupling suggests this circuit could be extended to complex-valued or higher-dimensional oscillatory SSM states, since the TCA pair naturally implements a rotation matrix on capacitor voltages.
  • The co-design methodology is only as good as the simulation models; a silicon validation with the same SHD task would be the decisive test of the claimed 1.5% accuracy drop.
  • Because the output comparator consumes additional power not counted in the 1.6–132.6 nW range, chip-level power budgets could be higher than reported.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

5 major / 5 minor

Summary. The manuscript presents a 22-nm FDSOI analog circuit that implements a resonate-and-fire (RAF) neuron with linear state coupling. The two state variables are voltages on capacitors C1 and C2, coupled through bulk-driven cascoded transconductance amplifiers and decayed through programmable switched-capacitor paths; the design is intended to reproduce the continuous-time SSM/RAF dynamics of Eq. (1). Based on Spectre, Monte-Carlo, and transient-noise simulations, the authors report transconductance linearity from 0 to 0.8 V, resonance-frequency tuning by the bias current Ibias, SC time-constant programmability, a power range of 1.6–132.6 nW, an area of 6524 μm², and a frequency range of 100 Hz–500 kHz (Table I). They then map four levels of circuit non-ideality into an SHD keyword-spotting benchmark, reporting an accuracy drop from 93.4% to 91.9%. The paper concludes that RAF neurons are robust, energy-efficient computational primitives for neuromorphic hardware. All quantitative performance figures are simulation-based; no measured silicon data are presented.

Significance. The central idea—linearly coupling the two RAF state variables with TCAs and using SC leakage for the decay terms—is a reasonable and timely way to make analog RAF dynamics compatible with modern SSM-style linear recurrences. The co-design evaluation is a strength: the SHD simulation uses a fixed model from [3], 8-bit weight quantization, and circuit-extracted constraints/mismatch/noise added progressively, so the 1.5-point accuracy drop is a genuine forward test rather than a fitted result. If the quantitative claims were backed by silicon measurements, the paper would be a solid contribution. As it stands, however, the headline tuning range is internally inconsistent with the displayed simulations and power envelope, the quoted power excludes the comparator, and the PVT-resilience claim in the abstract is not backed by any shown PVT analysis. These issues must be corrected before the claims are publication-ready.

major comments (5)
  1. [§III-D / Table I / Figs. 5, 7] The reported upper resonance frequency of 500 kHz is not supported by the presented data. Fig. 5 shows resonance frequency only up to about 8 kHz for Ibias in the 0–8 nA range, and Fig. 7's empirical slope of 16.5 nW/nA together with the 132.6 nW maximum pins the maximum bias to about 8 nA at 0.8 V. Since the resonance frequency scales linearly with gm(Ibias), reaching 500 kHz at the same C1/C2 would require roughly 60× larger gm and hence a bias current/power far above the stated envelope. The paper does not disclose C1/C2 values or a high-current tuning curve. Table I's '100 Hz–500 kHz' claim is therefore an unsupported extrapolation or an unstated operating point, and the 'broad dynamic range' conclusion rests directly on it.
  2. [§III-D / Table I] The 1.6–132.6 nW power range is not the full neuron power. The text states that 'the output comparator is not included in this estimate,' but Table I reports 'Power consumption' without that qualification. A comparator is an integral part of the spiking neuron (the Heaviside output in Eq. (1)), and it may contribute a significant dynamic component. To support the energy-efficiency claim, either include the comparator (or a realistic estimate of its power) in the reported total, or explicitly relabel the figure as core-analog (TCA + SC) power.
  3. [§III-A–III-D / §IV / §V] No fabricated chip or measured data are presented. All quantitative performance claims—linearity (Fig. 3), dynamics (Fig. 4), tuning (Figs. 5–6), power (Fig. 7), area (Table I), and the hardware-calibrated model (Fig. 8)—come from Spectre, Monte-Carlo, and transient-noise simulations. The manuscript nowhere states that the results are pre-silicon; the abstract and conclusions use unqualified 'built in 22 nm FDSOI' and 'robust.' Real switched-capacitor charge injection, clock feedthrough, substrate/bulk leakage, layout parasitics, and silicon mismatch are not included, so the reported PPA numbers are provisional. At minimum, add an explicit limitation statement and qualify the headline claims as simulation-based.
  4. [Abstract / §I / §III] The abstract and introduction claim that the design is evaluated for 'resilience to Process, Voltage, and Temperature (PVT) variations,' but no PVT simulation results appear in the manuscript. The only variability data are Monte-Carlo and transient-noise characterizations of mismatch and noise (Figs. 3, 5–6 and Section IV). Either add the missing PVT analysis or remove the PVT-resilience claim from the abstract and conclusions.
  5. [§II Eq. (1) / §IV] The authors state that 'we do not include a reset mechanism in the model,' and Eq. (1) gives z(t)=H(v(t)−Θ). Without reset, the 'spike' output is a level output whose event semantics differ from standard spiking RAF implementations. Since the system-level simulation is built on a spiking codebase [3], the paper should specify how spikes are generated in the SHD setting and whether a reset is applied in the benchmark; otherwise the comparison to ideal SNN accuracy and the claim of sparse event-based communication are not transparent.
minor comments (5)
  1. [§IV] Typo: 'esulting' should be 'resulting'. Also, the 1.5% drop should be phrased as '1.5 percentage points' (93.4% to 91.9%), since the relative drop is about 1.6%.
  2. [§III-D / Fig. 7] The text says power is 'dominated by static biasing' but Fig. 7 is labeled 'Dynamic power.' Clarify the static-vs-dynamic terminology to avoid confusion.
  3. [Table I] The row 'Additional voltage regulator/current reference required' is written as 'NO/YES,' which is ambiguous. Specify whether a voltage regulator is required and what current reference is needed.
  4. [§III-A–III-B] The values of C1, C2, and the SC fringe capacitance are not reported, which makes the tuning curves in Figs. 5–6 difficult to reproduce or check. Adding these values would improve the paper.
  5. [§II Eq. (1)] The relationship between the circuit's gm1,2 and the matrix entries ωu, ωv in Eq. (1) (e.g., ω = gm/(2πC)) is not explicitly stated. Please define it for clarity.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the SHD result is a forward test with independently extracted circuit constraints.

full rationale

The paper's derivation chain is not circular in the sense defined here. The central claim is that the Fig. 1 circuit implements the linear RAF/SSM dynamics of Eq. (1). The circuit is built from TCAs and SC leakage paths, and the quantitative non-idealities (gm nonlinearity from Fig. 3, resonance-frequency dependence from Fig. 5, time-constant compression from Fig. 6, mismatch and noise from Monte Carlo/transient simulations) are extracted from circuit-level simulations and then inserted as fixed constraints into a behavioral model based on the external codebase [3]. The 93.4% to 91.9% SHD accuracy drop is not obtained by fitting any parameter to the SHD result; it is a forward evaluation of the calibrated model. Thus there is no fitted input renamed as a prediction, no equation that reduces to its input by definition, and no load-bearing self-citation. The only co-author citation ([15], Billaudelle et al.) is used to justify a design topology choice, but the paper independently characterizes that topology's linearity and includes it as an analyzed component, so the citation is not load-bearing. The skeptical observation about the 500 kHz frequency-range entry conflicting with Fig. 5 and the 132.6 nW power envelope is a correctness/consistency concern, not a circularity concern; the claimed tuning range may be unsupported or misreported, but that does not make the derivation circular. Overall, the paper is self-contained against an external benchmark (SHD), and the hardware-to-system mapping is a legitimate co-design flow rather than a circular argument.

Assumptions & free parameters 4 free parameters · 4 assumptions · 0 invented entities

No new physical entities are introduced. The ledger is dominated by circuit and simulation parameters (gm, f_SC, capacitor values, bias points) and by the anchoring assumptions of the design kit and the [3] codebase. The absence of fabricated-chip measurements means all quantitative entities are simulated model values.

free parameters (4)
  • g_m from M2/M3 input pair with I_bias = I_bias = 0.1–8 nA; gm varied in Fig. 3
    The linear transconductance, a design/simulation parameter, sets the resonance frequency ω≈g_m/C. Its linearity curve (Fig. 3) is measured in simulation and later inserted into the system model. Not a universal constant but a circuit parameter.
  • f_SC,u and f_SC,v = not disclosed vs. time constant curve
    Switching frequency sets the decay time constants τ via the SC discharge. It is tunable but the mapping τ(f_SC, I_bias) is presented only as a plot; the exact C_fringe/C1,2 values are unstated.
  • 8-bit weight quantization in SHD simulation = 8 bits
    A modeling constraint chosen for the system-level simulations; it bounds memory precision but is a free design choice, not fitted to the SHD accuracy.
  • Non-ideality levels 1–4 in behavioral model = e.g., noise std not stated
    The noise/mismatch values are obtained from MC/transient-noise simulations, but the exact injection procedures and magnitudes are not described in the text.
assumptions (4)
  • domain assumption The SHD codebase [3] correctly implements spiking-network training and the RAF equations, such that adaptation for this paper changes only the neuron dynamics.
    The system-level results (Fig. 8) build on [3] and are asserted without shipped code; this is a domain expertise/prior-implementation assumption.
  • domain assumption Voltage stored on C1/C2 maps linearly to the state variables u and v and the comparator/Heaviside threshold Θ does not require a reset mechanism.
    Assumed in Eq. (1) and circuit description, Sec. II–III; omission of reset is explicitly noted as a modeling/circuit choice.
  • domain assumption The two state capacitors are ideal (no parasitic capacitance dominates, no charge injection from switches) except where the SC leakage is purposely modeled.
    The SC model treats the switch as a periodic discharge to VCM; charge injection from the switches in 22nm FDSOI is not discussed. Standard circuit-theory idealization.
  • domain assumption In 22nm FDSOI, the bulk-driven cascoded differential pair [15] exhibits the simulated linearity and low leakage at 0.8 V supply.
    Fig. 2/Fig. 3 rely on the specific transistor model; without fabricated silicon, the simulated linearity is an assumption about model correctness.

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Cite this review

Pith. "Pith review of A Linear Implementation of an Analog Resonate-and-Fire Neuron." pith.science (2026). https://pith.science/paper/IXJY3L4R

@misc{pith2026251112297,
  author       = {Pith},
  title        = {Pith review of: A Linear Implementation of an Analog Resonate-and-Fire Neuron},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/IXJY3L4R}},
  note         = {Machine review of arXiv:2511.12297}
}
read the original abstract

Oscillatory dynamics have recently proven highly effective in machine learning (ML), particularly through State-Space-Models (SSM) that leverage structured linear recurrences for long-range temporal processing. Resonate-and-Fire neurons capture such oscillatory behavior in a spiking framework, offering strong expressivity with sparse event-based communication. While early analog RAF circuits employed nonlinear coupling and suffered from process sensitivity, modern ML practice favors linear recurrence. In this work, we introduce a resonate-and-fire (RAF) neuron, built in 22nm Fully-Depleted Silicon-on-Insulator technology, that aligns with SSM principles while retaining the efficiency of spike-based communication. We analyze its dynamics, linearity, and resilience to Process, Voltage, and Temperature variations, and evaluate its power, performance, and area trade-offs. We map the characteristics of our circuit into a system-level simulation where our RAF neuron is utilized in a keyword-spotting task, showing that its non-idealities do not hinder performance. Our results establish RAF neurons as robust, energy-efficient computational primitives for neuromorphic hardware.

Figures

Figures reproduced from arXiv: 2511.12297 by the authors.

Figure 1
Figure 1. Linear-Resonate-and-Fire block-level circuit diagram. [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 6
Figure 6. Time constant for the two states u and v as a function of the switching frequency fSC , and for different TCA bias currents Ibias. B. Switched Capacitor exponential decay The intrinsic decay terms of the RAF neuron, corresponding to the diagonal elements τu,v of the system matrix in Eq.1, are realized using SC circuits. Leveraging the low-leakage properties of FDSOI technology, the SC circuit can operate at a very l… view at source ↗
Figure 4
Figure 4. Dynamics of the coupled oscillator of Fig. 1 with [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗
Figures from the paper (3 more)
Figure 5
Figure 5. Figure 5: Resonance frequency as a function of the TCA’s bias current. [PITH_FULL_IMAGE:figures/full_fig_p003_5.png]
Figure 8
Figure 8. Figure 8: Classification accuracy on the SHD task with different levels of [PITH_FULL_IMAGE:figures/full_fig_p004_8.png]
Figure 7
Figure 7. Figure 7: Dynamic power consumption as a function of the bias current [PITH_FULL_IMAGE:figures/full_fig_p004_7.png]

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Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Adaptive-Frequency Resonate-and-Fire Neurons for Spectral Estimation of Streaming Radar Signals

    cs.NE 2026-06 unverdicted novelty 6.0 of 10

    Adaptive-frequency resonate-and-fire neurons perform sample-by-sample spectral estimation for FMCW radar, with memory scaling by number of targets rather than signal length.

Reference graph

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