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arxiv: 2511.15028 · v3 · submitted 2025-11-19 · 💻 cs.PL

Decoupling Data Layouts from Bounding Volume Hierarchies

Christophe Gyurgyik , Alexander J Root , Fredrik Kjolstad This is my paper

Pith reviewed 2026-05-17 21:19 UTC · model grok-4.3

classification 💻 cs.PL
keywords bounding volume hierarchiesdata layoutsdomain-specific languagescompilersray tracingperformance portabilityarchitecture independence
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0 comments X

The pith

Scion decouples bounding volume hierarchy data layouts from traversal algorithms via a domain-specific language and compiler.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Bounding volume hierarchies are acceleration structures whose speed depends on memory layouts that improve cache behavior, bandwidth, and vectorization. In existing systems the layout decisions remain tied to the traversal code, blocking independent tuning or reuse across programs and machines. Scion supplies a high-level language for writing layout rules alone; its compiler emits the corresponding memory arrangements without reference to any particular traversal routine. The approach reproduces many known high-performance layouts while staying free of architecture-specific assumptions. Measurements across algorithms, processors, and scenes establish that the best-performing and smallest-footprint layouts change with context, and that a hybrid layout assembled from prior techniques is Pareto-optimal in multiple settings.

Core claim

The central claim is that a domain-specific language called Scion, together with its compiler, can specify bounding volume hierarchy data layouts independently of tree traversal algorithms, express a wide range of high-performance computing layout optimizations in an architecture-agnostic manner, and through systematic design exploration identify Pareto-optimal layouts that vary by algorithm, architecture, and workload together with a novel ray-tracing layout that achieves optimality across diverse architectures and scenes.

What carries the argument

Scion, a domain-specific language and compiler that lets users describe BVH data layouts separately from traversal logic.

If this is right

  • Developers can tune data layouts and traversal algorithms separately for different contexts without rewriting either.
  • The single best layout is not universal; Pareto-optimal choices shift with algorithm, machine, and input data.
  • A new hybrid layout that merges techniques from earlier work delivers strong performance and modest memory use across many architectures and scenes.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same separation of layout specification from control logic could be applied to other hierarchical data structures used in simulation and analytics.
  • Systematic layout exploration becomes feasible once the description language is decoupled from any one traversal, potentially surfacing additional hybrid arrangements for specialized workloads.
  • Compilers for general-purpose languages might eventually adopt similar declarative layout primitives to improve data-structure performance without manual rewriting.

Load-bearing premise

That a compiler can turn high-level layout descriptions into efficient, architecture-agnostic code without adding overhead that erases the gains from the chosen layouts.

What would settle it

A side-by-side benchmark in which Scion-generated code for an otherwise identical layout runs measurably slower or uses more memory than equivalent hand-written code on the same hardware.

Figures

Figures reproduced from arXiv: 2511.15028 by Alexander J Root, Christophe Gyurgyik, Fredrik Kjolstad.

Figure 1
Figure 1. Figure 1: Visualization of bounding volume hierarchies. [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: illustrates the Scion system overview. Application developers express tree traversal algorithms against algebraic data type (ADT) specifications that define the logical structure of the tree, while performance engineers separately specify how those ADTs are physically realized using the layout language (Section 4) and build language (Section 5). The layout specification enables destructor2 specialization: … view at source ↗
Figure 4
Figure 4. Figure 4: A closest-hit ray tracing query algorithm written with respect to the logical BVH specification. [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figure 3
Figure 3. Figure 3: Syntax of the traversal language [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 5
Figure 5. Figure 5: Comparison of PBRTv4 BVH layouts for the logical [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Syntax of the layout language. To achieve the goal of combining clarity of ADTs with spe￾cialized layout performance, Scion provides a separate declar￾ative layout language (abstract syntax provided in [PITH_FULL_IMAGE:figures/full_fig_p005_6.png] view at source ↗
Figure 8
Figure 8. Figure 8: Example sub-layout diagrams. Solid arrows indicate the flow of data (either a derivation or loaded [PITH_FULL_IMAGE:figures/full_fig_p008_8.png] view at source ↗
Figure 7
Figure 7. Figure 7: Layout diagram for PBRTv4. To aid understanding of layout specifications, we intro￾duce layout diagrams that visualize how field accesses propagate through layout language constructs. These dia￾grams trace the path from the initial reference (illustrated as a shaded box) through group constructs, split primi￾tives, and indirect lookups, terminating at either stored fields (loads from memory) or derived fie… view at source ↗
Figure 9
Figure 9. Figure 9: Build specification for the PBRTv4 layout. [PITH_FULL_IMAGE:figures/full_fig_p009_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Build language syntax. 5.2.1 Local. Local primitives describe how stored (physical) fields are populated for each variant type. Build statements populate physical fields from logical values. The statement build x copies the field x directly from the logical representation to the corre￾sponding physical location in the layout specification. For example, in [PITH_FULL_IMAGE:figures/full_fig_p010_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Destructor code generation for PBRTv4 layout. [PITH_FULL_IMAGE:figures/full_fig_p012_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: BVH with DOP-14 bounding volumes [43] specified in Scion [PITH_FULL_IMAGE:figures/full_fig_p013_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: BVH for strand-based geometry with heterogeneous volumes and quantized OBBs specified in [PITH_FULL_IMAGE:figures/full_fig_p014_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: BVH for the shared slab optimization with tree-carried dependencies specified in [PITH_FULL_IMAGE:figures/full_fig_p015_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: Performance variation across scenes and architectures for [PITH_FULL_IMAGE:figures/full_fig_p017_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: Algorithm-dependent 8.2.4 Algorithm-Dependent [PITH_FULL_IMAGE:figures/full_fig_p018_16.png] view at source ↗
Figure 17
Figure 17. Figure 17: The set of (machine × scene × ray distribution) contexts where pbrt-q16 is not Pareto-optimal. Results. Among bvh2 layouts, pbrt-q16 achieves Pareto optimality in 35 of 42 evalu￾ation contexts spanning three architectures, seven scenes, and two ray distribution pat￾terns. Notably, 4 of the 7 non-dominating in￾stances (shown in [PITH_FULL_IMAGE:figures/full_fig_p018_17.png] view at source ↗
Figure 18
Figure 18. Figure 18: Closest-hit ray tracing demonstrating (left) worst- and (right) best-case comparison with Embree. [PITH_FULL_IMAGE:figures/full_fig_p019_18.png] view at source ↗
Figure 19
Figure 19. Figure 19: Normalized performance comparison against state-of-the-art libraries (higher is better). [PITH_FULL_IMAGE:figures/full_fig_p020_19.png] view at source ↗
Figure 20
Figure 20. Figure 20: C++ code generated by Scion for Closest Hit Ray Tracing with the PBRTv4 layout. We provide the unoptimized version because renaming occurs during the optimization passes, resulting in inscrutable code [PITH_FULL_IMAGE:figures/full_fig_p032_20.png] view at source ↗
read the original abstract

Bounding volume hierarchies are ubiquitous acceleration structures in graphics, scientific computing, and data analytics. Their performance depends critically on data layout choices that affect cache utilization, memory bandwidth, and vectorization -- increasingly dominant factors in modern computing. Yet, in most programming systems, these layout choices are hopelessly entangled with the traversal logic. This entanglement prevents developers from independently optimizing data layouts and algorithms across different contexts, perpetuating a false dichotomy between performance and portability. We introduce Scion, a domain-specific language and compiler for specifying the data layouts of bounding volume hierarchies independent of tree traversal algorithms. We show that Scion can express a broad spectrum of layout optimizations used in high-performance computing while remaining architecture-agnostic. We demonstrate empirically that Pareto-optimal layouts (along performance and memory footprint axes) vary across algorithms, architectures, and workload characteristics. Through systematic design exploration, we also identify a novel ray tracing layout that combines optimization techniques from prior work, achieving Pareto-optimality across diverse architectures and scenes.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript introduces Scion, a domain-specific language and compiler for specifying data layouts of bounding volume hierarchies independently of traversal algorithms. It claims that Scion can express a broad spectrum of high-performance computing layout optimizations while remaining architecture-agnostic, empirically demonstrates that Pareto-optimal layouts vary across algorithms, architectures, and workload characteristics, and identifies a novel ray-tracing layout that combines prior techniques to achieve Pareto-optimality across diverse architectures and scenes.

Significance. If the empirical results and compiler overhead claims hold, this work would meaningfully advance the state of the art by separating layout and traversal concerns that are currently entangled in graphics and scientific computing systems. The systematic design exploration and identification of a novel layout represent concrete contributions; the architecture-agnostic property, if achieved without prohibitive runtime cost, would be particularly valuable for portable high-performance code.

major comments (2)
  1. [§5.2] §5.2, performance tables: the reported speedups for Scion-generated layouts versus baseline implementations do not include a direct measurement of accessor overhead (e.g., extra indirection or missed prefetch opportunities) relative to equivalent hand-tuned code for the same layout; this measurement is load-bearing for the central claim that decoupling does not negate net performance gains.
  2. [§4.1] §4.1, language semantics: the formal description of how layout descriptors are lowered to traversal-compatible accessors does not specify preservation of cache-line packing or vectorization opportunities that hand-tuned code exploits; without this, the architecture-agnostic guarantee risks becoming a performance tax in hot paths.
minor comments (2)
  1. [Figure 3] Figure 3 caption: the legend for the novel layout is difficult to distinguish from the 'combined' baseline; a clearer visual encoding would improve readability.
  2. [§6] §6: the discussion of limitations mentions only a subset of traversal algorithms; adding a brief note on compatibility with non-recursive or GPU-specific traversals would strengthen the decoupling claim.

Simulated Author's Rebuttal

2 responses · 0 unresolved

Thank you for the detailed review. We appreciate the feedback on the performance evaluation and language semantics. We respond to each major comment below.

read point-by-point responses

  1. Referee: [§5.2] §5.2, performance tables: the reported speedups for Scion-generated layouts versus baseline implementations do not include a direct measurement of accessor overhead (e.g., extra indirection or missed prefetch opportunities) relative to equivalent hand-tuned code for the same layout; this measurement is load-bearing for the central claim that decoupling does not negate net performance gains.

    Authors: We agree that isolating the overhead introduced by the generated accessors compared to hand-tuned equivalents for the same layout would provide stronger evidence for the claim. In the revised version, we will add experiments that directly compare the performance of Scion-generated accessors against hand-written code implementing the identical data layout. This will quantify any indirection or prefetching differences and confirm that net gains are preserved. revision: yes

  2. Referee: [§4.1] §4.1, language semantics: the formal description of how layout descriptors are lowered to traversal-compatible accessors does not specify preservation of cache-line packing or vectorization opportunities that hand-tuned code exploits; without this, the architecture-agnostic guarantee risks becoming a performance tax in hot paths.

    Authors: The Scion compiler's lowering rules are constructed to maintain the specified cache-line packing and vectorization properties through explicit layout descriptors that control alignment and access patterns. To address the concern about the formal description, we will update §4.1 to include explicit invariants stating that the lowering preserves cache-line boundaries and vector-friendly access sequences as defined in the layout specification. This will clarify that the architecture-agnostic aspect does not introduce a performance tax beyond what the chosen layout permits. revision: yes

Circularity Check

0 steps flagged

No circularity: new DSL introduction with independent empirical validation

full rationale

The paper presents Scion as a new DSL and compiler for decoupling BVH data layouts from traversal algorithms. No equations, fitted parameters, or predictive derivations are described that could reduce to inputs by construction. Claims rest on the system's ability to express existing optimizations and on empirical Pareto curves across algorithms, architectures, and workloads. These demonstrations are self-contained and do not rely on self-citation chains, ansatzes smuggled from prior author work, or renaming of known results as novel derivations. The central contribution is the introduction and evaluation of a new system rather than any closed-form reduction to prior fitted quantities.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 1 invented entities

The central claim rests on the existence and effectiveness of the newly introduced Scion system. No free parameters or standard mathematical axioms are mentioned in the abstract. The main invented entity is the Scion language and compiler itself.

invented entities (1)
  • Scion no independent evidence
    purpose: Domain-specific language and compiler for specifying BVH data layouts independently of traversal algorithms
    New system introduced to solve the entanglement problem described in the abstract.

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