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arxiv: 2601.03831 · v2 · submitted 2026-01-07 · 💻 cs.IT · eess.SP· math.IT

Low-Complexity Planar Beyond-Diagonal RIS Architecture Design Using Graph Theory

Matteo Nerini , Zheyu Wu , Shanpu Shen , Bruno Clerckx This is my paper

Pith reviewed 2026-05-16 16:47 UTC · model grok-4.3

classification 💻 cs.IT eess.SPmath.IT
keywords reconfigurable intelligent surfacesbeyond-diagonal RISgraph theoryplanar graphsprinted circuit boardsdegrees of freedomlow-complexity design
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The pith

Graph theory identifies planar-connected beyond-diagonal RIS architectures that fit on double-layer PCBs with maximum degrees of freedom.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper applies graph theory to determine which beyond-diagonal reconfigurable intelligent surface designs can be built on double-layer printed circuit boards. Beyond-diagonal RIS improve control over wireless signals by adding tunable impedance links between surface elements, but dense links normally force multi-layer boards that raise fabrication cost and difficulty. The authors represent the links as edges in a graph and establish that the architecture can be realized on a double-layer board exactly when the graph is planar. Among all planar graphs they isolate the ones that retain the largest number of independent tunable components. If the characterization holds, engineers gain a systematic way to keep most of the performance benefit of beyond-diagonal designs while using simpler manufacturing.

Core claim

The paper establishes that a beyond-diagonal RIS architecture is realizable on a double-layer PCB if and only if the graph formed by its tunable impedance interconnections is planar, and that among all such planar-connected RISs the graphs offering the largest number of edges or specific maximal structures deliver the highest degrees of freedom under the fabrication constraint.

What carries the argument

Planar graphs whose edges represent tunable impedance interconnections between RIS elements; planarity guarantees that all connections can be routed on a double-layer board without wire crossings.

If this is right

  • Planar-connected RISs can be manufactured at lower cost and complexity than architectures requiring multi-layer boards.
  • The maximal-degree-of-freedom planar graphs preserve the largest number of independent control parameters while satisfying the double-layer constraint.
  • Graph-theoretic enumeration supplies a complete catalog of admissible low-complexity BD-RIS architectures.
  • The same planar-graph test can be applied to select fabrication-feasible variants for any given number of surface elements.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same graph model could be used to optimize interconnections in other reconfigurable antenna or metasurface technologies.
  • Over-the-air measurements of a maximal planar-connected RIS would quantify how much performance is retained relative to an unconstrained multi-layer design.
  • Incorporating frequency dependence or specific impedance ranges into the planarity check could further narrow the set of recommended architectures.

Load-bearing premise

The assumption that mathematical planarity of the interconnection graph fully determines whether all tunable impedance links can be physically realized on a double-layer PCB without extra electrical or manufacturing obstacles.

What would settle it

Fabricating a beyond-diagonal RIS whose interconnection graph is non-planar on a double-layer PCB and verifying whether the required links can be completed without additional layers or vias.

Figures

Figures reproduced from arXiv: 2601.03831 by Bruno Clerckx, Matteo Nerini, Shanpu Shen, Zheyu Wu.

Figure 1
Figure 1. Figure 1: (a) The complete graph on five vertices K5 (non-planar), and (b) the complete graph on four vertices K4 (planar). from every point of the board through vias, always without crossing any interconnection. After determining the requirements on the graph G for a BD￾RIS to be planar-connected, we study in the following four propositions when existing BD-RIS architectures are planar, i.e., whether they are plana… view at source ↗
Figure 2
Figure 2. Figure 2: Recursive construction of a planar drawing of the graph of a [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Admittance matrix Y of the three examples of maximal-planar￾connected RIS, with tunable entries in black and zero entries in white. planar-connected. We observe that single-, forest-, and tree￾connected RISs are always planar, while group-, Q-stem-, and Q-band-connected RISs are planar only under conditions on the group size NG and Q, and the fully-connected RIS is not planar. IV. MAXIMAL-PLANAR-CONNECTED … view at source ↗
Figure 5
Figure 5. Figure 5: Example 3 of maximal-planar-connected RIS, with [PITH_FULL_IMAGE:figures/full_fig_p004_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: (a) Sum rate, and (b) circuit complexity of different RIS architectures. The sum rate is calculated with [PITH_FULL_IMAGE:figures/full_fig_p005_6.png] view at source ↗
read the original abstract

Reconfigurable intelligent surfaces (RISs) enable programmable control of the wireless propagation environment and are key enablers for future networks. Beyond-diagonal RIS (BD-RIS) architectures enhance conventional RIS by interconnecting elements through tunable impedance components, offering greater flexibility with higher circuit complexity. However, excessive interconnections between BD-RIS elements require multi-layer printed circuit board (PCB) designs, increasing fabrication difficulty. In this letter, we use graph theory to characterize the BD-RIS architectures that can be realized on double-layer PCBs, denoted as planar-connected RISs. Among the possible planar-connected RISs, we identify the ones with the most degrees of freedom, expected to achieve the best performance under practical constraints.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The manuscript uses graph theory to characterize beyond-diagonal RIS (BD-RIS) architectures realizable on double-layer PCBs, which it denotes as planar-connected RISs. It then identifies the subset of these architectures possessing the maximum number of degrees of freedom, which are expected to deliver the best performance under fabrication constraints.

Significance. If the graph-theoretic characterization accurately maps to physical double-layer PCB layouts, the work supplies a systematic, low-complexity design method for BD-RIS that balances circuit complexity against performance. The application of standard planarity concepts to RIS interconnection graphs is a clear methodological contribution and could guide hardware implementations in future wireless systems.

major comments (2)
  1. [Characterization of planar-connected RISs] The central claim equates planar interconnection graphs with double-layer PCB realizability, yet the manuscript provides no explicit verification or derivation showing that planarity is necessary and sufficient once via requirements, trace-length effects, and parasitic coupling are taken into account. This assumption is load-bearing for the definition of planar-connected RISs and the subsequent selection of maximum-DOF instances.
  2. [Identification of maximum-DOF planar-connected RISs] The identification of the planar-connected RIS with the largest number of degrees of freedom is presented without accompanying analysis or simulation that confirms these architectures remain optimal once the unmodeled electrical and manufacturing constraints are included. The performance claim therefore rests on an untested extrapolation from the graph model.
minor comments (1)
  1. [Abstract] The abstract states a characterization result but does not reference the section or theorem number where the derivation appears, which reduces immediate readability.

Simulated Author's Rebuttal

2 responses · 1 unresolved

We thank the referee for the constructive comments and recommendation for major revision. We address each point below, clarifying the scope of our graph-theoretic abstraction while indicating targeted revisions to the manuscript.

read point-by-point responses

  1. Referee: [Characterization of planar-connected RISs] The central claim equates planar interconnection graphs with double-layer PCB realizability, yet the manuscript provides no explicit verification or derivation showing that planarity is necessary and sufficient once via requirements, trace-length effects, and parasitic coupling are taken into account. This assumption is load-bearing for the definition of planar-connected RISs and the subsequent selection of maximum-DOF instances.

    Authors: We agree that the manuscript relies on planarity as a topological proxy for double-layer PCB realizability without a full derivation that incorporates vias, trace lengths, and parasitics. In the graph model, planarity ensures non-crossing interconnections that can be routed on two layers under idealized conditions (direct connections with no length-induced phase shifts). This is a standard abstraction in circuit topology design, but we acknowledge it is not sufficient for a complete electromagnetic validation. We will revise the manuscript by adding an explicit paragraph in Section II (System Model) stating the modeling assumptions and limitations, including that the characterization is combinatorial rather than a full PCB layout verification. revision: partial

  2. Referee: [Identification of maximum-DOF planar-connected RISs] The identification of the planar-connected RIS with the largest number of degrees of freedom is presented without accompanying analysis or simulation that confirms these architectures remain optimal once the unmodeled electrical and manufacturing constraints are included. The performance claim therefore rests on an untested extrapolation from the graph model.

    Authors: The maximum-DOF result follows directly from Euler's formula: the densest planar graph on N vertices has at most 3N-6 edges, which we identify as the upper bound on tunable impedances under the planar-connected constraint. The expectation of superior performance is stated as such in the abstract and introduction because more independent parameters allow greater flexibility in shaping the scattering matrix. We do not claim or demonstrate optimality once parasitics are included, as the letter is limited to the graph-theoretic characterization. We will revise the text in Section III to emphasize that the DOF count is combinatorial and add a sentence noting that practical optimality would require further circuit-level analysis. revision: partial

standing simulated objections not resolved
  • Providing explicit derivations or electromagnetic simulations that incorporate via requirements, trace-length effects, and parasitic coupling to confirm necessity/sufficiency and performance optimality under realistic PCB constraints.

Circularity Check

0 steps flagged

No circularity: standard graph planarity applied to model double-layer PCB constraints

full rationale

The paper maps BD-RIS interconnection architectures to graphs and uses the standard mathematical notion of planarity to characterize those realizable on double-layer PCBs, denoting the result planar-connected RISs. This modeling step relies on external graph theory rather than any self-definition, fitted parameter renamed as prediction, or load-bearing self-citation. The subsequent identification of maximum-degree-of-freedom planar graphs follows directly from known properties of planar graphs and does not reduce to the paper's own inputs or outputs. The derivation chain is therefore self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The central claim rests on the domain assumption that graph planarity exactly corresponds to double-layer PCB realizability for impedance interconnections; no free parameters or invented entities are mentioned in the abstract.

axioms (1)
  • domain assumption Interconnections between BD-RIS elements can be modeled as an undirected graph whose planarity determines double-layer PCB feasibility.
    Stated implicitly by the use of graph theory to characterize planar-connected RISs.

pith-pipeline@v0.9.0 · 5422 in / 1203 out tokens · 57573 ms · 2026-05-16T16:47:04.318673+00:00 · methodology

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Reference graph

Works this paper leans on

16 extracted references · 16 canonical work pages

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