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arxiv: 2602.05743 · v2 · pith:VZ7A7OMQnew · submitted 2026-02-05 · 💻 cs.AR

Balancing FP8 Computation Accuracy and Efficiency on Digital CIM via Shift-Aware On-the-fly Aligned-Mantissa Bitwidth Prediction

Liang Zhao , Kunming Shao , Zhipeng Liao , Xijie Huang , Tim Kwang-Ting Cheng , Chi-Ying Tsui , Yi Zou This is my paper

Pith reviewed 2026-05-21 13:45 UTC · model grok-4.3

classification 💻 cs.AR
keywords FP8compute-in-memorybitwidth predictiondigital CIMtransformer inferenceprecision scalable MACenergy efficiencyaligned-mantissa
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The pith

Dynamic bitwidth prediction lets digital CIM hardware run variable FP8 formats more efficiently.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper develops a digital compute-in-memory accelerator for FP8 formats used in transformers by introducing on-the-fly prediction of the needed mantissa bitwidths. This allows the hardware to use variable precision for weights and inputs instead of fixed widths, paired with a simplified alignment mechanism and scalable multiply-accumulate units. The design supports all FP8 variants and was tested on a 28nm chip with a 64 by 96 array. A reader would care because it addresses the rigidity of existing CIM hardware when dealing with the varying data distributions in large language models, potentially cutting energy use while keeping task performance intact.

Core claim

The paper claims that its dynamic shift-aware bitwidth prediction (DSBP) with on-the-fly input prediction adaptively adjusts aligned-mantissa precision for weights at 2/4/6/8 bits and inputs at 2 to 12 bits, combined with a FIFO-based input alignment unit and a precision-scalable INT MAC array. In 28nm CMOS with a 64×96 CIM array, it reaches 20.4 TFLOPS/W for E5M7 format, 2.8 times higher FP8 efficiency than prior work, and on Llama-7b it delivers higher efficiency than fixed bitwidth at equivalent accuracy on BoolQ and Winogrande.

What carries the argument

Dynamic shift-aware bitwidth prediction (DSBP) using on-the-fly input prediction to adaptively set weight and input aligned-mantissa bitwidths.

If this is right

  • The accelerator supports variable aligned-mantissa bitwidths for all FP8 formats.
  • It achieves 20.4 TFLOPS/W efficiency in 28nm for fixed E5M7.
  • DSBP mode provides higher efficiency than fixed bitwidth at the same accuracy on Llama-7b datasets.
  • Configurable parameters allow trade-offs between accuracy and efficiency.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • This approach may generalize to other floating-point precisions if the prediction logic can be extended.
  • Reducing reliance on complex barrel shifters could simplify future CIM designs for variable precision.
  • Real-time adaptation might enable better performance on edge devices with changing input distributions.

Load-bearing premise

The on-the-fly prediction correctly estimates the bitwidths needed for different data distributions so that accuracy stays high enough after any recovery from configurable settings, and the extra hardware for alignment and scaling adds little cost compared to the savings.

What would settle it

Running the design on additional large models beyond Llama-7b and observing whether the dynamic bitwidth selection maintains accuracy without requiring bitwidths that eliminate the efficiency advantage over fixed modes.

Figures

Figures reproduced from arXiv: 2602.05743 by Chi-Ying Tsui, Kunming Shao, Liang Zhao, Tim Kwang-Ting Cheng, Xijie Huang, Yi Zou, Zhipeng Liao.

Figure 1
Figure 1. Figure 1: (a) FP8 parameters extracted from Llama-7b with different format. [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Overall framework of our software-hardware co-design Variable-Mantissa FP8 DCIM accelerator. [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: The schematic of the proposed MPU. mantissa only needs Bfix bitwidth without further shifting. If almost all shifti values are 5, Bg,dyn will approach 5 to balance bitwidth and truncation error. k fine-tunes this prediction as a hyperparameter. B. Mantissa Prediction Unit (MPU) Design The Mantissa Prediction Unit (MPU) implements the DSBP calculation described in Algorithm 1 for on-the-fly input aligned-ma… view at source ↗
Figure 4
Figure 4. Figure 4: FIAU achieves alignment by controlling pointer movement. [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: The schematic of the adder tree and fusion unit. [PITH_FULL_IMAGE:figures/full_fig_p003_5.png] view at source ↗
Figure 7
Figure 7. Figure 7: Comparison of accuracy versus energy efficiency for fixed and DSBP [PITH_FULL_IMAGE:figures/full_fig_p004_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: (a) Area and (b) power breakdown of the proposed CIM macro. [PITH_FULL_IMAGE:figures/full_fig_p005_8.png] view at source ↗
read the original abstract

FP8 low-precision formats have gained significant adoption in Transformer inference and training. However, existing digital compute-in-memory (DCIM) architectures face challenges in supporting variable FP8 aligned-mantissa bitwidths, as unified alignment strategies and fixed-precision multiply-accumulate (MAC) units struggle to handle input data with diverse distributions. This work presents a flexible FP8 DCIM accelerator with three innovations: (1) a dynamic shift-aware bitwidth prediction (DSBP) with on-the-fly input prediction that adaptively adjusts weight (2/4/6/8b) and input (2$\sim$12b) aligned-mantissa precision; (2) a FIFO-based input alignment unit (FIAU) replacing complex barrel shifters with pointer-based control; and (3) a precision-scalable INT MAC array achieving flexible weight precision with minimal overhead. Implemented in 28nm CMOS with a 64$\times$96 CIM array, the design achieves 20.4 TFLOPS/W for fixed E5M7, demonstrating 2.8$\times$ higher FP8 efficiency than previous work while supporting all FP8 formats. Results on Llama-7b show that the DSBP achieves higher efficiency than fixed bitwidth mode at the same accuracy level on both BoolQ and Winogrande datasets, with configurable parameters enabling flexible accuracy-efficiency trade-offs.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

3 major / 2 minor

Summary. The paper proposes a digital compute-in-memory (DCIM) accelerator supporting variable FP8 formats for Transformer inference. It introduces dynamic shift-aware bitwidth prediction (DSBP) for on-the-fly adjustment of aligned-mantissa bitwidths (weights 2/4/6/8b, inputs 2~12b), a FIFO-based input alignment unit (FIAU) to replace barrel shifters, and a precision-scalable INT MAC array. Fabricated in 28nm CMOS with a 64×96 CIM array, the design reports 20.4 TFLOPS/W for fixed E5M7, 2.8× higher FP8 efficiency than prior work, and improved efficiency over fixed-bitwidth mode on Llama-7b for BoolQ and Winogrande at equivalent accuracy, with configurable parameters for accuracy-efficiency trade-offs.

Significance. If validated, the work offers a practical advance in energy-efficient CIM hardware for FP8-based LLM inference by addressing variable mantissa alignment and precision scaling. The reported efficiency numbers, support for all FP8 formats, and Llama-7b results on standard datasets provide concrete evidence of utility for edge or data-center accelerators. The hardware innovations (FIAU and scalable MAC) and on-the-fly prediction could influence future CIM designs if overheads and generalization are clearly demonstrated.

major comments (3)
  1. [§4.2] §4.2 (DSBP algorithm): The on-the-fly bitwidth prediction relies on input statistics without explicit separation of training and test data for the predictor itself; this creates a potential circularity risk where the mechanism may be tuned to the evaluated Llama-7b distributions, undermining claims of generalization to diverse inputs.
  2. [Table 2] Table 2 (efficiency comparison): The 2.8× FP8 efficiency gain versus prior work is reported for fixed E5M7 but lacks explicit baseline operating points, power breakdown, or area overheads for the added DSBP and FIAU logic; without these, it is unclear whether the gains are load-bearing or partly due to process/voltage differences.
  3. [§5.3] §5.3 (Llama-7b results): Accuracy-efficiency curves on BoolQ and Winogrande are shown for DSBP versus fixed modes, but post-hoc selection of configurable parameters and lack of error bars or multiple random seeds make it difficult to confirm that the reported higher efficiency at iso-accuracy is robust rather than dataset-specific.
minor comments (2)
  1. [§3.1] The abstract and §3.1 use '2/4/6/8b' and '2~12b' notation without defining the exact mapping to E4M3/E5M2 formats; a small table or sentence clarifying the correspondence would improve readability.
  2. [Figure 4] Figure 4 (FIAU diagram) would benefit from an explicit timing diagram showing pointer-based control latency relative to a conventional barrel shifter to quantify the claimed minimal overhead.

Simulated Author's Rebuttal

3 responses · 0 unresolved

We thank the referee for the constructive feedback and the recommendation for minor revision. We address each major comment below with clarifications and indicate where revisions will be made to improve the manuscript.

read point-by-point responses

  1. Referee: [§4.2] §4.2 (DSBP algorithm): The on-the-fly bitwidth prediction relies on input statistics without explicit separation of training and test data for the predictor itself; this creates a potential circularity risk where the mechanism may be tuned to the evaluated Llama-7b distributions, undermining claims of generalization to diverse inputs.

    Authors: We clarify that DSBP is a heuristic algorithm performing real-time statistical analysis of input mantissa distributions and shifts to predict bitwidths on the fly. It contains no learned parameters or training phase, so no separation of training and test data is involved or needed. The method adapts dynamically to any input distribution without dataset-specific tuning, including Llama-7b. We have revised §4.2 to explicitly describe DSBP as a heuristic with no training dependency to address this concern. revision: yes

  2. Referee: [Table 2] Table 2 (efficiency comparison): The 2.8× FP8 efficiency gain versus prior work is reported for fixed E5M7 but lacks explicit baseline operating points, power breakdown, or area overheads for the added DSBP and FIAU logic; without these, it is unclear whether the gains are load-bearing or partly due to process/voltage differences.

    Authors: We agree that additional details are warranted for a transparent comparison. In the revised manuscript, we will update Table 2 to specify operating points (voltage and frequency), provide a power breakdown isolating contributions from DSBP and FIAU, and report area overheads of these units relative to the CIM array. This will help distinguish our architectural gains from process or voltage variations. revision: yes

  3. Referee: [§5.3] §5.3 (Llama-7b results): Accuracy-efficiency curves on BoolQ and Winogrande are shown for DSBP versus fixed modes, but post-hoc selection of configurable parameters and lack of error bars or multiple random seeds make it difficult to confirm that the reported higher efficiency at iso-accuracy is robust rather than dataset-specific.

    Authors: The curves demonstrate DSBP's configurable trade-off space, where parameters are selected to maintain equivalent accuracy while improving efficiency on both datasets. Selection follows the design goal of iso-accuracy gains rather than arbitrary post-hoc choices. Hardware results are deterministic, so traditional error bars from random seeds do not apply; we will revise §5.3 to elaborate on the parameter selection rationale and confirm consistency across BoolQ and Winogrande. revision: partial

Circularity Check

0 steps flagged

No significant circularity detected

full rationale

The paper's core claims rest on a 28nm CMOS implementation of a 64×96 CIM array, measured efficiency of 20.4 TFLOPS/W for fixed E5M7, and empirical Llama-7b accuracy results on BoolQ and Winogrande. The DSBP mechanism is presented as an on-the-fly hardware predictor that inspects input mantissas at runtime to select aligned bitwidths; no equations or descriptions indicate that this predictor is fitted to the reported accuracy or efficiency numbers, nor that its outputs are defined in terms of the final metrics. FIAU and scalable MAC are described with pointer-based and precision-scalable hardware details whose overheads are accounted for in the measured power and throughput figures. No self-citation chains, uniqueness theorems, or ansatzes are invoked to justify the central results. The derivation chain from circuit design to measured performance is therefore self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 2 invented entities

The central claims rest on the assumption that real-time bitwidth prediction can be performed with negligible overhead and that the hardware modifications preserve functional correctness across all FP8 formats; no new physical entities are postulated.

free parameters (1)
  • configurable accuracy-efficiency trade-off parameters
    The abstract states that configurable parameters enable flexible trade-offs, implying at least one tunable threshold or scaling factor fitted or chosen to balance the reported efficiency and accuracy on BoolQ and Winogrande.
axioms (1)
  • domain assumption Diverse input data distributions in Transformers can be handled by adaptive aligned-mantissa bitwidths without violating FP8 format semantics.
    Invoked in the description of DSBP handling variable distributions.
invented entities (2)
  • DSBP (dynamic shift-aware bitwidth prediction) no independent evidence
    purpose: On-the-fly adjustment of weight and input aligned-mantissa precision
    New technique introduced to adapt precision dynamically.
  • FIAU (FIFO-based input alignment unit) no independent evidence
    purpose: Replace complex barrel shifters with pointer-based control
    New hardware unit for alignment.

pith-pipeline@v0.9.0 · 5810 in / 1605 out tokens · 43789 ms · 2026-05-21T13:45:53.945035+00:00 · methodology

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Reference graph

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