arxiv: 2603.20971 · v2 · submitted 2026-03-21 · 💻 cs.NI

Recognition: 2 theorem links

· Lean Theorem

FLEX: Joint UL/DL and QoS-Aware Scheduling for Dynamic TDD in Industrial 5G and Beyond

Leonard Kleinberger , Michael Gundall , Hans D. Schotten

Authors on Pith no claims yet

Pith reviewed 2026-05-15 06:29 UTC · model grok-4.3

classification 💻 cs.NI

keywords 5GTDDQoS schedulingindustrial networksdynamic TDDUL/DL ratiobuffer estimationns-3

0 comments

The pith

FLEX dynamically adjusts UL/DL ratios in flexible TDD 5G networks to enforce QoS priorities while matching static throughput.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Industrial 5G TDD networks currently rely on fixed uplink to downlink resource splits that cannot respond to changing traffic volumes or priorities between directions. The paper introduces FLEX as a scheduler that reconfigures the ratio slot by slot and adds a downlink buffer estimator to avoid starving high-priority downlink flows. The estimator works by using the regular, repeating arrival patterns typical of factory equipment to forecast buffer growth. Simulations with 5G LENA in ns-3 show that the method keeps total data rates close to those of established schedulers, correctly applies QoS rules in both directions, and adds less than one slot of extra delay when patterns stay predictable. This combination matters because industrial automation needs both flexibility for mixed sensor and control traffic and strict timing guarantees.

Core claim

FLEX is a QoS-aware scheduler that dynamically adjusts the UL/DL ratio in flexible TDD slots while respecting diverse QoS requirements. It introduces DL buffer state estimation to prevent starvation of high-priority DL traffic, exploiting the deterministic nature of industrial traffic patterns for accurate predictions. Through extensive simulations of industrial scenarios using 5G LENA and ns-3, FLEX achieves similar throughput compared to established scheduling while correctly enforcing QoS priorities in both traffic directions and maintains minimal latency overhead of less than one slot duration for deterministic traffic patterns.

What carries the argument

DL buffer state estimation mechanism that forecasts future downlink arrivals from deterministic industrial patterns to guide dynamic UL/DL slot reconfiguration and avoid priority starvation.

If this is right

Throughput stays comparable to static schedulers even as the UL/DL ratio changes slot by slot.
QoS priority rules apply correctly to both uplink and downlink flows at the same time.
Latency overhead remains below one slot duration when traffic follows repeating deterministic patterns.
Industrial automation systems can use adaptive TDD without losing efficiency or violating timing bounds.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

The same buffer estimation idea could be tested in non-industrial 5G scenarios if a suitable traffic model replaces the deterministic assumption.
Future standards might reduce reliance on pre-configured TDD patterns if schedulers like FLEX prove reliable across more traffic types.
Pairing the estimator with online learning could extend protection against starvation when patterns are only partially predictable.

Load-bearing premise

Industrial traffic patterns are deterministic enough that downlink buffer state estimation can accurately predict future arrivals and prevent starvation of high-priority downlink traffic.

What would settle it

A simulation run with non-deterministic traffic arrivals in which high-priority downlink flows show increased latency or starvation under the FLEX scheduler compared with static baselines.

Figures

Figures reproduced from arXiv: 2603.20971 by Hans D. Schotten, Leonard Kleinberger, Michael Gundall.

**Figure 2.** Figure 2: Activity diagram for the scheduling procedure. Resources are assigned one-by-one to the UE with the highest priority. [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗

**Figure 3.** Figure 3: PLR for different numbers of UEs in scenario 1. Lower is better. FLEX [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗

**Figure 4.** Figure 4: PLR for different numbers of UEs in scenario 2. Lower is better. FLEX [PITH_FULL_IMAGE:figures/full_fig_p006_4.png] view at source ↗

**Figure 5.** Figure 5: PLR per traffic direction in scenario 3. Lower is better. DL traffic has [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗

read the original abstract

Industrial 5G deployments using Time Division Duplex (TDD) networks face a critical challenge: existing schedulers rely on static configuration of Uplink (UL) to Downlink (DL) resource ratios, failing to adapt to dynamic asymmetric traffic demands. This limitation is particularly problematic in Industry 4.0 scenarios where traffic patterns exhibit significant asymmetry between directions and heterogeneous Quality of Service (QoS) requirements. We present FLEX, a novel QoS-aware scheduler that dynamically adjusts the UL/DL ratio in flexible TDD slots while respecting diverse QoS requirements. FLEX introduces DL buffer state estimation to prevent starvation of high-priority DL traffic, exploiting the deterministic nature of industrial traffic patterns for accurate predictions. Through extensive simulations of industrial scenarios using 5G LENA and ns-3, we demonstrate that FLEX achieves similar throughput compared to established scheduling while correctly enforcing QoS priorities in both traffic directions. For deterministic traffic patterns, FLEX maintains minimal latency overhead (less than 1 slot duration), making it particularly suitable for industrial automation applications.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

FLEX gives a workable engineering fix for asymmetric industrial 5G TDD traffic by pairing dynamic slot ratios with QoS rules and DL buffer estimates, but the gains depend on unquantified prediction accuracy.

read the letter

The main point is that FLEX combines dynamic UL/DL ratio selection with QoS-aware scheduling in flexible TDD, using DL buffer state estimation to protect high-priority downlink flows under the deterministic traffic common in factories. This is a direct response to the limitation of static configurations that cannot handle shifting asymmetry between directions while still meeting varied QoS targets. The ns-3 simulations with 5G LENA show it keeps throughput close to established schedulers, enforces priorities in both directions, and adds less than one slot of latency when patterns are perfectly periodic. That combination is new enough in the industrial 5G scheduling literature to be worth noting. The work is straightforward and grounded in a real deployment pain point, which is its main strength. The soft spot is exactly the one the stress test flags: the buffer estimation step is central to avoiding downlink starvation, yet the paper supplies no separate error metrics, false-negative rates, or results when arrivals deviate even modestly from the assumed periodicity. Without those numbers it is hard to tell how much of the reported performance is tied to the specific traffic generator rather than the scheduler itself. If the full text includes those checks, the contribution becomes more solid; if not, the claims stay simulation-specific. This is for people building or evaluating schedulers for private 5G and Industry 4.0 networks. A reader who needs concrete ideas for handling mixed UL/DL QoS under TDD will find usable design details and baseline comparisons. It deserves a serious referee because the problem is practical and the approach is implementable, even though revisions would likely be needed to quantify the estimation robustness. I would send it to review with a request for the missing prediction-accuracy analysis.

Referee Report

2 major / 2 minor

Summary. The manuscript presents FLEX, a QoS-aware scheduler for dynamic TDD in industrial 5G networks. FLEX dynamically adjusts UL/DL slot ratios while enforcing heterogeneous QoS priorities across directions. It introduces DL buffer state estimation that exploits deterministic industrial traffic patterns to predict arrivals and avoid high-priority DL starvation. ns-3 simulations using 5G LENA are reported to achieve throughput comparable to established schedulers, correct QoS enforcement, and latency overhead below one slot duration for deterministic patterns.

Significance. If the buffer estimation accuracy holds under realistic conditions, FLEX could improve resource efficiency in asymmetric industrial traffic scenarios. The use of standard simulation tools (5G LENA/ns-3) and focus on deterministic patterns provide a practical starting point, but the absence of quantified prediction error or sensitivity results limits the strength of the performance claims.

major comments (2)

[Simulation Results] The headline claims of comparable throughput, correct QoS enforcement, and <1-slot latency overhead rest on the DL buffer state estimation correctly predicting arrivals. However, the simulation results section provides no separate measurement of prediction error, false-negative rate for buffer underruns, or performance when arrivals deviate from the assumed periodicity, leaving the outcomes tied to the specific traffic generator.
[Abstract and Evaluation] The abstract and evaluation sections state that FLEX 'achieves similar throughput compared to established scheduling' and 'maintains minimal latency overhead (less than 1 slot duration)' without reporting specific quantitative metrics, exact baseline definitions, or implementation details of the buffer estimation algorithm.

minor comments (2)

[Abstract] The abstract refers to 'established scheduling' without naming the concrete baseline algorithms or configurations used for comparison.
[System Model] Notation for QoS parameters and buffer estimation variables could be introduced more clearly in the system model section before the algorithm description.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback. We address each major comment below and indicate planned revisions to strengthen the manuscript.

read point-by-point responses

Referee: [Simulation Results] The headline claims of comparable throughput, correct QoS enforcement, and <1-slot latency overhead rest on the DL buffer state estimation correctly predicting arrivals. However, the simulation results section provides no separate measurement of prediction error, false-negative rate for buffer underruns, or performance when arrivals deviate from the assumed periodicity, leaving the outcomes tied to the specific traffic generator.

Authors: We agree that explicit quantification of the buffer estimation accuracy would strengthen the claims. In the revised version we will add a dedicated subsection reporting prediction error (mean absolute error and false-negative rate for underruns) under the deterministic patterns used in the main experiments. We will also include sensitivity results for moderate deviations from periodicity (e.g., 5–20 % jitter) using the same 5G LENA/ns-3 setup. These additions will be placed before the main performance figures so that readers can assess how tightly the reported throughput and latency results depend on perfect periodicity. revision: yes
Referee: [Abstract and Evaluation] The abstract and evaluation sections state that FLEX 'achieves similar throughput compared to established scheduling' and 'maintains minimal latency overhead (less than 1 slot duration)' without reporting specific quantitative metrics, exact baseline definitions, or implementation details of the buffer estimation algorithm.

Authors: We accept that the current wording is insufficiently precise. We will revise the abstract to state concrete figures (e.g., “within 3 % of Proportional-Fair throughput under the evaluated loads”) and will explicitly name the baselines (Proportional Fair and Round-Robin with static TDD configuration). In the evaluation section we will add a table of exact throughput, latency, and QoS-violation percentages together with a new appendix containing the pseudocode and parameter settings of the DL buffer-state estimator. These changes will be made without altering the original simulation data. revision: yes

Circularity Check

0 steps flagged

No significant circularity in derivation chain

full rationale

The paper presents FLEX as a scheduling algorithm whose core mechanism (DL buffer state estimation) is motivated by the external assumption of deterministic industrial traffic patterns rather than any fitted parameter or self-referential definition. Performance claims are grounded in independent ns-3/5G LENA simulations that compare throughput, QoS enforcement, and latency against established baselines; no equations, self-citations, or ansatzes are shown that would force the reported outcomes by construction. The derivation chain therefore remains self-contained and externally falsifiable.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The performance claims rest on the domain assumption that industrial traffic is sufficiently deterministic for buffer prediction to work; no free parameters or new entities are explicitly introduced in the abstract.

axioms (1)

domain assumption Industrial traffic patterns are deterministic and therefore predictable from recent buffer states
Invoked to justify the DL buffer state estimation that prevents starvation.

pith-pipeline@v0.9.0 · 5489 in / 1179 out tokens · 34356 ms · 2026-05-15T06:29:25.266374+00:00 · methodology

discussion (0)

Lean theorems connected to this paper

Citations machine-checked in the Pith Canon. Every link opens the source theorem in the public Lean library.

IndisputableMonolith/Cost/FunctionalEquation.lean washburn_uniqueness_aczel unclear

?

unclear
Relation between the paper passage and the cited Recognition theorem.

FLEX introduces DL buffer state estimation to prevent starvation of high-priority DL traffic, exploiting the deterministic nature of industrial traffic patterns for accurate predictions.
IndisputableMonolith/Foundation/BranchSelection.lean branch_selection unclear

?

unclear
Relation between the paper passage and the cited Recognition theorem.

The priority function: w_i,f(t) = 1/5QI × r_i,f(t)/R_i,f(t)

What do these tags mean?

matches: The paper's claim is directly supported by a theorem in the formal canon.
supports: The theorem supports part of the paper's argument, but the paper may add assumptions or extra steps.
extends: The paper goes beyond the formal theorem; the theorem is a base layer rather than the whole result.
uses: The paper appears to rely on the theorem as machinery.
contradicts: The paper's claim conflicts with a theorem or certificate in the canon.
unclear: Pith found a possible connection, but the passage is too broad, indirect, or ambiguous to say the theorem truly supports the claim.

Reference graph

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