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arxiv: 2604.05313 · v1 · submitted 2026-04-07 · 📡 eess.SY · cs.SY

An Ultra-Low-Power Synthesizable Asynchronous AER Encoder for Neuromorphic Edge Devices

Yihui Wang , Sheng-Yu Peng , Sahil Shah This is my paper

Pith reviewed 2026-05-10 20:06 UTC · model grok-4.3

classification 📡 eess.SY cs.SY
keywords AERasynchronous encoderneuromorphicsynthesizablemicropipelinebundled-datalow-poweredge devices
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The pith

A fully synthesizable tree-based AER encoder achieves 33 MEvent/s throughput and 435 fJ per event using only standard digital cells.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper establishes a fully synthesizable asynchronous AER encoder for neuromorphic edge devices by employing a tree-based architecture with semi-decoupled micropipeline and bundled-data protocol. This replaces custom latches with standard flip-flops and embeds a random-priority arbiter, allowing complete digital synthesis and place-and-route. A prototype fabricated in 65 nm CMOS validates the approach with measured performance of 33 MEvent/s peak throughput, 50 ns average event latency, and 435 fJ energy per encoded event. This matters for enabling scalable, low-power event encoding in commercial digital processes without specialized design flows.

Core claim

The central claim is that an asynchronous AER encoder can be realized as a purely digital, standard-cell design using a semi-decoupled micropipeline with bundled-data protocol and an embedded cross-coupled NAND arbiter, achieving high throughput and ultra-low power as proven by silicon measurements in 65 nm technology.

What carries the argument

Semi-decoupled micropipeline with bundled-data protocol and embedded random-priority arbiter that allows replacement of latches with flip-flops for synthesizability while resolving event collisions.

Load-bearing premise

That the asynchronous micropipeline and arbiter circuit will operate correctly and without errors when extended to larger numbers of events beyond the tested 8-event prototype.

What would settle it

A fabricated larger-scale version of the encoder showing arbitration conflicts, timing violations, or energy per event significantly above 435 fJ would disprove the claims of reliable scalability and ultra-low power.

Figures

Figures reproduced from arXiv: 2604.05313 by Sahil Shah, Sheng-Yu Peng, Yihui Wang.

Figure 1
Figure 1. Figure 1: The Address-Event Representation (AER) protocol. The AER system [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: The proposed asynchronous bundled-data micropipeline. (a) Datapath [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 4
Figure 4. Figure 4: (a) Earle latch-based C-elements. (b) Modified 4-phase Semi [PITH_FULL_IMAGE:figures/full_fig_p002_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Multiplexed Arbitration circuit. The inherent metastability of the cross [PITH_FULL_IMAGE:figures/full_fig_p003_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: The stochastic arbiters were implemented exclusively [PITH_FULL_IMAGE:figures/full_fig_p003_6.png] view at source ↗
Figure 6
Figure 6. Figure 6: Die micrograph and layout details of the fabricated AER encoder in [PITH_FULL_IMAGE:figures/full_fig_p004_6.png] view at source ↗
read the original abstract

This paper presents a fully synthesizable, treebased Address-Event Representation (AER) encoder designed for scalable neuromorphic computing systems. To achieve high throughput while maintaining strict compatibility with commercial EDA workflows, the asynchronous design employs a bundled-data protocol within a semi-decoupled micropipeline. The architecture replaces traditional transparent latches with standard edge-triggered flip-flops, enabling digital synthesis and place-and-route (PnR) using Cadence toolkits. A cross-coupled NAND-based random-priority arbiter is embedded within the encoder of each tree node to resolve event collisions efficiently. An 8-event AER prototype is fabricated in 65 nm CMOS technology utilizing a purely digital standard-cell flow. Post-fabrication silicon measurements validate the design, demonstrating a peak throughput of 33 MEvent/s and an average event latency of 50 ns, equating to a propagation delay of 17 ns/(event-bit). The design consumes only 435 fJ per encoded event.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. This paper presents a fully synthesizable tree-based asynchronous AER encoder for neuromorphic edge devices. It uses a bundled-data protocol in a semi-decoupled micropipeline, replaces transparent latches with edge-triggered flip-flops for standard-cell EDA compatibility, and embeds cross-coupled NAND random-priority arbiters at each tree node. An 8-event prototype fabricated in 65 nm CMOS is validated by post-silicon measurements showing 33 MEvent/s peak throughput, 50 ns average latency (17 ns per event-bit), and 435 fJ per encoded event.

Significance. If the central claims hold, the work offers a practical, ultra-low-power synthesizable AER solution that could ease integration of neuromorphic interfaces into digital edge systems. The silicon measurements provide direct empirical support for the prototype's throughput and energy figures, which is a strength for an engineering design paper. The standard-cell flow and avoidance of custom latches are notable for reproducibility and adoption.

major comments (2)
  1. [Abstract] Abstract: The positioning of the design as suitable for 'scalable neuromorphic computing systems' is load-bearing but unsupported beyond the 8-event prototype. No simulation results, timing analysis, or validation of the semi-decoupled micropipeline and embedded arbiter are provided for deeper trees or higher event densities, where accumulated forward-path delay mismatch could violate the bundled-data assumption or introduce unexercised metastability.
  2. [Prototype validation] Prototype results (as reported in the abstract and validation section): The measured peak throughput of 33 MEvent/s and energy of 435 fJ/event lack any baseline comparison to prior AER encoders or details on test conditions (e.g., event injection rate, temperature, or number of trials), which weakens assessment of the claimed performance margins.
minor comments (2)
  1. [Abstract] Abstract: The reported figures (50 ns latency, 17 ns/(event-bit) delay) would benefit from explicit definition of how the per-event-bit metric is derived from the measured latency and whether it accounts for arbitration overhead.
  2. [Abstract] Abstract: Inclusion of error bars, standard deviations, or at least a statement of measurement repeatability would improve the presentation of the silicon results.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We are grateful to the referee for the thorough review and valuable feedback. We address each major comment below, agreeing to strengthen the manuscript with additional analysis and details where appropriate.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The positioning of the design as suitable for 'scalable neuromorphic computing systems' is load-bearing but unsupported beyond the 8-event prototype. No simulation results, timing analysis, or validation of the semi-decoupled micropipeline and embedded arbiter are provided for deeper trees or higher event densities, where accumulated forward-path delay mismatch could violate the bundled-data assumption or introduce unexercised metastability.

    Authors: We thank the referee for this observation. The design employs a modular tree structure with replicated semi-decoupled micropipelines and embedded arbiters, which by construction supports scaling to larger event counts without custom cells. The 8-event prototype confirms the functionality and performance in silicon. To directly address the concern, the revised manuscript will include post-synthesis timing analysis and behavioral simulations for deeper trees (such as 16- and 32-event configurations), verifying that delay mismatches do not violate the bundled-data protocol and that metastability is properly resolved at each level. revision: yes

  2. Referee: [Prototype validation] Prototype results (as reported in the abstract and validation section): The measured peak throughput of 33 MEvent/s and energy of 435 fJ/event lack any baseline comparison to prior AER encoders or details on test conditions (e.g., event injection rate, temperature, or number of trials), which weakens assessment of the claimed performance margins.

    Authors: We agree that providing baseline comparisons and test setup details will facilitate better evaluation. The measurements were obtained from the fabricated prototype under controlled conditions. In the revised version, we will augment the results section with a comparison to representative prior AER encoders (including throughput, energy per event, and technology node) and specify the test conditions: event injection at varying rates up to 33 MEvent/s using an on-chip pattern generator, measurements at 25°C, and statistics over 10,000 events across multiple runs. revision: yes

Circularity Check

0 steps flagged

No circularity: design validated by silicon measurements, no derivations or predictions

full rationale

The paper describes a synthesizable asynchronous AER encoder architecture using bundled-data semi-decoupled micropipelines and standard-cell flip-flops, followed by fabrication of an 8-event prototype in 65 nm CMOS and direct post-silicon measurements of throughput, latency, and energy. No equations, first-principles derivations, fitted parameters, or predictions appear in the provided text; performance claims reduce directly to measured silicon results rather than to any self-referential construction, self-citation chain, or ansatz. The scaling assumption for larger trees is stated as a design goal but is not presented as a derived result.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The central claim rests on standard asynchronous circuit design principles and the properties of the 65 nm CMOS process; no free parameters, invented entities, or ad-hoc axioms are introduced beyond domain assumptions.

axioms (1)
  • domain assumption Bundled-data asynchronous protocols and semi-decoupled micropipelines function correctly when implemented with edge-triggered flip-flops
    The design replaces transparent latches with flip-flops while preserving asynchronous timing assumptions from prior literature.

pith-pipeline@v0.9.0 · 5469 in / 1271 out tokens · 66270 ms · 2026-05-10T20:06:55.872051+00:00 · methodology

discussion (0)

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