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arxiv: 2604.07387 · v2 · submitted 2026-04-08 · 💻 cs.AR · cs.AI

A Self-Calibrating Framework for Analog Circuit Sizing Using LLM-Derived Analytical Equations

Antonio J. Bujana , Aydin I. Karsilayan This is my paper

Pith reviewed 2026-05-10 18:34 UTC · model grok-4.3

classification 💻 cs.AR cs.AI
keywords analog circuit sizingLLM-derived equationsself-calibrationdesign automationprocess portabilityanalytical modelsopamp topologies
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The pith

LLM-derived analytical equations for analog circuits are calibrated from one DC simulation to enable fast, portable sizing.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper develops a framework that uses a large language model to generate complete analytical sizing functions directly from circuit netlists, with each device dimension linked to an explicit design rationale. These functions are then adjusted through a deterministic calibration that pulls process-dependent parameters from a single DC operating point simulation, combined with an iterative feedback loop that corrects for any remaining prediction inaccuracies. Validation covers opamp topologies from 8 to 30 transistors across 40 nm, 90 nm, and 180 nm nodes. On standard benchmarks the process reaches target specifications in 2 to 7 simulations total, and the same calibrated equations transfer to new process nodes without retraining or additional characterization. If this holds, analog sizing shifts from repeated black-box optimization to a short sequence of interpretable analytical steps anchored by minimal measurement feedback.

Core claim

The central claim is that LLM-generated topology-specific analytical equations, when paired with a one-shot calibration extracted from a single DC point and a measurement-feedback correction loop, produce accurate device sizes for analog circuits in only 2-7 simulations while automatically absorbing process variations for direct portability across nodes.

What carries the argument

The measurement-feedback architecture that extracts process parameters from one DC operating point and iteratively compensates residual analytical errors in the LLM-derived sizing function.

If this is right

  • Sizing converges in 2-7 simulations on benchmarks spanning Miller, folded-cascode, nested-Miller, and class-AB opamps.
  • The same equations and calibration procedure transfer across 40 nm, 90 nm, and 180 nm nodes without modification or retraining.
  • Each final device dimension remains traceable to a specific design rationale inside the generated Python sizing function.
  • Convergence occurs even when initial equation predictions contain large errors, because the feedback loop corrects them.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The approach could lower the entry barrier for analog design by letting a designer supply only a netlist and receive both sizes and the reasoning behind them.
  • If LLM equation quality improves further, the number of required simulations might drop to one or two after calibration.
  • The same self-calibration idea could be tested on other analog tasks such as filter tuning or power-amplifier matching.
  • Integration with existing SPICE flows would let designers run the framework as a lightweight pre-step before full verification.

Load-bearing premise

The large language model must produce complete, topology-specific analytical equations from a raw netlist that remain usable after calibration from only one DC operating point.

What would settle it

Applying the framework to a matched-specification class-AB opamp benchmark on a new process node and observing that it requires more than seven simulations or fails to meet all specifications after the single DC calibration step.

Figures

Figures reproduced from arXiv: 2604.07387 by Antonio J. Bujana, Aydin I. Karsilayan.

Figure 1
Figure 1. Figure 1: Self-calibrating framework architecture. The loop iterates until all target specifications are met [PITH_FULL_IMAGE:figures/full_fig_p004_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Calibration table from calibrate.py output for 2SMC-N at 40 nm, as provided to the LLM in the Round 1 prompt. M5 is flagged as operating in the triode region [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Excerpt from the LLM-generated compute_sizing() function for 2SMC-P at 180 nm, Round 0. The complete function (~200 lines) is executed unmodified [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Schematic diagrams of the tested topologies. (a) Current-mirror (CM-N). (b) Folded cascode (FC-N). (c) Two-stage Miller-compensated (2SMC-N). (d) Nested Miller-compensated (NMC). (e) Complementary class-AB opamp (30T). NMOS￾input variants shown for (a)–(c) [PITH_FULL_IMAGE:figures/full_fig_p008_4.png] view at source ↗
read the original abstract

We present a design automation framework for analog circuit sizing that produces calibrated, topology-specific analytical equations from raw circuit netlists. A large language model (LLM) derives a complete Python sizing function in which each device dimension is traceable to a specific design rationale - a form of interpretable output absent from existing optimization-based and LLM-based sizing methods. A deterministic calibration loop extracts process-dependent parameters from a single DC operating point simulation, while a prediction-error feedback mechanism compensates for analytical inaccuracies. We validate the framework on circuits ranging from 8 to 30 transistors - spanning two-stage Miller-compensated, current-mirror, folded cascode, nested Miller-compensated, and complementary class-AB output topologies - across three process nodes (40 nm, 90 nm, 180 nm). On matched-specification benchmarks, including the class-AB opamp case, the framework converges in 2-7 simulations. Despite large initial prediction errors, convergence depends on the measurement-feedback architecture, not prediction accuracy. The one-shot calibration automatically captures process-dependent variations, enabling cross-node portability without modification, retraining, or per-process characterization.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 3 minor

Summary. The paper presents a self-calibrating framework for analog circuit sizing in which an LLM derives complete, topology-specific analytical equations (as a Python function with traceable design rationales) directly from raw netlists. A deterministic loop extracts process-dependent parameters from a single DC operating-point simulation, and a prediction-error feedback mechanism compensates for analytical inaccuracies. Validation is reported on 8- to 30-transistor circuits (two-stage Miller, current-mirror, folded-cascode, nested-Miller, and class-AB topologies) across 40 nm, 90 nm, and 180 nm nodes, with convergence in 2-7 simulations on matched-specification benchmarks and claims of unmodified cross-node portability without retraining or per-process characterization.

Significance. If the central claims hold, the work would represent a meaningful advance in analog EDA by delivering interpretable, equation-based sizing that achieves very low simulation counts while automatically capturing process variations. The combination of LLM-derived traceable equations and measurement-feedback architecture, together with explicit validation across multiple topologies and nodes, distinguishes it from both black-box optimizers and pure data-driven methods. The emphasis that convergence depends on the feedback loop rather than initial prediction accuracy is a useful insight.

major comments (1)
  1. [Calibration procedure] Calibration loop description: the claim that a single DC operating-point simulation suffices to extract all relevant process-dependent parameters (mobility, thresholds, channel-length modulation, etc.) and thereby enable unmodified cross-node portability (40 nm to 180 nm) without retraining or characterization is load-bearing for the portability and low-simulation-count results. Analog compact models are multi-parameter; one bias point yields an underdetermined system for fitting quantities that affect multiple operating regimes and performance metrics. While intra-node feedback can compensate equation errors, evidence is needed that the extracted parameters produce unbiased starting points that the 2-7 simulation loop reliably corrects across topologies and specs.
minor comments (3)
  1. The abstract states 'large initial prediction errors' and 'convergence in 2-7 simulations' but provides no quantitative error metrics, tolerance definitions, or tables comparing initial vs. final sizing accuracy.
  2. No details are given on the LLM (model, temperature, prompt templates, or verification steps) used to derive the analytical equations from netlists, which affects reproducibility of the interpretable-output claim.
  3. [Validation] The validation section would benefit from explicit definition of 'matched-specification benchmarks' and the precise convergence criterion (e.g., error tolerances on gain, bandwidth, phase margin).

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the constructive feedback and for recognizing the potential significance of the self-calibrating framework. We address the major comment on the calibration procedure below, providing clarification on the method and its empirical support while acknowledging the inherent limitations of single-point extraction.

read point-by-point responses

  1. Referee: [Calibration procedure] Calibration loop description: the claim that a single DC operating-point simulation suffices to extract all relevant process-dependent parameters (mobility, thresholds, channel-length modulation, etc.) and thereby enable unmodified cross-node portability (40 nm to 180 nm) without retraining or characterization is load-bearing for the portability and low-simulation-count results. Analog compact models are multi-parameter; one bias point yields an underdetermined system for fitting quantities that affect multiple operating regimes and performance metrics. While intra-node feedback can compensate equation errors, evidence is needed that the extracted parameters produce unbiased starting points that the 2-7 simulation loop reliably corrects across topologies and specs.

    Authors: We agree that a single DC operating point cannot uniquely determine all parameters of a full compact model across all regimes, and that the system is underdetermined in principle. Our calibration procedure does not attempt to fit a complete device model; instead, it extracts a small set of effective, bias-point-specific scalars (e.g., effective mobility and threshold at the target operating region) that are directly substituted into the LLM-derived analytical equations for that particular circuit. These scalars are obtained deterministically from the DC solution without optimization or fitting. The subsequent prediction-error feedback loop then iteratively corrects residual inaccuracies, as emphasized in the manuscript. The cross-node results (40 nm to 180 nm) were obtained with identical LLM-derived equations and the same calibration routine, without any node-specific retraining or additional characterization. While we do not claim the extracted parameters are globally accurate, the experimental evidence shows that they consistently produce starting points from which the 2-7 simulation feedback loop converges on the target specifications for the evaluated topologies. To address the request for more explicit evidence, we will revise the manuscript to include: (i) a detailed description of the exact parameters extracted and the extraction equations, (ii) tabulated initial prediction errors versus final converged values across all test cases, and (iii) an ablation showing convergence behavior when the calibration step is disabled. revision: partial

Circularity Check

0 steps flagged

No significant circularity; calibration supplies independent empirical grounding

full rationale

The paper's chain begins with LLM derivation of topology-specific analytical equations from raw netlists, followed by a deterministic calibration loop that extracts process parameters directly from a single DC operating-point simulation. This simulation measurement constitutes external data, not a fitted input renamed as prediction or a self-definitional loop. The framework explicitly attributes convergence (2-7 simulations) to the measurement-feedback architecture rather than the accuracy of the initial LLM-derived predictions. No self-citations, uniqueness theorems, or ansatzes from prior author work are invoked to justify the core sizing function or portability claim. The cross-node behavior is presented as an empirical outcome of the one-shot calibration, which remains falsifiable against additional simulation benchmarks. The method is therefore self-contained against external validation data.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The central claim depends on the LLM's capability to produce usable equations and the effectiveness of the single-simulation calibration for process variations.

axioms (1)
  • domain assumption Large language models can generate complete and correct analytical sizing equations from circuit netlists
    This is the core mechanism described in the abstract for producing the Python functions.

pith-pipeline@v0.9.0 · 5506 in / 1381 out tokens · 81735 ms · 2026-05-10T18:34:05.541000+00:00 · methodology

discussion (0)

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Reference graph

Works this paper leans on

16 extracted references · 16 canonical work pages · 1 internal anchor

  1. [1]

    Batch Bayesian optimization via multi- objective acquisition ensemble for automated analog circuit design,

    W. Lyu, F. Yang, C. Yan, D. Zhou, and X. Zeng, "Batch Bayesian optimization via multi- objective acquisition ensemble for automated analog circuit design," in Proc. Int. Conf. Mach. Learn. (ICML), 2018, pp. 3306–3314

    work page 2018

  2. [2]

    The initialization effect: Refining Bayesian optimization for circuit design,

    A. James, Z. H. Kong, S. K. Ata, K. M. M. Aung, K. S. Yeo, C. S. Foo, and A. James, "The initialization effect: Refining Bayesian optimization for circuit design," IEEE Trans. Circuits Syst. Artif. Intell., vol. 3, no. 1, pp. 38–47, 2026

    work page 2026

  3. [3]

    Optimal design of a CMOS op -amp via geometric programming,

    M. del Mar Hershenson, S. P. Boyd, and T. H. Lee, "Optimal design of a CMOS op -amp via geometric programming," IEEE Trans. Comput.- Aided Design Integr. Circuits Syst., vol. 20, no. 1, pp. 1–21, Jan. 2001

    work page 2001

  4. [4]

    AutoCkt: Deep reinforcement learning of analog circuit designs,

    K. Settaluri, A. Haj -Ali, Q. Huang, K. Hakhamaneshi, and B. Nikolić, "AutoCkt: Deep reinforcement learning of analog circuit designs," in Proc. Design, Autom. Test Eur. Conf. (DATE), 2020, pp. 490–495

    work page 2020

  5. [5]

    P. G. A. Jespers and B. Murmann, Systematic Design of Analog CMOS Circuits: Using Pre -Computed Lookup Tables. Cambridge, U.K.: Cambridge Univ. Press, 2017

    work page 2017

  6. [6]

    EEsizer: LLM-based AI agent for sizing of analog and mixed signal circuit,

    C. Liu and D. Chitnis, "EEsizer: LLM-based AI agent for sizing of analog and mixed signal circuit," IEEE Trans. Circuits Syst. I, Reg. Papers, 2026, doi: 10.1109/TCSI.2025.3646359

    work page doi:10.1109/tcsi.2025.3646359 2026

  7. [7]

    LEDRO: LLM-enhanced design space reduction and optimization for analog circuits,

    D. V. Kochar, H. Wang, A. P. Chandrakasan, and X. Zhang, "LEDRO: LLM-enhanced design space reduction and optimization for analog circuits," in Proc. IEEE Int. Conf. LLM -Aided Design (ICLAD), 2025, pp. 141–148

    work page 2025

  8. [8]

    LLM -USO: Large language model -based universal sizing optimizer,

    N. S. K. Somayaji and P. Li, "LLM -USO: Large language model -based universal sizing optimizer," IEEE Trans. Comput. -Aided Design Integr. Circuits Syst., vol. 45, no. 4, pp. 1907 –1920, Apr. 2026, doi: 10.1109/TCAD.2025.3604643

    work page doi:10.1109/tcad.2025.3604643 1907

  9. [9]

    ADO-LLM: Analog design Bayesian optimization with in-context learning of large language models,

    Y. Yin, Y. Wang, B. Xu, and P. Li, "ADO-LLM: Analog design Bayesian optimization with in-context learning of large language models," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design (ICCAD), 2024, pp. 1–9

    work page 2024

  10. [10]

    11240788

    M. Ahmadzadeh, K. Chen, and G. Gielen, "(Invited Paper) AnaFlow: Agentic LLM -based workflow for reasoning -driven explainable and sample-efficient analog circuit sizing," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design (ICCAD), 2025, doi: 10.1109/ICCAD66269.2025.11240818. 14

    work page doi:10.1109/iccad66269.2025.11240818 2025

  11. [11]

    Atelier: An automated analog circuit design framework via multiple large language model-based agents,

    J. Shen, Z. Chen, J. Zhuang, J. Huang, F. Yang, L. Shang, Z. Bi, C. Yan, D. Zhou, and X. Zeng, "Atelier: An automated analog circuit design framework via multiple large language model-based agents," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 45, no. 1, pp. 31 –44, 2026

    work page 2026

  12. [12]

    AutoSizer: Automatic sizing of analog and mixed -signal circuits via large language model (LLM) agents,

    X. Yu, D. Torbunov, S. Mandal, and Y. Ren, "AutoSizer: Automatic sizing of analog and mixed -signal circuits via large language model (LLM) agents," arXiv preprint arXiv:2602.02849, 2026

    work page internal anchor Pith review arXiv 2026

  13. [13]

    TopoSizing: An LLM-aided framework of topology -based understanding and sizing for AMS circuits,

    Z. Wei, Z. Kong, Y. Wang, D. Z. Pan, and X. Tang, "TopoSizing: An LLM-aided framework of topology -based understanding and sizing for AMS circuits," arXiv preprint arXiv:2509.14169, 2025

    work page arXiv 2025

  14. [14]

    EasySize: Elastic analog circuit sizing via LLM -guided heuristic search,

    X. Wu et al., "EasySize: Elastic analog circuit sizing via LLM -guided heuristic search," arXiv preprint arXiv:2508.05113, 2025

    work page arXiv 2025

  15. [15]

    LLMACD: An LLM -based analog circuit designer driven by behavior parameters,

    S. Xu, H. Zhi, J. Li, and W. Shan, "LLMACD: An LLM -based analog circuit designer driven by behavior parameters," in Proc. Int. Symp. Electron. Design Autom. (ISEDA), 2025, pp. 157–162

    work page 2025

  16. [16]

    Ampagent: An llm-based multi-agent system for multi-stage amplifier schematic design from literature for process and performance porting,

    C. Liu, W. Chen, A. Peng, Y. Du, L. Du, and J. Yang, "AmpAgent: An LLM-based multi-agent system for multi-stage amplifier schematic design from literature for process and performance porting," arXiv preprint arXiv:2409.14739, 2024. Antonio J. Bujana (Graduate Student Member, IEEE) received the B.S. degrees in engineering (electrical and biomedical) and th...

    work page arXiv 2024