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arxiv: 2604.12891 · v1 · submitted 2026-04-14 · 💻 cs.LG · cs.AR

Recognition: unknown

TCL: Enabling Fast and Efficient Cross-Hardware Tensor Program Optimization via Continual Learning

Chaoyao Shen , Linfeng Jiang , Yixian Shen , Tao Xu , Guoqing Li , Anuj Pathania , Andy D. Pimentel , Meng Zhang
Authors on Pith no claims yet

Pith reviewed 2026-05-10 15:42 UTC · model grok-4.3

classification 💻 cs.LG cs.AR
keywords tensor program optimizationcontinual learningcross-hardware optimizationcost modelactive learningdeep learning compilersknowledge distillationMamba model
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The pith

TCL speeds up tensor program tuning by over 12x on CPU and GPU while improving inference latency.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Deep learning compilers use cost models and auto-tuning to adapt tensor programs to specific hardware, but building those models requires large, expensive offline datasets that transfer poorly between platforms. TCL introduces a framework that reduces this burden through three coordinated pieces. An RDU Sampler picks just 10 percent of candidate programs by balancing representativeness, diversity, and uncertainty. A lightweight Mamba cost model captures long schedule dependencies without heavy parameterization. A continuous distillation process transfers learned knowledge across hardware without the parameter growth typical of multi-task training. Experiments on mainstream models show the combined system tunes programs much faster than prior baselines and yields slightly lower inference times.

Core claim

TCL is a compiler framework for cross-hardware tensor program optimization built on an RDU Sampler that selects only 10 percent of programs while preserving cost-model accuracy, a Mamba-based cost model that models long-range dependencies efficiently, and a continuous knowledge distillation method that transfers knowledge progressively across platforms; together these components deliver substantially faster tuning and modestly better inference latency than Tenset-MLP on both CPU and GPU.

What carries the argument

The RDU Sampler, which jointly scores tensor programs for representativeness, diversity, and uncertainty to enable data-efficient active learning that trains accurate cost models from far fewer examples.

If this is right

  • Tuning time drops by roughly 16x on CPU and 12x on GPU for typical deep learning models.
  • Final optimized programs run with 13-20 percent lower latency than those produced by the prior Tenset-MLP baseline.
  • Data collection cost for cost-model training falls to roughly one-tenth of previous requirements.
  • Knowledge can be transferred to new hardware platforms without retraining from scratch or suffering parameter explosion.
  • The same three-component structure supports progressive improvement as additional hardware targets are encountered.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The continual-distillation design may allow incremental updates when entirely new hardware families appear without discarding prior knowledge.
  • Because only a small program subset is needed, the approach could be applied in resource-constrained environments such as edge-device optimization loops.
  • The method's emphasis on uncertainty sampling suggests it could be combined with online feedback from actual hardware runs to further refine the cost model over time.

Load-bearing premise

Selecting only 10 percent of tensor programs with the RDU criteria keeps the cost model's accuracy close enough to the full-data version that optimization quality does not degrade on new programs or platforms.

What would settle it

Train the cost model once on the full dataset and once on the RDU-selected 10 percent subset, then compare both the prediction error on held-out tensor programs and the final tuned inference latency; a large gap in either metric would falsify the efficiency claim.

Figures

Figures reproduced from arXiv: 2604.12891 by Andy D. Pimentel, Anuj Pathania, Chaoyao Shen, Guoqing Li, Linfeng Jiang, Meng Zhang, Tao Xu, Yixian Shen.

Figure 1
Figure 1. Figure 1: Examples of two tensor programs for Conv + BN + ReLU subgraph in ResNet-18 on Nvidia Tesla T4 [PITH_FULL_IMAGE:figures/full_fig_p005_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Overview of the TCL cross-hardware DL Complier. The training phase offline-trains the cost model for the target hardware, [PITH_FULL_IMAGE:figures/full_fig_p006_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Distribution of operator types for assignments on Intel Xeon E5-2673 in the Tenset dataset. This dataset covers 2,308 assignments [PITH_FULL_IMAGE:figures/full_fig_p007_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Normalized latency score frequency distribution for tensor programs on Intel Xeon E5-2673 in the Tenset dataset. The [PITH_FULL_IMAGE:figures/full_fig_p007_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Model architecture description of Mamba-based cost model. [PITH_FULL_IMAGE:figures/full_fig_p010_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Overview of the proposed Continuous Knowledge Distillation (CKD) framework for cross-hardware cost model training. [PITH_FULL_IMAGE:figures/full_fig_p012_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Comparison Across Different Sampling Rates on CPU and GPU Platforms. [PITH_FULL_IMAGE:figures/full_fig_p017_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: The Top-1 Score of Alternating CL and KD on CPU/GPU. [PITH_FULL_IMAGE:figures/full_fig_p019_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Tuning Curves of Five Representative Models on CPU and GPU. [PITH_FULL_IMAGE:figures/full_fig_p021_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Comparison of Tuning Time Required to Match Tenset-MLP’s Inference Latency Across Different Models [PITH_FULL_IMAGE:figures/full_fig_p022_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Inference Latency Achieved Under 2000 Tuning Trials Across Different Models [PITH_FULL_IMAGE:figures/full_fig_p022_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Comparison of Tuning Time Required to Match Ansor’s Inference Latency Across Different Models. [PITH_FULL_IMAGE:figures/full_fig_p023_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: Inference Latency Achieved Under 2000 Tuning Trials Across Different Models. [PITH_FULL_IMAGE:figures/full_fig_p023_13.png] view at source ↗
read the original abstract

Deep learning (DL) compilers rely on cost models and auto-tuning to optimize tensor programs for target hardware. However, existing approaches depend on large offline datasets, incurring high collection costs and offering suboptimal transferability across platforms. In this paper, we introduce TCL, a novel efficient and transferable compiler framework for fast tensor program optimization across diverse hardware platforms to address these challenges. Specifically, TCL is built on three core enablers: (1) the RDU Sampler, a data-efficient active learning strategy that selects only 10% of tensor programs by jointly optimizing Representativeness, Diversity, and Uncertainty, substantially reducing data collection costs while maintaining near-original model accuracy; (2) a new Mamba-based cost model that efficiently captures long-range schedule dependencies while achieving a favorable trade-off between prediction accuracy and computational cost through reduced parameterization and lightweight sequence modeling; and (3) a continuous knowledge distillation framework that effectively and progressively transfers knowledge across multiple hardware platforms while avoiding the parameter explosion and data dependency issues typically caused by traditional multi-task learning. Extensive experiments validate the effectiveness of each individual enabler and the holistic TCL framework. When optimizing a range of mainstream DL models on both CPU and GPU platforms, TCL achieves, on average, 16.8x and 12.48x faster tuning time, and 1.20x and 1.13x lower inference latency, respectively, compared to Tenset-MLP.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The manuscript introduces TCL, a framework for efficient cross-hardware tensor program optimization in deep learning compilers. It consists of three main components: the RDU Sampler for selecting only 10% of tensor programs using representativeness, diversity, and uncertainty to reduce data collection costs while preserving accuracy; a Mamba-based cost model for efficient long-range dependency capture with reduced parameterization; and a continuous knowledge distillation approach for progressive knowledge transfer across hardware platforms. The paper reports that on mainstream DL models for CPU and GPU, TCL achieves 16.8x and 12.48x faster tuning time, and 1.20x and 1.13x lower inference latency compared to Tenset-MLP.

Significance. If the empirical results hold under rigorous validation, TCL could meaningfully advance DL compiler optimization by reducing the high costs of offline data collection and improving transferability across hardware. The combination of active learning sampling, lightweight sequence modeling via Mamba, and continual distillation targets practical bottlenecks in auto-tuning, with potential for broader adoption if the speedups and latency gains prove robust.

major comments (2)
  1. [Abstract] The central tuning-time claims (16.8× on CPU, 12.48× on GPU) rest on the RDU sampler's 10% selection preserving near-original cost-model accuracy. The abstract asserts this but supplies no quantitative bounds (MAPE, Kendall-τ, or similar) on held-out programs or unseen hardware platforms, nor an ablation isolating sampler-induced ranking errors from the Mamba and distillation components. Without these, it is impossible to confirm that the reported latency gains are not eroded by mis-ranked candidates.
  2. [Experiments] The abstract presents concrete average speedups and latency reductions but omits all details on statistical significance, run-to-run variance, data splits, or ablation controls. This absence directly affects the soundness of the cross-hardware performance assertions and prevents assessment of whether the gains are reliable or platform-specific artifacts.
minor comments (1)
  1. [Abstract] The baseline 'Tenset-MLP' is referenced without a brief description or citation; adding one sentence would improve readability for readers unfamiliar with the prior work.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the thoughtful and constructive report. The two major comments identify areas where additional quantitative detail and statistical rigor would strengthen the presentation of our results. We address each point below and commit to revisions that directly incorporate the requested information without altering the core claims or methodology.

read point-by-point responses

  1. Referee: [Abstract] The central tuning-time claims (16.8× on CPU, 12.48× on GPU) rest on the RDU sampler's 10% selection preserving near-original cost-model accuracy. The abstract asserts this but supplies no quantitative bounds (MAPE, Kendall-τ, or similar) on held-out programs or unseen hardware platforms, nor an ablation isolating sampler-induced ranking errors from the Mamba and distillation components. Without these, it is impossible to confirm that the reported latency gains are not eroded by mis-ranked candidates.

    Authors: We agree that the abstract would be improved by explicit quantitative bounds on the RDU sampler. The current abstract summarizes end-to-end outcomes but does not report MAPE, Kendall-τ, or a dedicated isolation ablation. In the revised manuscript we will add a concise statement to the abstract citing the sampler's held-out Kendall-τ (reported in Section 4.2) and will insert a new ablation table in the experiments section that isolates the sampler's contribution to final ranking quality and latency from the Mamba cost model and distillation stages. These additions will allow readers to verify that any sampler-induced ranking discrepancies do not materially erode the reported speedups. revision: yes

  2. Referee: [Experiments] The abstract presents concrete average speedups and latency reductions but omits all details on statistical significance, run-to-run variance, data splits, or ablation controls. This absence directly affects the soundness of the cross-hardware performance assertions and prevents assessment of whether the gains are reliable or platform-specific artifacts.

    Authors: We concur that the experiments section would benefit from explicit statistical details. While averages across models are reported, the manuscript does not currently include run-to-run standard deviations, precise data-split descriptions, or expanded ablation controls. In the revision we will add: (i) standard deviations computed over five independent tuning runs per model, (ii) a description of the 80/20 random splits used for cost-model training together with 5-fold cross-validation results, and (iii) additional ablation tables that systematically vary each TCL component while holding the others fixed. These changes will demonstrate consistency across CPU and GPU and rule out platform-specific artifacts. revision: yes

Circularity Check

0 steps flagged

No circularity: empirical comparisons to external baseline

full rationale

The paper's central claims consist of measured speedups (16.8×/12.48× tuning time, 1.20×/1.13× latency) obtained by running TCL against the external Tenset-MLP baseline on mainstream DL models for CPU and GPU. The three enablers (RDU sampler, Mamba cost model, continual distillation) are introduced as engineering choices whose effectiveness is shown via ablation studies and end-to-end experiments; none of the reported quantities is obtained by fitting a parameter to a subset and then relabeling the fit as a prediction, nor is any load-bearing premise justified solely by a self-citation whose content reduces to the present result. The derivation chain therefore remains self-contained against external benchmarks and contains no self-definitional, fitted-input, or self-citation circularity.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

The framework is entirely empirical; it introduces no new mathematical axioms, free parameters beyond standard model hyperparameters, or invented physical entities. All claims rest on experimental validation rather than derivation from first principles.

pith-pipeline@v0.9.0 · 5579 in / 1196 out tokens · 26754 ms · 2026-05-10T15:42:59.851187+00:00 · methodology

discussion (0)

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