arxiv: 2604.13632 · v1 · submitted 2026-04-15 · 🪐 quant-ph

Recognition: unknown

A boldsymbol{2d times d times d} Spacetime Volume Implementation of a Logical S Gate in the Surface Code

Yuga Hirai , Shota Ikari , Yosuke Ueno , Yasunari Suzuki

Authors on Pith no claims yet

Pith reviewed 2026-05-10 13:00 UTC · model grok-4.3

classification 🪐 quant-ph

keywords surface codelogical S gatetwist defect braidingspacetime volumefault tolerancequantum error correctionnearest-neighbor gateslogical error rate

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The pith

A new twist defect braiding protocol implements the logical S gate in the surface code using a spacetime volume of 2d × d × d.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper aims to lower the resource cost of the logical S gate, a component required in many protected quantum operations on the surface code. Earlier braiding-based implementations occupied spacetime volumes of 2d × 2d × d or 2d × 1.5d × d. The authors introduce a compact braiding arrangement together with explicit circuit constructions that use only nearest-neighbor gates on a square lattice and no extra depth beyond standard syndrome extraction. Simulations indicate that the new arrangement reduces the fault distance by one or three yet produces logical error rates comparable to prior methods once the code distance reaches five or more and the physical error rate sits near 10 to the minus three. Lower per-gate overhead of this kind directly affects whether full fault-tolerant algorithms remain practical on hardware with limited qubit count and coherence time.

Core claim

We provide the missing circuit-level implementations of existing logical S-gate methods and propose a novel twist defect braiding protocol that reduces the spacetime volume to 2d × d × d. The protocol is first realized with constant-length non-local gates and then refined to nearest-neighbor two-qubit gates on a square grid without increasing two-qubit gate depth beyond that of standard syndrome extraction circuits. Numerical simulations evaluate fault distances and logical error rates for both existing and proposed methods, showing that although the proposed method reduces the fault distance by one or three, its logical error rates remain comparable to those of existing methods at large d (

What carries the argument

twist defect braiding protocol, which executes the logical S gate by moving and braiding twist defects through a compact 2d × d × d spacetime arrangement

If this is right

The protocol halves the spatial extent in one dimension relative to the common 2d by 2d by d baseline.
Both non-local and nearest-neighbor circuit versions are supplied, each without added two-qubit gate depth beyond syndrome extraction.
Logical error rates stay comparable to prior methods once d reaches 5 or larger at physical error rates near 10 to the minus 3.
The method supplies explicit circuit implementations that were previously unavailable for quantitative fault-distance comparison.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

The reduced volume could permit a higher density of S gates inside the same total spacetime budget of a full algorithm.
The same defect-braiding compaction idea might be adapted to other logical Clifford gates to lower overall resource demands.
Hardware runs on small surface-code patches could directly test whether the simulated error rates persist under device-specific noise.
Combining the protocol with lattice-surgery or other surface-code primitives could produce still lower-overhead universal gate sets.

Load-bearing premise

The numerical simulations of the circuit-level implementation with nearest-neighbor gates accurately capture the true fault distance and logical error rates of the proposed braiding protocol under realistic hardware noise.

What would settle it

A circuit-level simulation or hardware demonstration at code distance d equals 5 and physical error rate p equals 10 to the minus 3 that shows the proposed method's logical error rate clearly exceeding the rate of the 2d by 2d by d baseline would falsify the claim of comparable performance.

Figures

Figures reproduced from arXiv: 2604.13632 by Shota Ikari, Yasunari Suzuki, Yosuke Ueno, Yuga Hirai.

**Figure 1.** Figure 1: shows a rotated surface code. The white and black circles represent data and measurement qubits, respectively. The blue (red) shapes represent the Z (X) stabilizers. The boundaries terminated by the Z (X) stabilizers are called the Z (X) boundaries. The logical Z (X) operator is defined as a chain connecting the two disjoint Z (X) boundaries. To keep the code distance d, i.e., detect any non-trivial Pau… view at source ↗

**Figure 2.** Figure 2: FIG. 2 [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗

**Figure 4.** Figure 4: FIG. 4 [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗

**Figure 6.** Figure 6: FIG. 6 [PITH_FULL_IMAGE:figures/full_fig_p004_6.png] view at source ↗

**Figure 8.** Figure 8: ) back into standard square ones, a requirement imposed by nearest-neighbor connectivity constraints [16]. This transformation introduces additional two-qubit gate depth, making synchronization with other surface code patches difficult [24] and inducing additional idling errors on the data qubits. Furthermore, these rectangular stabilizers exhibit redundant Y-type support on data qubits, rendering both Z… view at source ↗

**Figure 9.** Figure 9: FIG. 9 [PITH_FULL_IMAGE:figures/full_fig_p006_9.png] view at source ↗

**Figure 10.** Figure 10: FIG. 10 [PITH_FULL_IMAGE:figures/full_fig_p006_10.png] view at source ↗

**Figure 11.** Figure 11: FIG. 11 [PITH_FULL_IMAGE:figures/full_fig_p007_11.png] view at source ↗

**Figure 13.** Figure 13: FIG. 13 [PITH_FULL_IMAGE:figures/full_fig_p007_13.png] view at source ↗

**Figure 14.** Figure 14: FIG. 14 [PITH_FULL_IMAGE:figures/full_fig_p008_14.png] view at source ↗

**Figure 15.** Figure 15: FIG. 15 [PITH_FULL_IMAGE:figures/full_fig_p008_15.png] view at source ↗

**Figure 16.** Figure 16: FIG. 16 [PITH_FULL_IMAGE:figures/full_fig_p009_16.png] view at source ↗

**Figure 17.** Figure 17: FIG. 17 [PITH_FULL_IMAGE:figures/full_fig_p011_17.png] view at source ↗

**Figure 18.** Figure 18: FIG. 18 [PITH_FULL_IMAGE:figures/full_fig_p013_18.png] view at source ↗

**Figure 19.** Figure 19: FIG. 19 [PITH_FULL_IMAGE:figures/full_fig_p013_19.png] view at source ↗

**Figure 20.** Figure 20: FIG. 20 [PITH_FULL_IMAGE:figures/full_fig_p014_20.png] view at source ↗

**Figure 21.** Figure 21: FIG. 21 [PITH_FULL_IMAGE:figures/full_fig_p014_21.png] view at source ↗

**Figure 22.** Figure 22: FIG. 22 [PITH_FULL_IMAGE:figures/full_fig_p015_22.png] view at source ↗

read the original abstract

The logical S gate implemented via twist defect braiding in the surface code is one of the major sources of overhead in fault-tolerant quantum computing, since an S-gate correction is required in every logical T-gate teleportation. Existing logical S-gate implementations require spacetime volumes of $2d \times 2d \times d$ or $2d \times 1.5d \times d$, where $d$ is the code distance of the surface code. To the best of our knowledge, their circuit-level implementations have not yet been shown, hindering quantitative comparisons of fault distances and logical error rates. In this work, we provide these missing circuit-level implementations. Additionally, we propose a novel twist defect braiding protocol that reduces the spacetime volume to $2d \times d \times d$. First, we construct an implementation of the proposed method using constant-length non-local gates, and then refine it to utilize only nearest-neighbor two-qubit gates on a square grid, without requiring additional two-qubit gate depth beyond that of standard syndrome extraction circuits. Through numerical simulations, we evaluate the fault distances and logical error rates for both existing and proposed methods. Our results show that, although the proposed method reduces the fault distance by one or three, its logical error rates remain comparable to those of existing methods at large code distances ($d \ge 5$) and at physical error rates near $p = 10^{-3}$. This demonstrates that the proposed method is promising for near-term fault-tolerant quantum computing.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

The paper gives the first circuit-level versions of prior S-gate braiding methods plus a new 2d×d×d protocol whose simulated error rates match the old ones at d≥5 despite a lower fault distance.

read the letter

The main thing to know is that this work supplies the missing circuit constructions for the existing 2d×2d×d and 2d×1.5d×d logical S-gate implementations and adds a new twist-defect braiding protocol that cuts the spacetime volume to 2d×d×d. They first build a version with constant-length non-local gates, then refine it to nearest-neighbor two-qubit gates on a square grid while keeping the two-qubit depth no higher than a standard syndrome extraction round. Numerical Monte Carlo simulations under depolarizing noise then compare fault distances and logical error rates across all three methods. The new protocol drops the fault distance by one or three, yet the logical error rates stay comparable to the prior ones once d reaches 5 and the physical error rate is around 10^{-3}. That is the practical payoff for T-gate teleportation overhead. What the paper does well is turn abstract volume numbers into concrete, simulatable circuits so direct quantitative comparison becomes possible. The side-by-side results are the useful output. The soft spots are limited and acknowledged in the work. The distance reduction is real and means the advantage only appears at moderate-to-large d; at small d the new method would be worse. The entire claim rests on the simulations correctly capturing fault distance and showing no hidden error channels from the nearest-neighbor conversion. If those runs are solid and the minimum-weight logical operators are properly identified, the volume saving holds. This is aimed at researchers who build surface-code compilers or run resource estimates for fault-tolerant circuits. It is the sort of concrete engineering step that helps turn volume claims into actual gate costs. I would send it to peer review because the constructions are explicit and the numerical comparison addresses a real overhead question, even though the simulation details will need checking.

Referee Report

2 major / 1 minor

Summary. The manuscript presents explicit circuit-level implementations of logical S gates via twist defect braiding in the surface code, including existing protocols with spacetime volumes 2d × 2d × d and 2d × 1.5d × d. It proposes a new braiding protocol achieving 2d × d × d volume, first using constant-length non-local gates and then refined to nearest-neighbor two-qubit gates on a square grid without added depth beyond standard syndrome extraction. Numerical Monte Carlo simulations under depolarizing noise are used to evaluate fault distances and logical error rates, claiming that despite a reduction in fault distance by 1 or 3, the logical error rates remain comparable to prior methods for d ≥ 5 at physical error rates near p = 10^{-3}.

Significance. If the numerical results hold under the stated conditions, the reduced spacetime volume would lower overhead for a frequently used gate in fault-tolerant quantum computing (required for every logical T teleportation), with direct relevance to near-term hardware. Strengths include the provision of missing circuit-level constructions for quantitative comparison and the explicit refinement to nearest-neighbor connectivity, which addresses a practical implementation gap.

major comments (2)

[Numerical Simulations] Numerical Simulations section: the central claim of comparable logical error rates at d ≥ 5 and p ≈ 10^{-3} despite reduced fault distance rests on Monte Carlo results, but the manuscript does not specify the procedure for extracting fault distance (e.g., minimum-weight logical operator search versus fitting), the number of shots per data point, or full error model parameters. This prevents verification that the nearest-neighbor refinement introduces no additional error channels or depth that would invalidate the volume or error-rate comparison.
[Circuit Construction] Circuit Construction and Refinement sections: the claim that the nearest-neighbor square-grid version requires 'no additional two-qubit gate depth beyond that of standard syndrome extraction circuits' is load-bearing for the spacetime volume assertion of 2d × d × d. Without explicit depth counts, circuit diagrams, or timing analysis showing how twist defect braiding is scheduled within existing syndrome rounds, it is unclear whether hidden overheads arise that offset the volume reduction.

minor comments (1)

[Abstract] The abstract states 'to the best of our knowledge' regarding prior circuit-level implementations; a brief citation to the specific prior works on twist-defect braiding would strengthen this.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for their thorough review and valuable feedback on our manuscript. We have carefully considered the major comments and will revise the manuscript to provide the requested clarifications and additional details, which we believe will strengthen the presentation of our results.

read point-by-point responses

Referee: Numerical Simulations section: the central claim of comparable logical error rates at d ≥ 5 and p ≈ 10^{-3} despite reduced fault distance rests on Monte Carlo results, but the manuscript does not specify the procedure for extracting fault distance (e.g., minimum-weight logical operator search versus fitting), the number of shots per data point, or full error model parameters. This prevents verification that the nearest-neighbor refinement introduces no additional error channels or depth that would invalidate the volume or error-rate comparison.

Authors: We agree that these details are essential for reproducibility and verification. In the revised manuscript, we will expand the Numerical Simulations section to explicitly describe the procedure for extracting the fault distance (using minimum-weight logical operator search), the number of Monte Carlo shots per data point, and the complete parameters of the depolarizing error model. We confirm that the nearest-neighbor refinement does not introduce additional error channels or depth beyond what is accounted for in the volume calculation. revision: yes
Referee: Circuit Construction and Refinement sections: the claim that the nearest-neighbor square-grid version requires 'no additional two-qubit gate depth beyond that of standard syndrome extraction circuits' is load-bearing for the spacetime volume assertion of 2d × d × d. Without explicit depth counts, circuit diagrams, or timing analysis showing how twist defect braiding is scheduled within existing syndrome rounds, it is unclear whether hidden overheads arise that offset the volume reduction.

Authors: We acknowledge that the current presentation lacks sufficient explicit documentation to fully substantiate this claim. To address this, we will include in the revised manuscript additional figures or appendices with circuit diagrams for the nearest-neighbor implementation and a detailed timing analysis showing the scheduling of the braiding operations. This analysis will demonstrate that the twist defect movements and measurements are performed within the standard syndrome extraction cycles without requiring extra two-qubit gate layers. We have ensured through our construction that the depth remains the same as standard surface code syndrome extraction, preserving the 2d × d × d spacetime volume. revision: yes

Circularity Check

0 steps flagged

No circularity: explicit construction plus independent Monte Carlo simulation

full rationale

The paper derives its central claim via an explicit twist-defect braiding circuit construction (first non-local, then nearest-neighbor square-grid) followed by direct circuit-level Monte Carlo simulation of fault distance and logical error rates under depolarizing noise. These steps are not algebraic reductions, parameter fits renamed as predictions, or self-citation chains; the implementations of both the new 2d×d×d protocol and the prior 2d×2d×d / 2d×1.5d×d methods are newly supplied in the manuscript, and the numerical results are generated from those circuits rather than from any pre-fitted quantities or author-specific ansätze. No load-bearing step collapses to a definition or prior self-result by construction.

Axiom & Free-Parameter Ledger

0 free parameters · 2 axioms · 0 invented entities

The central claim rests on standard surface-code error-correction properties and the validity of the new braiding schedule; no new free parameters, invented entities, or ad-hoc axioms are introduced in the abstract.

axioms (2)

domain assumption Surface codes of distance d can correct up to floor((d-1)/2) errors.
Invoked implicitly when defining logical error rates and fault distance for the implemented gates.
domain assumption Twist defects can be braided to realize the logical S gate.
Relies on prior surface-code literature referenced in the abstract.

pith-pipeline@v0.9.0 · 5599 in / 1596 out tokens · 52348 ms · 2026-05-10T13:00:25.282773+00:00 · methodology

discussion (0)

Reference graph

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Expand the surface code spatially from the X boundary while braiding the twist defects in the middle-bottom to the right-bottom corner
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Braid the twist defects from the middle-top to the 5 /u1D451 /u1D451 2/u1D451 FIG. 7. 3D defect diagram of Bombín’s method. The time goes upward. bottom side, and from the right-bottom to the right-top corner
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