PoSME: Proof of Sequential Memory Execution via Latency-Bound Pointer Chasing with Causal Hash Binding
Pith reviewed 2026-05-10 08:49 UTC · model grok-4.3
The pith
PoSME forces sustained sequential memory steps by chasing data-dependent pointers and binding each write to its own causal hash.
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
Core claim
PoSME achieves three properties through latency-bound pointer chasing over a mutable arena with symbiotic value-hash binding: strict linear enforcement of sequential memory steps, high resistance to time-memory tradeoffs with a formal quadratic space-time lower bound, and an ASIC advantage strictly limited by DRAM random-access latency rather than bandwidth or parallelism.
What carries the argument
Symbiotic binding of each written block's value to its causal hash inside data-dependent pointer chasing over a mutable memory arena.
If this is right
- Each step must complete before the next address is known, enforcing strict sequential execution.
- Time-memory tradeoffs incur at least a tenfold penalty at write density of 4, with quadratic scaling in steps.
- ASIC implementations gain no advantage beyond the inherent DRAM access latency limit.
- The construction requires no trusted setup and directly supports verifiable delay functions.
- The transcript enables authorship attestation and Sybil resistance applications.
Where Pith is reading between the lines
- The quadratic bound could make PoSME suitable for memory-hard sequential proofs in decentralized ledgers where parallelism must be penalized.
- Hardware asymmetry between CPUs and GPUs shown in benchmarks suggests possible use in client puzzles that favor general-purpose processors.
- The mutable arena plus causal binding might extend to verifiable execution traces that tie computation order to physical memory access patterns.
Load-bearing premise
That data-dependent pointer chasing in a mutable arena cannot be parallelized, prefetched, or otherwise optimized to break the latency-bound model or the quadratic space-time bound.
What would settle it
A concrete ASIC or optimized algorithm that completes N steps of PoSME with total time and memory cost growing only linearly rather than quadratically, or with effective latency per step below typical DRAM random-access times.
Figures
read the original abstract
We introduce PoSME (Proof of Sequential Memory Execution), a cryptographic primitive that enforces sustained sequential computation via latency-bound pointer chasing over a mutable arena. Each step reads data-dependent addresses, writes a block whose value and causal hash are mutually dependent (symbiotic binding), and chains the result into a global transcript. This yields three properties: (1) strict linear sequential memory-step enforcement, (2) high time-memory trade-off resistance (a tenfold penalty at a write density of 4, with a formal space-time lower bound that scales quadratically with the number of steps), and (3) a tight ASIC advantage bound by DRAM random-access latency rather than bandwidth. Benchmarks across 17 CPU platforms and 4 GPU architectures demonstrate that hash computation is under 3.5 percent of step cost and GPU hardware is 14 to 19 times slower than a consumer CPU. POSME requires no trusted setup and provides a foundation for verifiable delay, authorship attestation, and Sybil resistance.
Editorial analysis
A structured set of objections, weighed in public.
Axiom & Free-Parameter Ledger
free parameters (1)
- write density parameter
axioms (2)
- domain assumption Pointer chasing remains strictly latency-bound under data-dependent addressing
- ad hoc to paper Symbiotic binding between block value and causal hash prevents all non-sequential shortcuts
invented entities (1)
-
symbiotic binding
no independent evidence
Reference graph
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