A Novel Low-Power Cache Architecture Based on 6-Transistor SRAM Cells

Ceyda Elcin Kaya; Naser Khatti Dizabadi

arxiv: 2604.20176 · v1 · submitted 2026-04-22 · 💻 cs.AR · cs.ET

A Novel Low-Power Cache Architecture Based on 6-Transistor SRAM Cells

Naser Khatti Dizabadi , Ceyda Elcin Kaya This is my paper

Pith reviewed 2026-05-09 23:48 UTC · model grok-4.3

classification 💻 cs.AR cs.ET

keywords low-power SRAM cache6T SRAM cellsleakage powerstacking effectserial interconnectioncache architecturehold operation

0 comments

The pith

Connecting adjacent 6T SRAM cells in series within cache columns reduces leakage power via the stacking effect.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper introduces a cache architecture that reconfigures standard 6-transistor SRAM cells into a serial connection along each column. The goal is to exploit the stacking effect to lower leakage current during hold operations without adding transistors to the memory cells. Adjustments to the addressing and sensing structures are required to accommodate the new topology. Simulations using Keysight ADS demonstrate that leakage power decreases compared to conventional SRAM setups. A sympathetic reader would care because leakage power dominates energy consumption in modern cache memories as process nodes shrink.

Core claim

The paper claims that reconfiguring adjacent 6T SRAM cells in a serial topology within columns suppresses leakage current by the stacking effect. This requires changes to column organization and readout path. Transient simulations confirm lower leakage power than the conventional interconnection scheme while using unmodified 6T cells.

What carries the argument

The serial topology of adjacent cells in a column, which creates a stacked transistor configuration to reduce subthreshold leakage during hold mode.

Load-bearing premise

Reconfiguring adjacent cells into a serial topology can be achieved without causing substantial increases in access time, area, or reliability problems.

What would settle it

If prototype measurements reveal that the serial configuration increases access latency beyond acceptable thresholds or fails to reduce leakage in silicon, the architecture's advantages would be disproven.

Figures

Figures reproduced from arXiv: 2604.20176 by Ceyda Elcin Kaya, Naser Khatti Dizabadi.

**Figure 2.** Figure 2: Conventional 6T SRAM cell 5 [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗

**Figure 3.** Figure 3: Proposed cache architecture especially when the cells are in hold mode and several transistors remain off. Consequently, the leakage current of the proposed structure is expected to be lower than that of the conventional architecture. To realize the proposed concept in practice, several additional control and support circuits are required, as shown in Figure ??. The bit lines are connected to PMOS device… view at source ↗

**Figure 4.** Figure 4: Main idea of the proposed SRAM cell 7 [PITH_FULL_IMAGE:figures/full_fig_p007_4.png] view at source ↗

**Figure 5.** Figure 5: Output voltages of the lower core in the proposed SRAM cell [PITH_FULL_IMAGE:figures/full_fig_p009_5.png] view at source ↗

**Figure 6.** Figure 6: Total current drawn by the proposed SRAM cell [PITH_FULL_IMAGE:figures/full_fig_p009_6.png] view at source ↗

**Figure 7.** Figure 7: Simulated bit lines of the proposed SRAM cell [PITH_FULL_IMAGE:figures/full_fig_p009_7.png] view at source ↗

**Figure 8.** Figure 8: Simulated data line, cell output, and word-line signal of the proposed SRAM topology [PITH_FULL_IMAGE:figures/full_fig_p010_8.png] view at source ↗

read the original abstract

This paper presents a low-power cache architecture based on the series interconnection of conventional 6-transistor static random-access memory (6T SRAM) cells. The proposed approach aims to reduce leakage power in SRAM-based cache memories without increasing the transistor count of the memory cell itself. In the proposed architecture, adjacent cells within a column are reconfigured in a serial topology, thereby exploiting the stacking effect to suppress leakage current, particularly during hold operation. This architectural modification requires corresponding changes to the addressing and sensing structure of the cache, including adjustments to the column organization and readout path. To evaluate the proposed method, transient simulations were carried out using Keysight ADS. The simulation results show that the proposed architecture reduces leakage power compared with the conventional SRAM interconnection scheme while preserving the use of standard 6T SRAM cells.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

The paper reconfigures 6T SRAM cells into series columns to cut leakage via stacking but reports only that one metric from ADS simulations.

read the letter

The main takeaway is that the authors wire adjacent 6T SRAM cells in series down each cache column to exploit the stacking effect for lower hold leakage, while keeping the cell transistor count unchanged and adjusting the addressing and sensing logic accordingly. Transient simulations in Keysight ADS are said to confirm a leakage drop versus the standard parallel column scheme. That is the extent of the reported result. The idea is straightforward and stays within conventional cells, which is a practical choice compared with proposals that add sleep transistors or redesign the bitcell itself. The column-level change is presented as the novelty, and the abstract frames it as a direct way to apply stacking without new devices. The simulation approach is also standard and externally verifiable. The clear limitation is that nothing is shown about read or write timing, bitline capacitance, sense-amplifier behavior, static noise margin, or write margin under the new topology. A serial column arrangement necessarily lengthens the discharge path or adds resistance during access, so the assumption that these adjustments incur no meaningful speed or reliability cost is untested. The stress-test note correctly flags this gap; the provided abstract gives no counter-evidence. Without those numbers the power claim stands alone and cannot be weighed against performance. This work would interest circuit designers focused on leakage in embedded caches or mobile SoCs, where even modest hold-power savings matter if the speed penalty stays small. A reading group could usefully discuss the topology change and what additional simulations would be needed. I would not cite it in its current form because the evaluation is too narrow. It should go to peer review because the core claim is simple to check with standard tools and the missing data are straightforward to add.

Referee Report

2 major / 1 minor

Summary. The paper proposes a low-power cache architecture that interconnects standard 6T SRAM cells in a serial topology within columns to exploit the stacking effect for leakage reduction during hold operations. Modifications to addressing and sensing structures are required, and transient simulations in Keysight ADS are used to demonstrate lower leakage power relative to conventional parallel SRAM schemes while preserving the use of unmodified 6T cells.

Significance. If the serial reconfiguration can be shown to incur negligible penalties in access time, sense margins, and area, the approach would provide a practical leakage-reduction technique for SRAM caches that avoids custom cell designs or additional transistors. This would be relevant for energy-constrained processors. The current manuscript, however, supplies no quantitative leakage numbers, no performance metrics, and no technology-node details, so the practical significance cannot yet be assessed.

major comments (2)

[Abstract] Abstract: the claim that leakage power is reduced is presented without any numerical values, reduction percentages, supply voltage, temperature, or technology node; this absence prevents verification of the magnitude of the improvement.
[Evaluation] Evaluation (simulation results): only hold-mode leakage is simulated; no data or discussion is provided on read discharge path resistance, bitline capacitance, access time, static noise margin, or write margin after the serial column reorganization and sensing adjustments. These metrics are load-bearing for the central claim that the architecture remains functionally viable.

minor comments (1)

[Abstract] The abstract would be strengthened by including at least one quantitative result (e.g., leakage reduction factor) and a brief statement of the simulation conditions.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive and detailed feedback on our manuscript. We agree that strengthening the quantitative presentation and broadening the evaluation metrics will improve the clarity and impact of the work. Below we respond point-by-point to the major comments and outline the revisions we will make.

read point-by-point responses

Referee: [Abstract] Abstract: the claim that leakage power is reduced is presented without any numerical values, reduction percentages, supply voltage, temperature, or technology node; this absence prevents verification of the magnitude of the improvement.

Authors: We acknowledge that the abstract currently states the leakage reduction only qualitatively. Although the body of the manuscript reports transient simulation results from Keysight ADS that demonstrate lower leakage relative to the conventional parallel scheme, we agree that explicit numerical values are needed for immediate assessment. In the revised version we will update the abstract to include the observed leakage reduction percentage, the supply voltage, temperature, and technology node used in the simulations. revision: yes
Referee: [Evaluation] Evaluation (simulation results): only hold-mode leakage is simulated; no data or discussion is provided on read discharge path resistance, bitline capacitance, access time, static noise margin, or write margin after the serial column reorganization and sensing adjustments. These metrics are load-bearing for the central claim that the architecture remains functionally viable.

Authors: The referee is correct that the present evaluation focuses on hold-mode leakage to illustrate the stacking-effect benefit. We recognize that read and write performance metrics are essential to confirm that the serial column organization and modified sensing do not compromise functionality. In the revised manuscript we will add simulations and discussion of read discharge path resistance, bitline capacitance, access time, static noise margin, and write margin to substantiate that the architecture remains viable. revision: yes

Circularity Check

0 steps flagged

No circularity: architecture proposal validated by external simulation

full rationale

The paper proposes reconfiguring adjacent 6T SRAM cells into a serial column topology to exploit stacking for leakage reduction during hold, with corresponding changes to addressing and sensing. Evaluation consists of transient simulations in Keysight ADS comparing leakage power to the conventional parallel scheme. No equations, fitted parameters, self-citations, or derivations are present that reduce the central claim to its own inputs by construction. The result is an empirical simulation outcome rather than a self-referential loop, making the derivation self-contained against external circuit simulation benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

The work builds on conventional 6T SRAM cells and known stacking effect in CMOS circuits; no new free parameters are fitted, no additional axioms beyond standard electronics, and no new entities are postulated.

pith-pipeline@v0.9.0 · 5436 in / 1184 out tokens · 48282 ms · 2026-05-09T23:48:59.451727+00:00 · methodology

discussion (0)

Reference graph

Works this paper leans on

16 extracted references · 16 canonical work pages

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Abbasian, M

E. Abbasian, M. Gholipour, Design of a schmitt-trigger-based 7t sram cell for variation resilient low-energy consumption and reliable internet of things applications, AEU - International Journal of Electronics and Communica- tions 138 (2021) 153899. doi:https://doi.org/10.1016/j.aeue.2021.153899. URLhttps://www.sciencedirect.com/science/article/pii/S14348...

work page doi:10.1016/j.aeue.2021.153899 2021

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T. Kim, S. Manisankar, Y . Chung, A novel 8t cell-based subthreshold static ram for ultra-low power platform applications, Electronics 9 (6) (2020). doi:10.3390/electronics9060928. URLhttps://www.mdpi.com/2079-9292/9/6/928 10

work page doi:10.3390/electronics9060928 2020

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Tu, J.-Y

M.-H. Tu, J.-Y . Lin, M.-C. Tsai, C.-Y . Lu, Y .-J. Lin, M.-H. Wang, H.- S. Huang, K.-D. Lee, W.-C. Shih, S.-J. Jou, C.-T. Chuang, A single- ended disturb-free 9t subthreshold sram with cross-point data-aware write word-line structure, negative bit-line, and adaptive read operation timing tracing, IEEE Journal of Solid-State Circuits 47 (6) (2012) 1469–14...

work page doi:10.1109/jssc.2012.2187474 2012

[4] [4]

Najafi, B

D. Najafi, B. Ebrahimi, A low-leakage 6t sram cell for in-memory computing with high stability, in: 2021 29th Iranian Conference on Electrical Engineer- ing (ICEE), 2021, pp. 98–102. doi:10.1109/ICEE52715.2021.9544224

work page doi:10.1109/icee52715.2021.9544224 2021

[5] [5]

Bikki, M

P. Bikki, M. K. R. T, M. Annapurna, S. Vujwala, Analysis of low power sram design with leakage control techniques, in: 2019 TEQIP III Sponsored International Conference on Microwave Integrated Cir- cuits, Photonics and Wireless Networks (IMICPW), 2019, pp. 400–404. doi:10.1109/IMICPW.2019.8933178

work page doi:10.1109/imicpw.2019.8933178 2019

[6] [6]

C. Duan, A. J. Gotterba, M. E. Sinangil, A. P. Chandrakasan, Energy- efficient reconfigurable sram: Reducing read power through data statis- tics, IEEE Journal of Solid-State Circuits 52 (10) (2017) 2703–2711. doi:10.1109/JSSC.2017.2731814

work page doi:10.1109/jssc.2017.2731814 2017

[7] [7]

Grover, G

A. Grover, G. S. Visweswaran, C. R. Parthasarathy, M. Daud, D. Turgis, B. Giraud, J.-P. Noel, I. Miro-Panades, G. Moritz, E. Beign ´e, P. Flatresse, P. Kumar, S. Azmi, A 32 kb 0.35–1.2 v, 50 mhz–2.5 ghz bit-interleaved sram with 8 t sram cell and data dependent write assist in 28-nm utbb-fdsoi cmos, IEEE Transactions on Circuits and Systems I: Regular Pap...

work page doi:10.1109/tcsi.2017.2705116 2017

[8] [8]

Abbasian, F

E. Abbasian, F. Izadinasab, M. Gholipour, A reliable low standby power 10t sram cell with expanded static noise margins, IEEE Transactions on Circuits and Systems I: Regular Papers 69 (4) (2022) 1606–1616. doi:10.1109/TCSI.2021.3138849

work page doi:10.1109/tcsi.2021.3138849 2022

[9] [9]

Lorenzo, R

R. Lorenzo, R. Pailly, Single bit-line 11t sram cell for low power and improved stability, IET Computers & Digital Techniques 14 (3) (2020) 114–

work page 2020

[10] [10]

Charge equalisation for series-connected LiFePO4 battery strings,

arXiv:https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/iet- cdt.2019.0234, doi:https://doi.org/10.1049/iet-cdt.2019.0234. URLhttps://ietresearch.onlinelibrary.wiley.com/doi/abs/10.1049/iet-cdt.2019.0234 11

work page doi:10.1049/iet- 2019

[11] [11]

Usham, M

D. Usham, M. Bansal, Low power, highly stable and enhanced read speed 7t sram, in: 2022 International Conference on Automation, Computing and Renewable Systems (ICACRS), 2022, pp. 162–167. doi:10.1109/ICACRS55517.2022.10029285

work page doi:10.1109/icacrs55517.2022.10029285 2022

[12] [12]

Sanvale, N

P. Sanvale, N. Gupta, V . Neema, A. P. Shah, S. K. Vishvakarma, An improved read-assist energy efficient single ended p-p-n based 10t sram cell for wireless sensor network, Microelectronics Journal 92 (2019) 104611. doi:https://doi.org/10.1016/j.mejo.2019.104611. URLhttps://www.sciencedirect.com/science/article/pii/S0026269219303684

work page doi:10.1016/j.mejo.2019.104611 2019

[13] [13]

T. W. Oh, H. Jeong, K. Kang, J. Park, Y . Yang, S.-O. Jung, Power- gated 9t sram cell for low-energy operation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (3) (2017) 1183–1187. doi:10.1109/TVLSI.2016.2623601

work page doi:10.1109/tvlsi.2016.2623601 2017

[14] [14]

W. Gul, M. Shams, D. Al-Khalili, Sram cell design challenges in modern deep sub-micron technologies: An overview, Micromachines 13 (8) (2022)

work page 2022

[15] [15]

doi:10.3390/mi13081332

work page doi:10.3390/mi13081332

[16] [16]

Safaryan, M

K. Safaryan, M. Bazikyan, F. Aslikyan, S. Harutyunyan, G. Hakobyan, A. Petrosyan, Design of low leakage sram bitcell, in: 2019 IEEE 39th Inter- national Conference on Electronics and Nanotechnology (ELNANO), 2019, pp. 245–248. doi:10.1109/ELNANO.2019.8783371. 12

work page doi:10.1109/elnano.2019.8783371 2019